Electrically driven mid-submicrometre pixelation of InGaN micro-light-emitting diode displays for augmented-reality glasses

InGaN-based blue light-emitting diodes (LEDs), with their high efficiency and brightness, are entering the display industry. However, a significant gap remains between the expectation of highly efficient light sources and their experimental realization into tiny pixels for ultrahigh-density displays for augmented reality. Herein, we report using tailored ion implantation (TIIP) to fabricate highly efficient, electrically-driven pixelated InGaN micro-LEDs (μLEDs) at the mid-submicrometre scale (line/space of 0.5/0.5 μm), corresponding to 8,500 pixels per inch (ppi) (RGB). Creating a laterally confined non-radiative region around each pixel with a controlled amount of mobile vacancies, TIIP pixelation produces relatively invariant luminance, and high pixel distinctiveness, at submicrometre-sized pixels. Moreover, with the incomparable integration capability of TIIP pixelation due to its planar geometry, we demonstrate 2,000 ppi μLED displays with monolithically integrated thin-film transistor pixel circuits, and 5,000 ppi compatible core technologies. We expect that the demonstrated method will pave the way toward high-performance μLED displays for seamless augmented-reality glasses. Submicrometre-sized InGaN-based light-emitting diodes are fabricated by tailored ion implantation. The devices are free from electrical leakage and show a luminance of 7,440 nit at 4.9 A cm−2 even at the line/space scale of 0.5/0.5 μm (= 8,500 ppi).

O wing to their inherent high efficiency, brightness and stability, inorganic III-V μLEDs are being evaluated in next-generation displays for a wide variety of applications, including high-dynamic-range wall displays/televisions/ tablets 1-3 , long-use smart watches 4 , high-brightness heads-up displays 5 and high-brightness/resolution augmented-reality (AR) glasses 6,7 . Notably, with the assistance of pick-and-place technologies for RGB chips (R: AlGaInP; G and B: InGaN), μLED televisions are an appealing application due to their superior image quality. Micro-LEDs also have applications in the AR glasses industry, although this market is just developing. To fully experience seamless (indoor/outdoor) and realistic (field of view ±20°) merging of virtual and physical information, both high dynamic brightness range (from 1 to >10 4 nit, where 1 nit = 1 cd m −2 ) and high resolution (>full high definition: 1,920 × 1,080 pixels) are required while maintaining small form-factor (0.5 inch diagonal or less) microdisplays. Inorganic μLEDs can fulfil these strict requirements, given the lower brightness of OLEDs (organic LEDs) 8 and the lower contrast of liquid-crystal-on-silicon technology 9 . For their realization into microdisplays, the key challenge is to achieve efficient small-sized pixelation at the submicrometre dimension.
Pixelation refers to the formation of an array of light emitters (pixels) that can be distinctively controlled without cross-talk between neighbours. Mesa etching, which physically removes p-GaN and multiple quantum wells (MQWs) for electrical contact at the n-GaN surface, has long been used for making single-LED devices and is commonly regarded as a pixelation technique for next-generation μLEDs. However, non-optimized mesa etching exposes any damaged surface in the active region, which could lead to much greater non-radiative surface recombination with a decreasing pixel size (<10 μm including submicrometre sizes) 10,11 , thus significantly reducing the efficiency. Surface-passivation techniques or core-shell structures have been used to reduce surface recombination. In particular, core-shell structures (n-GaN inner core/MQW outer core/p-GaN shell) based on selective area growth can achieve small-sized, efficient pixelation 12,13 that yields a high internal quantum efficiency (IQE) of ~30% for blue light at a diameter of ~1 μm (ref. 14 ). However, core-shell structures are formed by a bottom-up approach, which inevitably introduces compositional variation and challenges in controlling wafer-scale uniformity; these issues result in electroluminescence (EL) spectral broadening. Moreover, integration into pixel-driven thin-film transistors (TFTs) is difficult because of three-dimensional (3D) geometry-related process issues such as poor step coverage. Therefore, a new pixelation strategy is needed to achieve both the high efficiency of submicrometre-scale devices and their easy integration into pixel-driving circuitry.
Herein, we report the use of TIIP to fabricate highly efficient, electrically-driven pixelated InGaN μLEDs at the midsubmicrometre scale (line/space of 0.5/0.5 μm), corresponding to 8,500 ppi (RGB). This technique exploits ion implantation (IIP) of a small-thickness pixelation mask at ~100 °C using heavy ionic species with a tilt angle of 0°, at a low energy and dose, with their pixelation mechanism revealed. Furthermore, we describe the monolithic integration of TIIP pixelation with low-temperature polysilicon (LTPS) pixel circuits to demonstrate 2,000 ppi (pentile) display prototypes and 5,000 ppi compatible core technologies including quantum dot colour converters (QD C/Cs). Figure 1 illustrates two different pixelation schemes, that is, mesa etching and IIP on InGaN-based μLEDs formed on silicon Electrically driven mid-submicrometre pixelation of InGaN micro-light-emitting diode displays for augmented-reality glasses substrates ( Supplementary Fig. 1a). Mesa etching is typically used in the μLED industry, but a number of etched surfaces at light-emitting quantum wells are exposed. Without elaborate surface passivation, this should create substantial non-radiative recombination centres that significantly decrease efficiency, particularly at the submicrometre scale because of an increased surface-to-volume ratio (Fig. 1a). By contrast, IIP can achieve planar-geometry pixelation without needing to expose any surfaces (Fig. 1b,c). Despite these advantages, micrometre-sized pixelation by IIP is highly challenging. We investigated the TIIP parameters for a number of implantation conditions and pixel sizes using fluorescence photoluminescence (PL) microscopy (Supplementary Fig. 2a-z and  Supplementary Table 1). The non-TIIP condition causes significant lateral spreading of As + under the implantation mask, called undermask penetration (Figs. 1b and 2a), whereby an unintentionally produced shallow As + profile exists near the surface of the GaN LEDs below the implantation mask. This undermask penetration can be notably reduced by adjusting the TIIP parameters (Figs. 1c and 2b). TIIP spatially confines the implanted region precisely, with minimal lateral spreading (Fig. 1c). A thin implantation mask thickness is the critical parameter for achieving optimal TIIP (Supplementary Fig. 2). Using a 0° tilt angle and heavier ions, including Ar + or Kr + , is also beneficial. A minimal ion energy and dose should be used because high values degrade the pixelation contrast. The ion energy is more influential than fluence. Lateral spreading with non-TIIP and TIIP is supported by high-resolution two-dimensional (2D) secondary ion mass spectrometry (SIMS) analyses of As + -implanted InGaN LEDs (Fig. 2a,b, respectively). Both shallow and deep ion profiles contribute to the luminescence quenching of the MQWs. Similar As + profiles were observed using time-of-flight SIMS ( Supplementary Fig. 3).

Submicrometre pixelation by IIP: suppressing lateral straggling
The lateral spreading of implanted ions can be explained by ion scattering [15][16][17] and lateral channelling 18-21 effects (Fig. 1d). When incident ions (projectiles) strike the implantation mask, they experience elastic nuclear scattering and inelastic electron scattering. In the low-energy regime (5-50 keV) used in this research, elastic nuclear scattering is the dominant scattering mechanism, causing significant angular deflections of the projectiles from their original pathways after collision. Most projectiles are backscattered near the top of the mask by nuclear stopping and some ions are scattered Inset, corresponding atomic arrangement of MQWs with sidewall surface defects working as abundant non-radiative recombination centres. Luminance weakens with decreasing pixel size (right). b, Ion-implanted 2D structure, where imperfect pixelation (non-TIIP) parameters result in significant ion scattering and lateral channelling to create some point defects at MQWs below the photoresist mask (left). Luminance is also weak at small-sized pixels (right). c, Ion-implanted 2D structure, where tailored or optimized pixelation parameters yield minimized lateral damage below the mask (left). Luminance is strong even at the submicrometre pixel size (right). d, Lateral penetration of implanted ions below the mask via ion scattering at the edge of the implantation mask and lateral channelling. e, Generation of vacancies depending on the implantation temperature.
from the mask edge. Once an ion is scattered from the mask into air, it should travel in a straight line until it re-enters the GaN LED structure (Fig. 1d). This scattering by uncontrolled particles is known in the complementary metal oxide semiconductor (CMOS) industry as the well-proximity effect and results in an undesirable threshold voltage shift of transistors [15][16][17] . The exact entry point depends on the position at which the ion exits the mask and its direction of motion. The former can be solved by reducing the mask thickness, whereas the latter can be solved by using vertically incident, heavy-mass ions in the optimal ranges of energy and fluence. We believe that ions re-entering the LEDs are easily coupled to lateral channelling (Fig. 1d), which finally results in significant lateral spreading in the shallow (near-surface) region. Note that an abnormal lateral spread for 4H-SiC has been predicted due to lateral channelling through <11-20> axial channels 20,21 . Owing to the structural similarity between GaN and 4H-SiC, and the wide angular distribution of scattered ions, significant lateral channelling is therefore expected. This can be minimized by using a thin mask and a non-tilted projectile incidence (a tilt angle of 0°) while keeping the energy and fluence as low as possible, that is, about 1-50 keV and 10 12 -10 13 cm −2 , respectively. Finally, mobile vacancies generated by implanted ions can cause further spatial luminescence quenching, which should be minimized for accurate spatial pixelation. The number of mobile vacancies for a given implantation energy and dose is minimized at an implantation temperature, T IIP , of ~100 °C (Fig. 1e), as discussed below.
nitride is a mechanically strong material. Therefore, in contrast to other semiconductor materials such as silicon, it is very difficult to induce structural damage by ion bombardment. We use X-ray diffraction (XRD) and transmission electron microscopy (TEM) to examine the microstructure. Argon-ion IIP at 1 × 10 15 atoms per cm 2 on our GaN LED epitaxial structures did not generate any serious structural changes, such as stacking faults or dislocations, as revealed by dark-field TEM images ( Supplementary Fig. 1b). With As + implantation at 1 × 10 14 atoms per cm 2 , only a slight peak broadening was observed in the XRD (Fig. 2c), and neither a shift in the AlGaN and InGaN satellite peaks nor shoulder peaks 22 was observed. These results suggest that a typical fluence would generate mostly point defects, including single-point defects and their defect complexes, forming deep-trap levels existing between conduction band minimum (E c ) and valence band maxium (E v ). Our deep-level transient spectroscopy (DLTS) measurements reveal two important features. First, the peaks (E c − 0.13 eV, E c − 0.07 eV, and E v + 0.09 eV) observed for the non-implanted LEDs attributed to activated donors and acceptors (inset of Fig. 2d and Supplementary Fig. 4a) disappear with increasing As + dose ( Fig. 2d and Supplementary  Fig. 4b,c). We assume that IIP deactivates Mg dopants in p-GaN, possibly by compensation, and some silicon dopants in n-GaN while generating deep traps, thereby forming an undoped region of high electrical resistivity. We measured substantial enhancement of resistivity after N + IIP ( Supplementary Fig. 1c). Second, the generated deep traps are only assigned to E c − 0.7 eV ( Supplementary Fig. 4d). Luminescence quenching of ion-implanted GaN MQWs has previously been studied using depth-profiled cathodoluminescence (CL) 23 . Both band-edge emission and the yellow luminescence band were strongly quenched even at relatively low-dose (10 12 -10 14 cm −2 ) ion bombardment, suggesting that enough vacancies (~5 × 10 19 cm −3 ) were created with the low dose. Importantly, the CL quenching depth of ~700 nm was well beyond the depth of ion bombardment (Rp + 3ΔRp, ~450 nm) estimated by collision simulation, where Rp and ∆Rp are the projected range and the straggle, respectively. This was attributed to the high mobility of created vacancies causing them to diffuse downward to yield further quenching 23,24 . These observations on the quenching of GaN CL are in good agreement with our experiments. In Supplementary Fig. 2, apparent luminescence quenching is evident at relatively low doses (>2 × 10 12 cm −2 ) even though all of the detectable implanted ions appear to locate above the MQWs (Fig. 2a,b). Notably, even near-surface implantation can affect the luminescence, which explains the low-and high-contrast pixelation in non-TIIP and TIIP (Fig. 1b,c,e).
The number of IIP-induced vacancies is correlated with the implantation temperature (Fig. 1e). It is reasonable that lattice damage monotonically decreases with increasing implantation temperature. However, positron annihilation spectroscopy studies have revealed that the number of induced vacancies in 4H-SiC is minimal at an implantation temperature of ~100 °C (ref. 25 ). This might occur via a dynamic or in situ annealing process at this temperature. We observe similar temperature dependence for TIIP: the PL intensity of submicrometre-sized pixels is improved at an implantation temperature of ~100 °C ( Supplementary Fig. 2y,z).

Demonstration of tIIP pixelation
We verify the excellence of TIIP pixelation by experiment (in this and the following section) and by simulation ( Supplementary  Information). A 200-nm-thick Ti mask is formed under TIIP conditions of Ar + implantation at 100 °C, a tilt angle of 0°, an energy of 5 keV and a dose of 2 × 10 12 cm −2 . PL microscopic images are displayed for various pixel densities (300-8,500 ppi) in Fig. 3a and Supplementary Fig. 5. Both pixel contrast and intrapixel uniformity are well maintained even at 8,500 ppi (RGB), which corresponds to the subpixel with a line/space of 0.5/0.5 μm. Also, TIIP pixelation yields four distinctive different-sized subpixels (2,400, 4,800, 6,600 and 8,500 ppi (RGB)) in series (marked by the dotted pink rectangle in Fig. 3b). CL spectra confirm a relative preservation of the integrated CL intensity ratio (I 8,500 ppi /I 300 ppi ) of ~20% (Fig. 3c). A single peak at 390 nm in the spectra originates from superlattices included for film-stress optimization in our LED epilayer. The EL characteristics of TIIP pixelation for various pixel densities are displayed in Fig. 3d under flipped architecture (FA) (Supplementary Figs. 6a, 7a and 8d). Figure 3d clearly shows that the luminance is well-maintained with decreasing pixel size. The EL luminance for TIIP pixelation is 14,290 and 55,835 nit at 4,800 and 300 ppi, respectively, at a current density of 4.9 A cm −2 . More importantly, the TIIP-pixelated LEDs are intrinsically invulnerable to misalignment-induced electrical leakage due to the absence of an n-GaN surface opening, which should facilitate their fabrication for ultrahigh-density μLEDs (Supplementary Fig. 9). This enables the fabrication of EL devices up to 8,500 ppi with a luminance of 7,440 nit at 4.9 A cm −2 . Therefore, the PL pattern in Fig. 3b can be reproduced well with an EL pattern (inset of Fig. 3d). This is an important practical advantage of TIIP pixelation for fabricating high-pixel-density displays for AR glasses.
The observed decrease in CL/EL intensity with decreasing pixel size needs to be further optimized by determining the TIIP conditions that minimize the lateral penetration of generated deep levels, as discussed in first and second sections. Assuming the lateral confinement of deep levels with a modified Shockley-Read-Hall model (https://dynamic.silvaco.com/), we numerically calculate the current flow, radiative recombination and IQE of an ideal TIIP pixelation ( Supplementary Fig. 7). The calculated IQE ratios (I 12,000 ppi /I 300 ppi ) are 79.2 and 89.6% at a current density of 8 A cm −2 for deep-level densities of 6 × 10 14 and 4 × 10 17 cm −3 , respectively ( Supplementary Fig. 7f). This means that the ideal TIIP can potentially achieve very high IQE pixelation even at a very small subpixel size. Regarding mesa pixelation, the importance of the surface recombination velocity, especially at a small pixel size, is emphasized for reference ( Supplementary Fig. 6). Calculation details are given in the Supplementary Information.

Integration of tIIP pixelation into tFt pixel circuits and QD C/Cs
In this section, we fully demonstrate the high integration capability of TIIP-pixelated LEDs with driving circuitry and QD C/Cs, as detailed in the Methods section. The following TIIP conditions are used: an implantation mask of a 200-nm-thick Ti patterned layer, Ar + ions, a tilt angle of 0° and an energy/dose of 5 keV/2 × 10 12 atoms per cm 2 . Owing to the planar geometry, TIIP pixelation is readily incorporated via monolithic or bonding integration into any high-resolution pixel-driving circuits in high-ppi μLED displays. For example, two-transistor/one-capacitor pixel circuits based on LTPS are fabricated monolithically on a TIIP/charge-blocking layer (CBL) structure ( Supplementary Fig. 8b). During the fabrication of LTPS-TFTs, keeping the dehydrogenation temperature of hydrogenated amorphous silicon (a-Si:H) to be less than 500 °C is a key requirement for preventing the performance degradation of InGaN LEDs caused by p-GaN deactivation (see Methods). Figure 4a,b presents TIIP/CBL-pixelated LEDs operated by 300/600/2,000 ppi LTPS-TFTs. The 2,000 ppi (pentile) LTPS-TFTs have a width/length (W/L) of 2/2 μm (Supplementary Fig. 10a). Furthermore, we verify the transfer (drain-source current versus the drain-source voltage (I ds -V ds )) characteristics of the p-Si TFT even at a W/L of 1/1 μm ( Supplementary Fig. 10b), which corresponds to 4,000 ppi (pentile) pixel circuits. However, at a W/L of 0.5/0.5 μm, the LTPS-TFT completely loses transistor characteristics at V ds = −10 V ( Supplementary  Fig. 10c) due to punch-through or short-channel effects whereas normal transfer curves are maintained at V ds = −3 V ( Supplementary  Fig. 10d). We believe that a W/L of 0.5/0.5 μm could be achieved for LTPS-TFTs with process optimization. This means that LTPS-TFTs could potentially be used as 8,000 ppi (pentile)-compatible pixel circuits in AR glasses, which far exceeds the previous estimate of 1,500 ppi (http://www.yole.fr/Reports.aspx). As a potential candidate for high-density, monolithic pixel circuits, we are also investigating GaN-based, normally-off high-electron-mobility transistors on InGaN LEDs, stacks of which can be epitaxially grown in a single round of metal organic chemical vapour deposition 26,27 . For efficient light extraction, FA displays with monolithically integrated LED/TFTs are fabricated using the series of processes illustrated in Supplementary Fig. 8c,d. With the 300 ppi (RGB) pixel TFTs, we demonstrated bright and uniform moving images with a brightness of 25,600 cd m −2 and an external quantum efficiency, or EQE, of 12% ( Fig. 4b and Supplementary Fig. 11 and Supplementary Videos 1 and 2). Moreover, our recent monolithic integration of LTPS-TFTs into the 2,000 ppi (pentile) FA vividly shows a moving black-and-white (BW) checker pattern free of flickering (Supplementary Video 3). Next, by simply modifying the FA, we further demonstrate a resonant-cavity flipped architecture (RCFA) structure exhibiting multimode EL peaks ( Fig. 4c and Supplementary Fig. 12). With a reduced cavity length below 0.5 μm, this type of structure could potentially yield single-mode EL peaks with reduced full-width at half-maximum (FWHM), as described in the Methods.
Finally, the TIIP/CBL LEDs are readily assembled with a QD C/C pattern. For example, we applied the QD C/C for 300 ppi RGB displays ( Fig. 4d and Supplementary Fig. 8e). The full structure of the QD C/C pattern is still under optimization for enhanced spectral purity ( Supplementary Fig. 8f,g), as described in the Methods and Supplementary Information. It should be noted that we have not observed implantation-related or QD-related degradation or failure at a brightness of 10,000 nit as shown in Supplementary Fig. 8h. Furthermore, we are under development of a backside-exposure technique for high-resolution patterning of QD C/Cs ( Supplementary  Fig. 13), which is essential for full-colour microdisplays in AR glasses. In the backside-exposure technique, a spin-or spray-coated negative QD photoresist (PR) layer is selectively cross-linked from self, backside exposure by TFT-driven, pixelated blue LED arrays located beneath the QD PR layer (Supplementary Fig. 13a-d). In the case of conventional front-side exposure, the QD PR is cross-linked from the top side while the bottom side is not fully cross-linked; this often results in removal of the exposed pattern during the developing process, leading to poor quality or yield in the fine patterning of QD PRs smaller than 5 μm. By contrast, the backside-exposed QD layer begins cross-linking from the bottom side, which enables fine patterning with controlled PR thickness. Regardless of the initial coating thickness, the patterned thickness can be accurately modulated depending on the exposure dose ( Supplementary  Fig. 13e). For example, screen-printed carbon nanotube paste can be patterned down to 2 μm using the backside-exposure technique 28 while the minimum pattern size is larger than 50 μm in the case of the front-exposure technique. Although patterning by backside exposure is in its early-development stage, 2.5-μm-wide and 6.5-μm-high QD patterns can be realized (Supplementary Fig. 13f). This indicates the feasibility of high-aspect-ratio patterning even at high resolution. We believe that the backside-exposure technique is a potential candidate for high-resolution QD patterning above 5,000 ppi (pentile).

Conclusions
We demonstrate TIIP for mid-submicrometre-sized, electricallydriven pixelation of InGaN-based LEDs with the pixelation mechanism revealed. PL microscopy of submicrometre-sized pixels clearly reveals that luminance, intrapixel uniformity and pixel distinctiveness in TIIP pixelation are well maintained. TIIP pixelation can achieve stable, leakage-free EL luminance of 7,440 nit at 4.9 A cm −2 even at mid-submicrometre sizes (W/L = 0.5/0.5 μm, 8,500 ppi (RGB)). We numerically show that, with further lateral confinement of implanted ions, TIIP can potentially achieve a high efficiency even for submicrometre-sized pixels. Furthermore, owing to planar geometry, the TIIP-pixelated LEDs have an excellent integration capability with small-sized TFT pixel circuits and QD C/ Cs. We strongly believe that TIIP pixelation is the ideal solution for full-colour ultrahigh-definition microdisplays for AR glasses.

online content
Any methods, additional references, Nature Research reporting summaries, source data, extended data, supplementary information, acknowledgements, peer review information; details of author contributions and competing interests; and statements of data and code availability are available at https://doi.org/10.1038/ s41566-021-00783-1.

Methods
Submicrometre IIP and 2D SIMS analysis. Distribution of arsenic ions is analyed by 2D SIMS to reveal the implanted profiles of TIIP and non-TIIP conditions. The tilt angle/ion energy for TIIP and non-TIIP were 0° per 5 keV and 7° per 8 keV, respectively, with the dose fixed at 1 × 10 16 atoms per cm 2 . After implantation, the PR mask is removed by O 2 ashing and the samples are measured by SIMS using a CAMECA IMS 7f instrument. The projected range of As + penetration is ~50 nm under the beam-sputtering time calibration of 2 eV, −40 nA Cs + . We analyse the p-GaN/AlGaN electron-blocking layer MQWs and some n-GaN near the MQWs. Using 30 keV and a 1 pA Bi + probe beam, the data detected in image mode are summed along a particular strip, that is, projected onto the particular plane, to improve the counting statistics. Two-dimensional concentration profiles are finally obtained by respective data analysis, where a deconvolution algorithm (Lucy-Richardson) is used to account for Gaussian distribution of the beam density.

Integration of TIIP/CBL-pixelated LEDs and LTPS-TFTs.
Our InGaN LED epilayers are formed on eight-inch-diameter Si (111) wafers ( Supplementary  Fig. 1a). The epilayer consists of a 150-nm-thick AlN nucleation layer, an AlGaN multilayer buffer, a 3-μm-thick undoped-GaN layer, a 3-μm-thick Si-doped n-GaN layer, a 2.1 nm/2.4 nm 50-period InGaN/GaN superlattice underlayer, five pairs of 3 nm/5 nm InGaN/GaN MQWs, a 10-nm-thick Mg-doped AlGaN electron-blocking layer and a 100-nm-thick Mg-doped p-GaN layer. The p-GaN activation was performed by annealing in a furnace under a nitrogen atmosphere for 30 min at 700 °C. After forming an alignment key, the pixel region is closed by a rectangular PR pattern that is subjected to IIP under TIIP conditions; an implantation mask of 200-nm-thick Ti patterned layer, Ar + ions, a tilt angle of 0° and an energy/dose of 5 keV/2 × 10 12 atoms per cm 2 . Then, a 50-nm-thick SiO x layer pattern is formed as a CBL with an opening into the pixel region, followed by a rectangular Ni (5 nm)/Al(100 nm)/Mo (50 nm) p-electrode pattern in the CBL opening region (Supplementary Fig. 8a). Supplementary Figure 8b shows that a 500-nm-thick-SiO 2 :H buffer layer and an a-Si:H layer are successively deposited by plasma-enhanced chemical vapour deposition. The a-Si layer is thermally annealed for 1 h at 450 °C for dehydrogenation, and excimer-laser annealing was subsequently used for its conversion into a p-Si active pattern. We observe that the dehydrogenation step of a-Si:H just before excimer-laser annealing is critical to EL performance. Above a dehydrogenation temperature of 500 °C, we observe only spotty EL emission after TFT integration. We attribute this to rehydrogenation of the activated Mg-doped p-GaN during the dehydrogenation step, where the evolved hydrogen from a-Si:H can be used for hydrogenation, thereby deactivating the activated p-GaN. A gate insulator (40-nm-thick SiO 2 /80-nm-thick SiN x ) and gate (150-nm-thick Mo) were deposited, with gate line-patterning followed by source/drain (S/D) boron implantation, interdielectric (400-nm-thick SiN x ) deposition and subsequent thermal annealing for activation and hydrogenation, via hole patterning to metallize the S/D and p-electrode of the LED and finally S/D (Mo/Al/Mo) deposition and patterning.
As an alternative driving method, bonding is also considered to provide a one-to-one electrical connection between the p-electrodes of the pixelated LEDs and drain electrodes of the driving CMOS transistors. This option has the following advantages: low power consumption, controllability of brightness uniformity, selection of peak current for high efficiency by high-speed operation (pulse-width modulation), small form-factor capability by integrating many peripheral circuits such as timing controllers, and it is bezel-less due to its vertical stacking. Regarding high-resolution bonding, conventional metal-to-metal bonding such as eutectic bonding has clear limits. The minimum pad dimension is ~5 μm with a pitch of ~10 μm, which is not suitable for microdisplays for AR glasses. New Cu-to-Cu, or C2C, hybrid bonding, which is currently being developed for CMOS image sensors, is under development with a pad size of 1.0 μm and a pitch of 2.0 μm. Hybrid bonding is a method that connects two plasma-treated substrates by Cu-Cu metal bonding and by ILD-ILD oxide bonding simultaneously 29 , where ILD is an interlayer dielectric. However, the strict requirement of ultrahigh surface smoothness (~2 nm) across the wafer makes it very difficult to use hybrid bonding in typical LEDs having 3D structures, such as mesa-etched or microrod LEDs. By contrast, a planar TIIP/CBL LED is easily modified to obtain the required smoothness by simply applying standard chemical mechanical polishing.
FA fabrication with or without resonant cavity. After fabricating the TFTs, the TFT + LED structure is adhesively bonded to a carrier substrate and the growth substrate is removed to apply the light-flipping (upside-down) procedure ( Supplementary Fig. 8c). First, the monolithically integrated LED + TFT structure is attached to the carrier substrate using a special adhesive resin, such as benzocyclobutene (Dow Chemical), and the silicon growth wafer is removed via wafer grinding and high-speed silicon deep etching of the substrate until the GaN buffer is revealed. Then, the complete buffer/u-GaN/n-GaN layer area is etched to various thicknesses of the LED layer using flood-area inductively coupled plasma etching with a Cl 2 /Ar mixture. Next, the n-common electrode (Ti/Ni) is formed via a lift-off process and GaN roughening is performed via treatment with 20% tetramethylammonium hydroxide solution at 60 °C for 5 min. For RCFA structures, instead of tetramethylammonium hydroxide roughening, an n-pair distributed Bragg reflector (DBR) is deposited on top of the n-common electrode. Opening of the pad was achieved by etching the n-GaN/buffer/400-nm-thick SiO 2 /gate insulator (40-nm-thick SiO 2 + 80-nm-thick SiN) to facilitate access of data, clock signals and d.c. biases to data lines, shift registers and drain voltage (V dd ) lines, respectively.
The RCFA is studied to reduce optical loss in the diffraction gratings in waveguide-type AR glasses ( Fig. 4c and Supplementary Fig. 12a). The resonant cavity consists of a medium-gain InGaN MQW placed between an aluminium p-electrode mirror and a TiO 2 /SiO 2 DBR, each of which is λ 0 /(4n eff ) thick ( Supplementary Fig. 12b). Five or three DBR pairs (with a reflectance R of 95 and 80%, respectively) should be chosen to obtain the optimal resonant light output considering the low reflectance of aluminium (R = 90%; Supplementary Fig. 12c). With ten DBR pairs (R > 99.9%), resonant light barely penetrates the DBR to obtain meaningful light output; the loss term in the aluminium electrode is too large even without considering the cavity loss. At a cavity physical thickness (L cavity = t n-GaN + t MQW + t p-GaN + t ITO , where t represents the respective thicknesses of the n-GaN, MQW, p-GaN and indium tin oxide layers) of 2.45 μm, the RCFA exhibits multimode resonance with a mode spacing (Δλ mode ) of 14 nm between the peaks at 456 and 442 nm ( Fig. 4c and right panel of Supplementary Fig. 12a). This measured value is consistent with the calculated value (14.8 where L eff , n cavity , n SiO2 and n TiO2 are the effective cavity length, refractive indices of the cavity, SiO 2 and TiO 2 , respectively, and m and L pen is the number of pairs and penetration depth of DBR layers, respectively. Each mode has an FWHM of ~4.8 nm, which is much smaller than the conventional value of ~20 nm. To achieve a single mode, we are reducing the L cavity value to below 0.5 μm and hence increase Δλ mode above the gain emission width. Quantum dot colour converter fabrication. An RGB colour converter pattern on a barrier rib is defined by conventional photolithography using negative-type QD-containing and QD-free PRs ( Supplementary Fig. 8e,g) 31 . The QD-containing PR consists of red and green QDs with the appropriate resin, solvent, TiO 2 nanoparticles (light scatterer) and photosensitizer, and the QD-free PR has all the same components except for the QDs. The fabrication process for a QD C/C pattern begins with the polymer rib pattern, followed by three photolithography processes for red/green QD and QD-free PR patterns. Each photolithography process consists of coating, exposure and developing steps. Then, a planarization layer based on an acrylate polymer is applied for planarization followed by a SiO x N y thin film for encapsulation. Absorption-type red/green colour filters, which pass red/green colours while cutting off other colours, respectively, are formed on the encapsulated planarization layer. Finally, a black matrix is formed to minimize reflection. An inorganic dielectric layer, such as SiO x N y , should be coated before patterning of negative photopolymers, such as QDs or a black matrix, to promote perfect patterning.

Data availability
The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.