Enhanced Breakdown Voltage of Si-GaN Monolithic Heterogeneous Integrated Cascode FETs by the Device Structure Design


 In this work, the factors affecting the breakdown voltage of Si-GaN monolithic heterogeneous integrated Casccode FET fabricated by transfer printing were investigated. These two factors are the avalanche breakdown resistance of the Si device and the thickness of SiN electrical isolation layer. Two kinds of device structures, Si MOSFET and Si laterally-diffused MOSFET (LDMOSFET), were designed to study the effect of the avalanche breakdown resistance of the Si devices on the breakdown characteristics of Cascode FET. The effect of the thickness of SiN electrical isolation layer was analyzed. Finally, the breakdown voltage of monolithic integrated Cascode FET reached 770 V.


I. INTRODUCTION
onolithic heterogeneous integrated devices and circuits are getting more and more attention in this era of Moore's Law coming to an end. Monolithic heterogeneous integrated devices and circuits, compared with the traditional packaging form of integrated devices and circuits, have a higher degree of integration, higher operating frequency and more diverse functions. These advantages are needed for devices and chips in the 5G era, and are needed to continue Moore's Law.
In recent years, there have been many reports on the fabrication of various monolithic heterogeneous integrated devices and circuits by different heterogeneous integration methods, heteroepitaxy [1]- [3], wafer bonding [4], [5] and transfer printing [6], [5]- [8], respectively. At present, monolithic heterogeneous integrated devices reported include Cascode FETs, Cascode diodes, flexible UV PDs and UV LEDs, etc [1], [2], [5], [6], [8]- [12]. And monolithic heterogeneous integrated circuits reported include GaN-Si hybrid amplifier, current mirror integrated circuits and half-bridge circuits [13]. Manuscript  Among the three heterogeneous integration methods mentioned above, the transfer printing method isn't limited to the sizes of material lattices, the crystal orientations of materials and the types of the integrated materials. And, the requirements on wafer flatness are not harsh, the operation is simple, the cost is low, so the transfer printing method has more universality and application prospect [14]- [16].
In our previous work, wafer-scale Si-GaN monolithic integrated Cascode FETs were realized by transfer printing and self-aligned etching technology preliminarily [6]. However, the breakdown characteristics of monolithic heterogenous integrated Cascode FET realized by transfer printing method were very poor (~ 40 V) [6]. To solve this problem, two key factors affecting the breakdown characteristics of the monolithic heterogeneous integrated Cascode FET devices have been found in this work. Firstly, the silicon devices in Cascode FET devices must have a certain anti-avalanche ability to turn off the GaN HEMTs. Secondly, the SiN used for the electrical isolation of Si and GaN should be thick enough to isolate the effect of 2DEG on the silicon devices. The relevant devices were tested, and the results verified the above viewpoints. What's more, the effect of polarization charge in AlGaN/GaN on silicon device is analyzed by physical model. Finally, the monolithic heterogeneous integrated Cascode FET with breakdown voltage of 770 V was realized. And, its switching characteristics at 100 Hz and 1 kHz were tested.

II. DEVICE FABRICATION
The fabrication process of Si-GaN monolithic heterogeneous integrated substrate is detailed in the previous work [6]. The Si-GaN monolithic integrated cascode FETs were fabricated on this Si-GaN heterogenous integrated substrate prepared by the transfer printing method [6]. Drift regions and S/D regions of Si devices were defined by phosphorus ion implantation. Boron ion implantation defined P+ regions of Si devices, and the dopants were activated by rapid thermal processing (RTP) at 1000 o C for 60 sec. Subsequently, SiN was etched away to form the Ohmic contact windows in source regions. And, Ti/Al/Ni/Au stack was deposited on it. By using RTP (875 °C, 30 sec), the Ohmic contact was formed. The gate and drain windows of GaN HEMTs were opened by Etching the SiN layer. Then, the gates and Schottky drains of GaN HEMTs were  In order to study the effect of anti-avalanche ability of silicon devices on the breakdown characteristics of monolithic heterogeneous integrated Cascode FET devices, two kinds of Si devices with different structures on the SiN/AlGaN/GaN substrate were designed, as shown in Fig. 1. Fig. 1 (a) shows the normal Si MOSFET device transferred on the SiN/AlGaN/GaN substrate. Fig.1 (b) shows the Si LDMOS device transferred on the SiN/AlGaN/GaN substrate. In addition, each of the different silicon devices has a different SiN layer thickness of 20 nm and 200 nm, respectively.was deposited followed by RTA at 400 °C for 30 sec to form ohmic alloy of the Si MOSFET. Finally, the vias of G/S/D electrodes of GaN HEMT were opened by BOE. Ni/Au stack deposition formed the metal interconnects.

III. RESULTS AND DISCUSSION
The Si devices were placed on top of an active 2DEG from AlGaN/GaN structure in our previous work [6]. This kind of monolithic heterogeneous integration is likely to cause problems with backgate effect and other coupling effects, which may adversely affect the performances of heterogeneous integrated Cascode FETs. Fig. 2 shows the cross-section diagram of the Si/SiN/AlGaN/GaN structure realized by transfer printing and self-aligned etching. The polarization charge generated by AlGaN/GaN structure is represented by white balls in the figure. Under normal circumstances, the polarization charges will induce a high concentration of electrons at the interface of AlGaN/GaN heterojunction, 2DEG, namely. At this time, the polarization charges and 2DEG reach the charge balance, and the AlGaN/GaN heterostructure is electrically neutral. The Si/SiN/AlGaN/GaN structure can be simplified to the equivalent graph, as shown in Fig. 2 (b). This equivalent structure consists of two capacitors (CSiN, CAlGaN/GaN) in series and the polarization charge (Qpol). Due to the existence of Si (100) layer, the polarization charges will also induce electron channel at the bottom interface of Si, and the charges balance relationship at this time is as follows: In the above formula, QSi is the amount of electron charge induced by the polarization charge in the Si layer. QAlGaN/GaN is the charge amount of 2DEG in AlGaN/GaN heterojunction. In order to weaken the effect of polarization charge on the Si layer, the electrons induced in the Si layer by polarization charge need to be reduced. It follows from the formula that it can be realized by reducing the CSiN. Therefore, the thickness of the SiN layer was increased to 200 nm to reduce the effect of polarization charge on the silicon layer. And, a 20 nm SiN layer was used as a control.  As can be seen from Fig. 3 (a), the breakdown voltage of Si LDMOSFET is 12 V, and the breakdown voltage of Si MOSFET is 6 V. And both of these Si devices on SiN/AlGaN/GaN substrate with 20 nm SiN have large current leakage. Similarly, it can be seen from Fig. 3 (b) that the breakdown voltage of Si LDMOSFET is 13 V, and the breakdown voltage of Si MOSFET is 6.5 V. And the turn-off currents of these two kinds of Si devices are both in a lower magnitude (10 -7 A). Therefore, through the above comparison, it can be concluded that the thinner SiN layer will have an adverse effect on the off-state current of the Si devices. This is because the CSiN of the thinner SiN layer (20 nm) is larger. The QSi induced by polarization charge is more in Si layer. Therefore, the electron channel formed by QSi is less easily controlled by the gate of silicon device. The gate was applied a voltage of -3 V to shut down the top channel and the bottom channel. However, due to the weak control force of the gate on the bottom channel and the high electron concentration of the bottom channel, the gate can't control the bottom channel well.
Therefore, as the VDS is increasing, the gate voltage is at a disadvantage in the competition with the VDS for the control of the bottom channel. It leads to the increase of current leakage. Moreover, Si LDMOSFET has higher breakdown voltage compared with Si MOSFET. The reason is that LDMOS has an Ndrift region which enables the Si device to withstand a larger voltage.  As can be seen from the figure, the off-state current of Si LDMOSFET with 20 nm SiN layer is an order of magnitude higher than that with 200 nm SiN layer. That is to say, the thinner the SiN layer, the more negative the threshold voltage of Si LDMOSFET drift, and the greater the off-state leakage current. The reason is that the thin SiN layer isn't thick enough to eliminate the influence of the polarization charge on the Si layer, so that the bottom interface of the Si layer is induced to generate a high concentration of electrons, forming a conductive channel. This bottom interface channel enables the Si device to have normally-on property, and it also makes the threshold voltage drift negatively. Compared with the Si device with 200 nm SiN layer, the Si device with 20 nm SiN layer has higher induced electron concentration in bottom interface channel. And, the bottom interface channel of Si device with 20 nm SiN layer is less likely to be clamped by the gate, so there will be higher off-state leakage current. Finally, the pulse switch response waveform of the Cascode FET device was tested in Fig. 6. The gate signal was set (Vhigh = 7 V, Vlow = 0 V). The dynamic response of the IDS of the Cascode FET at 100 Hz was good, as shown in Fig. 6 (a). Although the IDS is somewhat sluggish at 1 kHz, it can still reach saturation and follow the change of the VGS, as shown in Fig. 6 (b). In future work, we will continue to improve and optimize the dynamic characteristics of the Cascode FET by reducing the interface states and defects of Si devices.

IV. CONCLUSION
In conclusion, monolithic heterogeneous integrated Cascode FET devices fully demonstrate their advantages, but there is still a problem of poor breakdown characteristics. In this work, the influence mechanism of 2DEG on silicon layer was analyzed and explained in depth. Then, the above mechanism was verified by experiments. Finally, the breakdown voltage of Cascode FET reached 770 V by changing the structure of the silicon device and thickening the SiN layer. And, the dynamic characteristics of the Cascode FET device were tested and the optimization scheme was proposed.