Modeling and Dynamics Analysis of a Universal Interface for Constructing Floating Fractional Order Mem-Elements

Fractional-order systems generalize classical differential systems and have empirically shown to achieve fine-grain modeling of the temporal dynamics and frequency responses of certain real-world phenomena. Although the study of integer-order memory element (mem-element) emulators has persisted for several years, the study of fractional-order memory elements (FOMEs) has received little attention. To promote the study of the characteristics and applications of mem-element systems in fractional calculus (FC) and memory systems, in this paper, we propose a novel universal interface for constructing floating FOMEs. When the topological structure of the interface remains unchanged, the floating fractional-order memristor (FOMR), fractional-order memcapacitor (FOMC) and fractional-order meminductor (FOMI) emulators Acknowledgments This work was supported by the Young Scientists Fund of the National Natural Science Foundation of China Grant (No. 62101142); the Guangzhou Science and Technology Plan Research Project under Grant (No. 202102020874); and the Featured Innovation Foundation of the Education Department of Guangdong Province under Grant (Nos. 2021KTSCX062, 2021ZDZX1079). Ya Li · Lijun Xie School of Electronics and Information, Guangdong Polytechnic Normal University, Guangzhou 510660, China Ciyan Zheng ( ) School of Automation, Guangdong Polytechnic Normal University, Guangzhou 510660, China E-mail: ciyanzheng@gpnu.edu.cn Dongsheng Yu School of Electrical and Power Engineering, China University of Mining and Technology, University, Xuzhou 221116, China Jason K. Eshraghian the Department of Electrical Engineering and Computer Science, University of Michigan at Ann Arbor, Ann Arbor, MI 48109 USA Department of Computer Science and Software Engineering, University of Western Australia, WA 6009 Australia

can be realized by using the impedance combinations of different passive elements, without any mem-element emulators and mutators. When compared with previously proposed FOMEs, the proposed fractional-order mem-element emulators based on a universal interface not only feature the characteristics of floating terminals and simpler circuit structures, but can also realize all three different types of FOMEs. To explore the dynamical relationships between the mem-elements and the fractional order, we mathematically derive and analyze the maximum and minimum possible values of memductance, memcapacitance and inverse meminductance which accounts for practical design considerations when building FO systems. The memory characteristics of FOMEs are analyzed by varying their orders and stimuli frequencies. The consistency of theoretical analysis, numerical calculation and simulation results validates the correctness of our proposed emulators.

Introduction
Fractional calculus (FC) is a generalization of ordinary differential systems to an arbitrary, real order [1]. FC has been used to model real-world physical and quantum phenomena across a variety of domains which could not be achieved using integer-order dynamics alone [2][3][4][5]. Fractional derivatives have shown to successfully model the fine-grain memory and hereditary characteristics of the temporal dynamics and frequency responses of various systems. Several promising examples of the progress FC has made in applied domains include oscillators [6,7], filters [8,9], controllers [10,11], sub-atomic phenomena [12], and biological systems [13,14].
In 1971, Leon Chua theoretically predicted the existence of the 'missing fourth fundamental circuit element', namely the memristor [15]. Several decades later, in 2008, researchers from Hewlett Packard (HP) Labs discovered the link between devices exhibiting resistive switching characteristics with the memristor (MR) [16]. Such memory elements (mem-elements) have since been generalized to the memcapacitor (MC) and the meminductor (MI) [17]. Despite the significant resources pooled into undertaking memristive research, their accessibility remains limited. Most demonstrations of experimental results using memristors depend upon specialized fabrication processes [18,19], and presently available discretely packaged memristors are extremely sensitive exhibiting significant variation [20,21], with endurance that limits their practical application to prototypical experiments [22,23]. This motivates the need for emulators that facilitate the exploration and design space of mem-elements, until experimental usage of memristors and resistive random access memories (RRAM) are made more broadly accessible. Mem-element emulators can be subdivided into grounded and floating types. With respect to two-terminal emulators, floating mem-elements are more broad in potential applications as one of their terminals are not constrained to being grounded. For example, a highfrequency floating memristor emulator was presented in [24], where one terminal of the emulator is connected to the voltage source, and the other terminal is connected to an amplifier in a high-frequency modulation scheme, which cannot be achieved by grounded MR emulators. In general, mem-element emulators have accelerated memristive research that can be adopted by device researchers for future on-chip integration. In the past, emulators have been used to build adjustable relaxation oscillators [25][26][27], digital modulation [28], adaptive learning circuits [29], chaotic systems [30][31][32][33][34], and neuromorphic circuits [35][36][37].
The potential ability of fractional-order models in simulating a more generalized range of systems than corresponding integer-order counterparts [38] has driven research in memory systems using FC, where a mathematical paradigm for describing the behavior of FOMEs was proposed in [39]. Later, researchers proposed individual FOMR emulators [40], and in [41], a FOMR is realized on the basis of a floating integer-order memristor emulator circuit. More recently, multiple types of FOMEs have been emulated within the same circuit structure, where in [43], the FOMC and FOMI emulators are proposed based on fractional-order capacitors (FOC) and integer-order memristor emulators. A limitation of these approaches are that the constructed FOMC and FOMI emulators depend on the characteristics of the memristor emulators they are originally based upon, and the circuit structure thus becomes unnecessarily complex and difficult to simplify. Generalized grounded and floating FOMEs emulators that can emulate FOMR and FOMC are proposed by using different impedance combinations in [44], but these emulators cannot implement FOMI emulation, and are limited to the functionality of FOMR and FOMC. In [45], a fractional higher-order FOMR, FOMC and FOMI emulator was implemented by using a current conveyor (CCII) and analog voltage multiplier (AVM), but these FOMEs only have one free port, which does not enable flexible usage. While all of these emulators have helped researchers to explore the characteristics and potential applications of FOMEs, they all have their own specific drawbacks. Driven by the above shortcomings, we propose a novel floating universal interface, based on which floating FOMR, FOMC and FOMI emulators can be realized, without depending on a mem-element emulator or mutator as the basis of the design. In doing so, we address the flexibility and simplicity challenges that plague fractional-order mem-element emulators.
In this paper, three types of floating FOME emulators are realized by using different impedance combinations, verified using SPICE simulations. Compared with other similar research work, the universal interface can implement three types of FOME emulators with three key benefits: 1) the use of floating terminals and thus, enhanced flexibility, 2) without added circuit complexity over prior designs. 3) simpler circuit structure for easier implementation. The structure of this paper is as follows. In Sect. 2, we provide a theoretical analysis of FOMEs. In Sect. 3, three different fractional order mem-element emulators are presented on the basis of the theoretical analysis of the second section, which leads to the proposal of a novel universal interface, which uses FOCs to achieve fractional-order integration. In Sect. 4, we verify three different FOME emulators using both SPICE and MATLAB, with an accompanying analysis of the results obtained of the FOMR, the FOMC and the FOMI emulators. In Sect. 5 concludes the paper.

Theoretical analysis of FOMEs
The fundamental operator of fractional calculus m D α t can be defined as [46]: where α ∈ R, and m and t are the bounds of the operation. The theoretical analysis of each of the FOMR, FOMC and FOMI circuits are presented below.

Theoretical analysis of FOMR
The constitutive relationship between q and ϕ of the integer-order memristive system [47] is given as follows: where q and ϕ are the time-domain integrals of current i and voltage v. By differentiating both sides of equation (2), the i-v relationship of MR can be expressed as: where G m is the memductance (the reciprocal of memristance). The Taylor expansion of (2) is By substituting (4) into (3), the expression of the flux-controlled memductance [48] can be obtained: Introducing the fractional-order integral from equation (1), the corresponding expression of the fractional-order integral of voltage is derived: Assuming the initial value of ϕ α (t), ϕ α (0) = 0 results in: where 0 J α v(t) is the fractional-order integral of voltage v(t), and the notation of fractional-order integral using Riemann-Liouville's definition [49] is given by: By taking k = 2 in equation (5), and substituting J α v(t) into equation (5), one of possible equations of fractional-order memductance is derived using: where a 1 and b 1 are a scaling constant and the initial value of G m (ϕ α ), respectively.

Theoretical analysis of FOMC
The memcapacitor model based on its constitutive relationship was proposed in [50], and the constitutive relationship between σ and ϕ of a memcapacitative system [47,51] is given as: where σ and ϕ are the time-domain integrals of charge q and voltage v.B y differentiating both sides of equation (10), the q -v relationship of MC can be obtained: where C m is the memcapacitance. The Taylor expansion of (10) is The memcapacitance is obtained by substituting equation (12) into equation (11): Substituting J α v(t) of equation (7) into equation (13), and setting k =2 leads to one possible equation characterizing a fractional-order memcapacitance: where a 2 is a scaling constant and b 2 is the initial value of C m (ϕ α ).

Theoretical analysis of FOMI
The constitutive relationship between q and ρ of the meminductive system [47] is given as follows: where q and ρ are the time-domain integrals of current i and of flux ϕ.B y differentiating both sides of (15), the i-ϕ relationship can be expressed as: where L −1 m is the inverse meminductance. The Taylor expansion of (15) is By utilizing equations (16) and (17), the inverse meminductance [51] can be given as: The expression for fractional-order integral of flux is: where ϕ(t) is the integer-order integral of voltage v(t). Assuming the initial value of ρ α (t), ρ α (0) = 0, leads to the following result: where 0 J α ϕ(t) is fractional-order integral of the flux ϕ(t). Fig. 1 Universal interface for building FOME emulators.
When the parameter k in equation (18) is set to '2', and equation (20) is substituted into equation (18), one possible equation for the fractional-order of the inverse meminductance can be given as: where, analogous to the FOMC case, a 3 is a scaling constant and b 3 is the initial value of L −1 m (ρ α ). In this section, we have commenced with the theoretical analysis of integerorder mem-elements, and transitioned to FOMEs analysis.

Circuit design of FOME emulators based on a universal interface circuit and fractional-order capacitor
Before building FOME emulators, we first design a universal interface circuit. Following that, we will demonstrate the design of the corresponding emulators.

Design of a universal interface circuit
As shown in Fig. 1, the universal interface is made up of four current-feedback operational amplifiers AD844 (CFOAs, labeled U1, U2, U4 and U5), one voltage multiplier AD633 (U3), one resistor (R 2 ), two impedance elements that can be either a resistor, capacitor or inductor (Z 1 and Z 2 ), a DC voltage source V s and one FOC (C 1 ). A and B act as floating terminals of FOME emulators based on the universal interface, enabling emulators to be connected in series with other components, and the input voltage is applied between A and B. There are an unbounded number of ways to model FOMR, FOMC and FOMI, and different emulators can be designed by using various combinations of impedance elements to the interface terminals.
The AD844 behaves as a current conveyor and voltage follower in the universal interface circuit, where the port characteristics of AD844 can be expressed as: According to equations (22) and (23), the expressions of current i 1 , i 2 , i 3 and i AB of this universal interface in the complex frequency domain are: whereİ 1 andİ 2 are the complex frequency domain current responses from terminals x and z of U 1, respectively,V z2 is the complex frequency domain voltage across impedance Z 2 , andV w is the output voltage of AD633 in the complex frequency domain. As shown in Fig. 1, the FOC C 1 is the equivalent energy-storage element adopted in proposed emulators to provide the fractional-order integral operation. Due to the commercial unavailability of a two-port FOC device on the market, Valsa proposed a helpful method for calculating comparable FOC values [52], and according to the principle of calculation, different combinations of resistance and capacitance can be calculated when the FOC takes different values. According to the analysis of the fractional-order capacitance state [53], the voltage and current flowing through FOC can be expressed as: where 0 <α<1. According to the characteristics of FOC in equation (25), and the characteristics of AD844 in equations (22) and (23), voltage v c1 is transmitted to the output v x1 of terminal p of the AD844-U1 via an internal voltage follower. Thus, v x1 and v c1 in the complex frequency domain can be calculated by: whereV AB /s α shows the complex frequency domain response of J α v AB (t).
From equation (24a), and the combination of the characteristics of the AD844 in equations (22) and (23), the voltage of R 2 in the complex frequency domain can be described as: According to equations (27) and (28), and the input-to-output function of U3 (AD633), v w in the complex frequency domain can be calculated by: where V s is an adjustable direct-current voltage. Equations (24b) and (29) are combined to derive the relationship between the input voltage v AB and the input current i AB in the complex frequency domain:İ This concludes the theoretical characterization of the proposed universal interface circuit in Fig. 1. In the following sections, we present our design of the FOMR, FOMC and FOMI based on the universal interface circuit.

Design of a fractional-order memristor
When the impedance elements Z 1 and Z 2 in Fig. 1 are resistors R 1 and R 3 respectively, according to equation (30), the emulator is a FOMR. The relationship between the input voltage v AB and the current i AB in the time domain can be described as: The emulator is simulated as a flux-controlled FOMR. According to equations (9) and (31), the memductance G m (ϕ α ) of FOMR can be expressed as: From equations (31) and (32), a 1 and b 1 can be expressed as: Equation (32) shows the relationship between the value of the memductance of the FOMR emulator and the fractional-order integration of the input voltage v AB . Thus, the internal state of the FOMR emulator is dynamically varying in accordance with the fractional-order integration of the terminal input voltage v AB .

Design of a fractional-order memcapacitor
The emulator is a FOMC when the impedance elements Z 1 and Z 2 in Fig. 1 are a resistor R 1 and a capacitor C 2 . By inserting circuit parameters R 1 and C 2 into equation (30), in the complex frequency domain, the relationship between input voltage v AB and the current response i AB is as follows: The emulator is simulated as a flux-controlled FOMC. According to equation (34), the q-v relationship in the time domain can be written as: According to equations (14) and (35), the memcapacitance of the FOMC C m (ϕ α ) can be written as: From equations (35) and (36), a 2 and b 2 can be written as: The relationship between the value of the FOMC emulator's memcapacitance and J α v AB (t) is shown in equation (36). From this equation, there is an explicit relationship between the internal state of the FOMC emulator and the fractional-order integration of the terminal input voltage v AB .

Design of a fractional-order meminductor
The emulator is a FOMI when the impedance elements Z 1 and Z 2 in Fig. 1 are consist of an inductor L 1 and resistor R 1 .B ys u b s t i t u t i n gL 1 and R 1 into equation (30), in the complex frequency domain, the following relationship links input voltage v AB and the current response i AB : whereV AB /s α+1 indicates J α ϕ AB (t) in the complex frequency domain. The emulator is simulated as a ρ-controlled FOMI. According to equation (38), the i-ϕ relationship in the time domain can be given as: Ta b l e 1 FOME emulators realized by different impedance combinations Types of FOMEs The expression of FOMEs According to equations (21) and (39), the inverse meminductance L −1 m (ρ α ) of FOMI can be given as: From equations (39) and (40), a 3 and b 3 can be expressed as: The relationship between the value of the FOMI emulator's meminductance and J α ϕ AB (t) is seen in equation (40). The equation reveals that the internal state of the FOMI emulator is affected by the fractional-order integration of the terminal flux ϕ AB . Table 1 lists different types of FOMEs and their corresponding expressions when Z 1 and Z 2 are selected as different impedance elements.
From the above analysis, it is clear that only the impedance elements Z 1 and Z 2 need to be changed to either resistor, capacitor or inductor to realize corresponding FOMR, FOMC and FOMI elements.

Circuit implementation and simulation results
In this section, we provide SPICE and MATLAB simulation results in order to verify the circuit design of the proposed fractional-order mem-element emulators in Sect. 3.
The construction of FOMR, FOMC and FOMI emulators is based on a universal interface, shown in Fig. 1, according to different impedance combinations in Table 1. As charge q and flux ϕ are not directly measurable, instead, they can be measured by using internal voltages in the FOME emulators as proxy variables, that are proportional to q or ϕ.
For the FOMR emulator, the impedance elements Z 1 and Z 2 are resistors R 1 and R 3 , respectively. According to equation (27), the fractional-order integral of voltage v AB is proportional to v c1 in the time domain, therefore, v c1 can be used to replace the J α v AB (t) equivalently. Thus, the corresponding memductance G m (ϕ α ) of FOMR can be calculated according to (32) by using v c1 .
For the FOMC emulator, the impedance elements Z 1 and Z 2 are a resistor R 1 and capacitor C 2 , respectively. The charge q AB is proportional to the voltage (−v C2 ) in the time domain, as can be seen from equation (24b). As a result, the voltage (−v C2 ) can be substituted for q AB . Based on the FOMR analysis above, the voltage v c1 can be used to replace the J α v AB (t) equivalently. Thus, utilizing the voltage v c1 , the memcapacitance C m (ϕ α ) of FOMC can be determined according to equation (36).
For the FOMI emulator, the impedance elements Z 1 and Z 2 are an inductor L 1 and resistor R 1 , respectively. It is known from equation (24a) that flux ϕ AB is proportional to the current i 1 in the time domain. Therefore, flux ϕ AB can be replaced by i 1 . In addition, the equation (27) shows that the fractional-order integral of the flux ϕ AB is directly proportional to v c1 in the time domain. Hence, the inverse meminductance L −1 m (ρ α ) of the FOMI can be computed by using v c1 based on equation (40).

Fractional-order memristor circuit response
Here, we apply a sinusoidal waveform v AB (t)=A sin(2πft)=A sin(ωt) (V) to drive the FOMR. As the frequency f increases, the angular frequency ω increases accordingly. The emulator is a flux-controlled FOMR when Z 1 and Z 2 are R 1 and R 3 , respectively. According to equation (8), the fractionalorder integral of the sinusoidal waveform in the steady-state response [1] can be expressed as: To explore the effect of fractional-order parameter α on the fractional-order memductance variation range, we substitute equation (42) into equation (32), where the steady-state response for memductance of the FOMR can be written as: where A is the amplitude of the input voltage, and b 1 is the initial value of the fractional-order memductance. In addition, when A and α are constant, with an increase of the angular frequency ω, the memductance of FOMR shifts closer to its initial value b 1 . According to equation (43), the maximum value, minimum value and the variation range of the memductance of FOMR are given by the following equa-tions under different conditions: where Z belongs to the integer set. Through the analysis of equations (44c), when the fractional-order α and the amplitude of the input voltage remain constant, the value of ∆G decreases with an increase of the angular frequency ω. In addition, when the amplitude A and the angular frequency (ω>1) are constant, the value of ∆G increases with the decrease of α.
In reality, the value of the fractional-order memductance must be positive, restricting the value of ω as: In our SPICE simulations (conducted in PSPICE), the power supply voltages of chips AD844 and AD633 are ±15 V. A FOC can be electronically realized with an RC (resistive-capacitive) network as shown in Fig. 2. In the simulation experiment, a Valsa constant phase element (CPE) implementation circuit with m = 5 stages is used to emulate the FOC. Resistor and capacitor values of the FOC for C 1 = 18.335 nF/sec 1−α are summarized in Table 2 for fractional orders of α =0.95 and α =0.90, and the circuit parameters are A =1V,R 1 = 10 kΩ, R 2 = 100 kΩ, R 3 = 10 kΩ, V s = −6V .B ys u b s t i t u t i n g the set of parameters into equation (33), coefficients a 1 and b 1 are calculated as 0.545 Ω −1 V −1 s −α and 6 × 10 −4 Ω −1 ,r e s p e c t i v e l y . Fig. 3 shows the evolution of memductance over time of the FOMR across several different fractional orders. When the amplitude A and the frequency f remain constant, the smaller the fractional-order α is, the larger the variation range of the fractional-order memductance is, which is consistent with the analysis of equation (44c). Fig. 4 shows that the pinched hysteresis loop (PHL) of the FOMR emulator passes through the first and third quadrants in the v AB -i AB plane. In the v AB -i AB plane, the slope of the PHL is equivalent to the memductance of the FOMR. When the amplitude A and the angular frequency ω (ω¿1) of the excitation signal are constant, the variation range of the slope of the PHL increases with a decrease of α. Thus, the area within the PHL lobes becomes larger as the value of the fractional-order α decreases when ω>1. Fig. 4 Ta b l e 2 Resistor and capacitor values of Valsa FOC (C 1 =18.335nF/sec 1−α )a p p r o x i m ation circuit realizations at fractional order α =0. 95   shows that the simulation results are consistent with the theoretical analyses of equation (44c). Fig. 5 shows that when the order is 0.95 and the amplitude A of the excitation signal are constant, the value of ∆G decreases with the increase of frequency f . Therefore, the PHL decreases with the increase of frequency f . The simulation results in Fig. 5 are consistent with the theoretical analysis  of equation (44c), which proves the correctness of the FOMR emulator constructed by our novel universal interface.
To clearly express the behavioral relationship between the maximum and minimum fractional-order memductance values, and ω in equations (44a) and (44b), Fig. 6 was simulated using MATLAB. Fig. 6(a), (b) shows the change of the maximum and minimum of fractional-order memductance values with a changing applied frequency f for varying values of α. The maximum/minimum fractional-order memductance values decreases/increases as the frequency approaches infinity, respectively, towards the initial of value of the fractionalorder memductance b 1 , which adheres to the relations found in equations (44a) and (44b). But according to equation (44b), the minimum of the fractionalorder memductance value remains unchanged with a change of the frequency when α = 1. In other cases, the larger the value of α, the faster the decrease of the fractional-order memductance's variation range. In other words, low fractional orders can be utilized to emulate hysteresis behavior at high frequencies.

Fractional-order memcapacitor circuit response
Here, we intend to use a sinusoidal wave v AB (t)=A sin(2πft)=A sin(ωt) (V) to drive the FOMC, and when the frequency f is increased, the angular frequency ω also increases. When Z 1 and Z 2 are set to R 1 and C 2 ,respectively , the emulator is a flux-controlled FOMC. In order to analyze the influence of the value of fractional-order α on the dynamics of the FOMC, equation (42) is substituted into the equation (36) and the memcapacitance C m (ϕ) of FOMC can be expressed by the following equation: where b 2 is the initial value of the memcapacitance of FOMC. When the fractional-order α and the amplitude of the excitation signal v AB are constant, the equivalent memcapacitance of the FOMC approaches b 2 with an increase of the driving frequency. In order to explore the influence of the fractional-order α on the FOMC memcapacitance C m (ϕ α ), by analyzing equation (46), the maximum value, minimum value and the variation range can be obtained: where Z belongs to the integer set. It can be seen from equation (47c) that ∆C is proportional to A/ω α .Thus, when the value of fractional order α and the input voltage amplitude A remain constant, the value of ∆C decreases with the increase of the angular frequency ω. Furthermore, when the amplitude A and the angular frequency ω (ω>1) of the input signals are constant, a decrease in α causes ∆C to also drop.
To keep the fractional-order memcapacitance C m (ϕ α ) positive, a the following condition is imposed upon the applied angular frequency: A SPICE analysis is used for simulation verification. Fractional-order capacitance C 1 =1n F /sec 1−α , and the corresponding values of equivalent circuit RC components for fractional orders α =0.95 and α =0.90 are shown in Table 3. The power supply voltages of chips AD844 and AD633 are ±15 V, while circuit parameters are set to A =1V ,R 1 = 50 kΩ, R 2 = 100 kΩ, C 2 = 1 nF and V s = −6 V. Substituting these circuit parameters into equation (37), coefficients a 2 and b 2 can be calculated as 4 uFV −1 s −α and 1.2n F , respectively. Fig. 7 shows the transient response of the fractional-order memcapacitance value changing for a given excitation voltage, across several different fractional orders. The corresponding PHLs in Fig. 8 show that the smaller the fractional order, the larger the variation range of the fractional-order memcapacitance C m (ϕ α ). Equation (47c) highlights the trend of the range of the fractionalorder memcapacitance C m (ϕ α ) with a change of the fractional-order parameter α.
On the v AB -q AB plane in Fig. 8, the slope of the PHL is equivalent to the memcapacitance of the FOMC. When the excitation signal amplitude A and the angular frequency ω are both constant, the variable range of the slope of the PHL increases as the value of fractional-order α decreases. As a result, the area of the PHL lobes grow in size as the value of fractional order α drops  when ω>1. The simulation results are consistent with the theoretical analysis of equation (47c), as seen in Fig. 8. The slope of the PHL on the v AB -q AB plane is equivalent to the memcapacitance of the FOMC. When the order is 0.95 and the amplitude A of the excitation signal remains constant, the value of ∆C decreases as the frequency f increases. Thus, as the frequency f increases, the PHL shrinks. The simulation findings in Fig. 9 are consistent with the derived equation (47c). The maximum and minimum values of fractional-order memcapacitance are illustrated using functional simulations in MATLAB according to the equations (47a) and (47b). Fig. 10 shows that the maximum and minimum fractional-order memcapacitance values approach infinity as the excitation frequency increases, other than for the case where α = 1 in Fig. 10(b). It can be seen from Fig. 10 that the smaller the value of order α,t h es l o w e r the maximum and minimum values of fractional-order memcapacitance reach the initial memcapacitance. Therefore, in a higher frequency range, a smaller fractional-order α can better emulate the hysteresis behavior of the FOMC.

Fractional-order meminductor circuit response
In this section, we apply a cosine wave v AB (t)=A cos(2πft)=A cos(ωt) (mV) to drive the FOMI, and the angular frequency ω grows in lockstep with the increase of the frequency f . The construction of the FOMI emulator circuit is based on the universal emulator circuit. When Z 1 and Z 2 are L 1 and R 1 respectively, the emulator is a ρ -controlled FOMI. The integer integration of a cosine wave v AB (t) can be written as: According to equation (8), the fractional-order integral of the flux ϕ AB (t) in the steady-state response can be obtained as: In order to obtain the specific expression of the inverse meminductance of the FOMI, equation (50) is substituted into equation (40) to obtain: From equation (51), when the fractional order α and the amplitude A of the excitation signal are constant, the inverse fractional-order meminductance will become infinitely close to the initial value b 3 with an increase of the angular frequency ω. Therefore, the PHL of the FOMI will approach a straight line in the limit of an increasing frequency f .
According to equation (51), the maximum, minimum and variation range of the inverse meminductance of FOMI are given by: where Z belongs to the integer set. By observing equation (52c), when the amplitude A of the input voltage and the value of fractional order α are fixed, the value of ∆L −1 decreases as the angular frequency ω increases. Besides, the value of ∆L −1 increases as the value of fractional order α decreases when the amplitude A and the angular frequency ω are unchanged.
In order to make the inverse fractional-order meminductance positive, the following condition must be satisfied: In order to verify the correctness of the above theoretical analysis, SPICE is used to simulate the analog circuit. Fractional-order capacitance C 1 =1 nF/sec 1−α , and the corresponding value of the equivalent circuit of resistors and capacitors is shown in Table 3. The power supply voltages of chips AD844 and AD633 are ±15 V, and other corresponding circuit parameters are A =5 mV, L 1 = 1 mH, R 1 = 50 kΩ, R 2 = 10 kΩ and V s = −12 V. By substituting these given parameters into equation (41), a 3 =2× 10 13 H −1 Wb −1 s −α and b 3 = 240 H −1 can be obtained.
Through the comparison of different orders in Fig. 11, it can be seen that under the same frequency f and amplitude A of the excitation signal, the variation range of the inverse fractional order meminduction will increase with a decrease of fractional order. This result is consistent with the theoretical analysis of equation (52c).
From the ϕ AB − i AB plane in Fig. 12, the slope is equivalent to the inverse meminductance of the FOMI. When the excitation signal amplitude A and angular frequency ω are both constant, the variable range of the slope of the PHL increases as the value of the fractional-order α decreases. Hence, as the fractional-order α declines and ω>1, the area within the PHL lobe increases. As shown in Fig. 12, the simulation findings are consistent with the theoretical analysis of equation (52c). On the ϕ AB − i AB plane in Fig. 13, the slope of the PHL is equivalent to the inverse meminductance of the FOMI. From equation (49), the flux ϕ AB (t) is proportional to A/ω. Therefore, the amplitude of the flux ϕ AB (t) decreases with an increase of the frequency f when the amplitude A of the input signal is constant. In addition, when A = 5 mV and α =0 .95, the value of ∆L −1 decreases with an increasing frequency f . As a consequence, this fact causes the PHL of FOMI to shrink inward as the frequency increases. Furthermore, the theoretical analysis of equation (52c) also well illustrates the influence of the frequency f on the variation range of the slope of the PHL in Fig. 13.
In order to intuitively express equations (52a) and (52b), Fig. 14 was illustrated using MATLAB. The maximum and the minimum values of the inverse fractional-order meminductance are infinitely close to the initial value b 3 as the frequency increases, shown in Fig. 14. In Fig. 14, the maximum and the minimum value of the inverse fractional-order meminductance will reach the   initial value faster by increasing the fractional order α. In particular, for α = 1, the value of L −1 min is constant. Therefore, the lower the value of order α,t h e more evident the PHL behavior of FOMI is at the same frequency.
To summarize, these simulation results have shown consistency with the theoretical analysis, which effectively proves that the proposed novel universal interface for constructing floating fractional order mem-elements is valid. Table 4 provides comparisons among the proposed FOME based on a universal interface and prior floating FOME emulators, in the aspects of a) the number of active elements, b) the number of passive elements excluding FOC and c) the ability to realize different types of FOMEs. These several aspects of the comparison are crucial, because the fewer number of active and passive elements, the simpler the structures of FOME emulators will have; and the more types of FOMEs for implementation, the broader application prospects the FOME emulators should have. As for the number of active and passive elements, the proposed FOME emulators based on a universal interface obviously possess fewer active elements and passive elements excluding FOC, ensuring circuits structures of the proposed FOME emulators simpler and easier to implement. Regarding the ability to realize different types of FOMEs, only single FOMR emulators are proposed in [41] and [42]. In addition, FOMI emulator cannot be realized in [44]. However, the proposed FOME emulators have the ability to flexibly realize three types of FOMEs, which is more functional. Therefore, the proposed FOME emulators provide a new idea for the realization of simple and useful FOME emulators in the future.

Conclusion
This paper presented a novel universal interface circuit. The emulators of FOMR, FOMC and FOMI may be realized when Z 1 and Z 2 are selected using different impedance elements. Theoretical analyses are undertaken to verify the operation of these designed FOME emulators. SPICE simulations are undertaken in PSPICE to perform circuit analyses, and MATLAB simulations are used for dynamical analyses, presenting the influence of fractional-order parameters and excitation frequencies on the PHL of the FOME emulators, as well as the range of the fractional-order memductance, the fractional-order memcapacitance and the inverse fractional-order meminductance. From the consistency between our theoretical analyses and simulation results, we can see that the fractional-order parameter provides an extra degree of freedom and increases the controllability on memory-based systems. The newly proposed floating universal interface will facilitate further FOMR, FOMC and FOMI-based research by providing a method to emulate three types of FOMEs. Compared with other similar research work, the FOME emulators based on the proposed universal interface in this paper have the following advantages: 1) have floating terminals; 2) have reconfigurability among the three types of FOMEs that are not based on any other mem-emulators; 3) simpler circuit structure. Our proposed interface provides value for the future research, development and application of FOMEs.