Optimization of Heat Transfer Process in Double Gate MOSFET Using Modified BDE Model


 In this paper, a nonlinear electrical model is derived and is used to calculate the electric field and the current density. To corroborate our electrical model, it was compared to TCAD simulator. It was shown that the proposed model captures the current density with a good degree of agreement with TCAD simulator. The electrical model is given by the modified Drift-Diffusion (D-D) model coupled with the Ballistic-Diffusive Equation (BDE) which is able to predict the heat transfer phenomenon in the nanoscale regime. The thermal device performance is then investigated by varying device parameters including gate and drain biases with implementation of different gate dielectric to explore its response on thermal characteristics. It was further shown that the proposed electro-thermal model is able to predict the nano heat conduction in (DG) nanostructure devices. In addition, it is shown that the heat flux process could be controlled by adjusting the drain and gate voltages.

In order to overcome these technological defies several numerical and experimental works have been done in recent years. Kown et al. [12] have studied the effect of negative capacitance (NC) in Fully Depleted Silicon-On-Insulator (FD SOI) transistor reliability. They have demonstrated that an improved short channel performance was obtained due to the reverse drain induced barrier lowering characteristics of the NC operation. To better control the short channel effect, Wenstead et al. [11] have combined a thin SiGe channel with a nonband edge gate electrode. They found that this approach effectively solve some of the difficult associated technological challenges. The short-channel scaling of ultrathin SOI MOSFETs was analyzed by the generalization of 2-D numerical simulations by Xie et al. [17]. They found that, like a bulk MOSFET, the short-channel effect of an SOI MOSFET can be described by a scale length. As well, they proposed that the short-channel effect of SOI MOSFETs can be improved by applying a reverse bias to the substrate to push the inversion channel from the back surface to the front. Further, Chen et al. [18] have studied the electrothermal effects on hot-carrier injection (HCI) in 100-nm silicon-on-insulator (SOI) MOSFET for a digital integrated circuit. They proved that the buried oxide layer leads to a high temperature in the channel and deteriorates the HCI. In their reports, Swahn and Hassoun [19] have studied the self-heating in multi-fin devices by the development of thermal models for single-fin flared channel extension and for multi-fin devices. To measure the device thermal robustness, they have developed a metric for electro-thermal sensitivity.
To better predict the thermal transport in nano-transistors, we are obliged to replace the Fourier Law, which is invalid in the nanoscale regime [19]. Instead, Tzou [19] proposed a new thermal model which is able to predict the heat conduction in the nanoscale regime. From the Boltzmann transport equation, Chen [20] has developed a new model named, Ballistic Diffusive Equation (BDE), which represents a good approximation for the heat conduction in the nanoscale regime.
In order to improve the electrical properties of nano DG-MOSFETs, many works have used the high-k dielectric material as a gate oxide such as TiO2 [21], Al2O3 [22] and HfO2 [23].
In this report and in order to improve the electro-thermal effects of a 22nm DG MOSFET, we have used a nonlinear transient analysis model, which can be used to investigate phonon scattering and electron transports in a 22 nm DG-MOSFET. We report the drain-source and gate-source voltage effects and high-k dielectric material role on increasing the operation temperature in the analyzed structure. In the first step, we have compared the transfer characteristics and the temperature evolution given by the proposed model with those available in the literature. Then, we have studied the effect of HfO2 gate oxide on the electro thermal properties of the proposed structure.

2) THEORY AND FORMULAS
In order to predict the electro-thermal properties of the proposed structure, we have used a When the Fourier low ceases to be valid, we use a thermal model, which can be valid in nanoscale regime. In this work, we have used the DPL model.

A. Continuity and Poisson equations
To predict the electric characteristics of MOS structures, the well-known electron and hole continuity equations coupled with Poisson's equation have been used. Electrons and holes transport equations are given by: Where n and p are the electron and hole concentration respectively. Jn and Jp are the electron and hole current densities.
Where µn and µp are the electron and hole mobilities and (R-G) is the generationrecombination rate. In this work, this quantity is given by where p0 and n0 are the intrinsic carrier concentrations, τn and τp are the electron and hole lifetimes. In this work, in order to be close to the reality, µn and µp are given by [24]: The typical value of The threshold voltage used in our simulation is given by: where T0 = 300 K, k is the threshold voltage temperature coefficient (a typical value is 2.4 mV/K) [25].
To analyze the electric potential in the proposed structures, we have used the Poisson equation: where ɛ is the permittivity, V is the electrical potential, and ND and NA are the donor and the acceptor concentrations. The electric field is related to the electric potential by a gradient

B. BDE model and heat conduction equation
The heat transfer equation related to the BDE model is expressed as follows [19]: where Q represents the volumetric heat generation rate due to the Joule effect, τR is the phonon relaxation time, Keff is the effective thermal conductivity and C represents the volumetric heat capacity. The volumetric heat source Q is determined by modified D-D model and it's given by [9]: where KB represents the Boltzmann constant and the band gap Eg is given by: in which 0 g E (eV) denotes the band gap at ambient temperature.

C. Structures and Boundary conditions
In practice, a SiO2 layer encounters the left and the right sides of the transistors and the ambient temperature is T0=300 K. For this reason; ∂n/∂y = ∂p/∂y = ∂V/∂y = ∂T/∂y = 0 The drain boundary side is given by the VDS voltage, VGS is applied on the gate side and at the source side Vss = 0.
A 22 nm Symmetric Underlap DG MOSFET is selected for nano electro-thermal simulation to predict its thermal stability. The 22 nm DG MOSFET structure under investigation is shown in Fig. 1a.
In their report, Chattopadhyay et al. [27] gives all the parameters of the analyzed devices.
The height of the SiO2 interfacial layer was about 0.45 nm and the height of the HfO2 layer was about 1.9 nm. In order to provide higher physical gate height to the device, the HfO2 layer is placed over the SiO2 layer [27]. We validate the electric part of the proposed model with data obtained from Chattopadhyay et al. [27].  Table. 1 [28].

3) RESULTS AND DISCUSSION
To validate the electrical part of the present model, we show in Fig. 2 a comparison of the output characteristics for VDS=0.85V.
It is obvious that the electrical current obtained by the simulations have the same characteristics as the data obtained using TCAD simulation [27].  The effect of VDS becomes obvious for t=50 ps and an increase in the temperature with a few degrees appears clearly. It should be noted that this effect is nonlinear and it is more obvious for large values of VDS.  has achieved a constant value in the substrate zone. We show also that the temperature keeps a constant value between the two oxide/semiconductor interfaces. However, an important increase of the temperature was observed by crossing the interfaces. This is due to the phonon walls collisions and phonon scattering between the two walls (oxide/semiconductor interfaces) of the analyzed structures. The diffusion of the heat inside the device mitigates the maximal temperature achieved. Fig. 9 depicts a comparison of the temporal temperature evolution in the centerline of the transistor with and without high-k dielectric material using VGS = VDS = 0.9 V. It appears clearly that the temperature evolution keeps the same trend with different amplitudes. At t= 50 ps, the achieved temperature was 315 K, when we use only the SiO2 dielectric gate oxide.
When a coupled oxide (SiO2+ HfO2 layers) was used, the temperature achieved was 310 K.
Besides, when a layer of HfO2 was involved, the lateral heat conduction was modified and consequently, the maximal temperature reached is affected.
In Fig. 10, a comparison of the temperature profile versus Y-axis with and without HfO2 oxide layer at VGS = VDS = 0.9 V and t = 50 ps was presented. It can be seen that the temperature is almost constant at the value 314 K when a single oxide layer (SiO2) is employed. In contrast, when the two layers of HfO2 and SiO2 are used, the temperature decreases and a value of 310 K was achieved between both channel regions.

4) CONCLUSION
In summary, a comprehensive study of phonons and electrons transport in a 22 nm DG MOSFET transistor by using a nonlinear electro-thermal model was successfully reported.
We found that the phonon transports and following that the temperature distribution can be controlled by adjusting the drain-source and gate-source voltages in nanotransistors. In a technological viewpoint, the important increase of the operation temperature in the analyzed DG-MOSFET remains lower than that given in a 22 nm FD-SOI-MOSFET. Indeed, we have also demonstrated that phonon scattering in the DG-MOSFET, (between two oxide/semiconductor interfaces), is considerably influenced by adding the HfO2 layer. The use of a High-k dielectric layer decreases considerably the phonon transport in nanodevices which is necessary to limit the self-heating mechanisms.