A bulk-driven quasi-floating gate regulated cascode current mirror and its application in squarer circuit

A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (I in ) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and 0.8 V respectively. The designed chip of the proposed BD-QFG RGC CM occupies an area of 29.4 μm 2 . To show the workability of the proposed circuit, a new squarer circuit has been presented.


INTRODUCTION
Low voltage and low power circuit is demanded in portable electronics to extend the battery lifetime. For analog circuits, higher threshold voltage CMOS technology imposes a serious degrading circuit performance [1]. In the literature, diverse techniques unconventional have been developed to construct the low supply voltage and the low consumption CMOS circuits. The important techniques are the floating-gate (FG) [2], the quasi-floating-gate (QFG) [3] and the bulk-driven (BD) [4]. These techniques have many advantages and disadvantages. The disadvantages of the unconventional techniques (FG, QFG) in comparison to the conventional technique (GD) are the reduction of the effective transconductance, the high occupied chip area and the lower output impedance. Although, these techniques (FG, QFG) offer the possibility of multiple inputs. Moreover, the threshold voltage can be reduced in the FG and QFG techniques [5]. For the BD technique, the threshold voltage is removed, and it can process DC signals. The disadvantage of the BD MOST is the lower transconductance than the FG, QFG and GD MOST. A two new MOS techniques Bulk-Driven Floating-Gate (BD-FG) and Bulk-Driven Quasi-Floating-Gate (BD-QFG) are firstly presented in 2014 [6], experimentally verified and published in the literature [7]. The BD-QFG technique has revealed all the advantages of BD and QFG techniques and suppress their limitations. The symbol of the BD-QFG MOST is shown in Fig. 1.a, and their equivalent circuit is exposed in Fig. 1.b [14]. In this technique, the input signal (Vin) is applied to the quasi-floating gate and to the bulk terminal through the capacitance Cin. The quasifloating-gate terminal of the BD-QFG MOST is connected by a very high value resistor (Rb) to an appropriate bias voltage (Vbias). Practically, this resistance (Rb) is implemented via transistor MR operating in the cutoff region. The current mirror (CM) structure is an important circuit in many applications, such as the conveyors, the multiplier, the comparator [1], the OTA, the ADC [8], [9] and the DAC. Various researches have been reported to attain the perfect performance of the CM circuit. The characteristic of the CM has a direct impact on the efficiency of the integrated circuits [10]- [12]. The CM presented in [13] is characterized by a low input impedance and a high output impedance. These types of CM are needed to minimize the loading effect. But it has a very high supply voltage and power operation. In [14], using the unconventional technique (BD), a CM circuit is introduced to surmount the limitation of the high supply voltage of the technique GD. This circuit presented an amelioration in terms of power consumption and supply voltage, but it has low bandwidth. High bandwidth in a CM is an important characteristic of increasing the speed of devices. In [15], the CM employs the BD-QFG technique. It presents amelioration in terms of low supply voltage and low input impedance, but it suffers from lowered output impedance and a high number of transistors. Based on the advantages of the unconventional technique (BD-QFG), a new regulated cascode CM circuit is proposed. The interesting performances of the proposed circuit are low voltage supply, high bandwidth, low consumption, and high output impedance. The proposed circuit is employed to realize a high-performance squarer circuit. This paper is arranged as follows. Section 2 presents the proposed BD-QFG RGC CM and calculates its significant performances.
Simulation results are presented in Section 3. Section 4 presents the application of the proposed CM. Finally, Section 5 concludes the paper. In this part, the operation and implementation of the conventional and unconventional CM are discussed. The conventional RGC CM proposed in [16] is shown in Fig. 2.a. This circuit is composed of a simple CM (M1, M2) and an amplification stage. The amplification stage is consisting of a transistor M4, a current source IB1, and a cascode transistor M3. This structure provides a high output impedance owing to the negative feedback offered by the transistor M4 and the bias current IB. This circuit performs a low supply voltage and high output impedance. Due to the augmented demand for smaller electronic devices, reducing the supply voltage, removing the threshold voltage, reducing the input impedance and lowering the power consumption becomes necessary. The unconventional BD-QFG transistor has a high transconductance near to the transconductance of the GD technique, and it can be presented [6], [7]: The small signal analysis for calculating the output impedance of the proposed circuit, is presented in Fig. 3.
From Eq. (1) and (8), it can be noticed that the output impedance of the BD-QFG RGC circuit is near to the conventional GD RGC circuit.

Bandwidth:
For calculating the bandwidth, the small signal analysis is presented in Fig.4. Assume: At node1: At node2: At node3: From Eq. (10) and (11), the expression of V2 is found as: The equation for the transfer function is given as follows: The expressions for the gain and the pulse are expressed as follows: Usually 02 01   and 02 03   , the expression of the transfer function has become in the following form:

Simulation Results
The performance of the GD RGC and the proposed BD-QFG RGC is verified through cadence simulator based on 90 nm CMOS parameters under a 0.8 V supply voltage. The conventional and unconventional RGC CM shown in Fig. 2 have been simulated in the same environment to provide an appropriate comparison. The dimensions of transistors and element values of the GD RGC and the BD-QFG RGC CM are identical. For the conventional RGC CM, the current source IB1 has been designed by using a transistor M5.    Fig. 10 present the resulted output current of the conventional and unconventional RGC CM for a sinusoidal input current signal with a frequency of 10 KHz and a peakto-peak value of 100 µA, the total harmonic distortion (THD) is respectively 1.5% and 0.4%. The Monte-Carlo analysis is presented of 500 runs for an input current 200 μA for some important specifications including the bandwidth, the current transfer error, and the output impedance. From Fig. 11, it is seen that the proposed CM does not present an important degradation within the mentioned specifications.
The layout of the proposed BD-QFG RGC CM has been done by using 90 nm process technology with cadence virtuoso. The total chip area was 4.2 µm × 7 µm (29.4µm 2 ). The layout simulation is shown in Fig. 12. The BD-QFG technique shows the best performance in the current mirror design in terms of low supply voltage, low current transfer error, low output voltage and low THD value. While the other parameters (frequency, output impedance, and consumption) are close for both techniques. The comparative study between the BD-QFG RGC CM and GD RGC CM is summarized in Table 1.
The validity of the layout is confirmed by using the postlayout simulation. Table. 2 present a comparison between the post-layout and the pre-layout simulations. From this table, it is clear that the variations between the pre-layout and the post-layout simulations are very weak. The simulation results of the proposed BD-QFG RGC CM are presented with other works in Table. 3.

BD-QFG squarer circuit
The squarer circuit is an important circuit in the design of many integrated circuits. It is can be used in many applications such as the current multipliers, the automatic gain controlling, the frequency doubles and the modulator circuit.
The implementation of the conventional and unconventional squarer circuit is discussed in this part. The conventional squarer circuit presented in [21] is shown in Fig. 13.a. This structure is composed of simple current mirrors based on the conventional (GD) technique. According to the abovementioned advantage of the proposed BD-QFG RGC CM, a new squarer circuit is proposed. Fig. 13.b shows the proposed BD-QFG squarer circuit. The transconductance of the BD-QFG MOST operating in the saturation region is determined by [6]: Where CTotal is the capacitance seen from the QFG, Cin is the input capacitance between the QFG and the input-terminal, CGC is the gate channel capacitance, and CBS is the bulk channel capacitance. Using Eq.
The threshold voltage (VTH) is removed in BD-QFG technique [6]. The equation of VGS can be presented as:

. Simulation results
The simulation results of the conventional and the proposed squarer circuit are simulated through Cadence simulator using 90 nm CMOS technology parameters with 0.8 V supply voltage. The conventional and the proposed square circuit have been verified in the same environment to provide a proper comparison. The bias current (IB) is 20 μA, the input current (Iin) is varied from 0 μA to 100 μA. The DC analysis of the conventional and the proposed squarer circuit is presented in Fig. 14 and the transient analysis is shown in Fig. 15 with an input signal triangular for 1 MHz frequency and for 100 μA amplitude. The Nonlinearity Errors analysis of the conventional and the proposed squarer circuit are respectively 41% and 0.5%. The simulations of frequency show in Fig.16 a -3 dB are 320 MHz and 1.2 GHz respectively of the GD and the proposed BD-QFG squarer circuit. Monte Carlo analysis of the proposed squarer circuit of the bandwidth has been presented in Fig. 17. The simulation results of the proposed BD-QFG squarer circuit are presented with other works in Table. 4.

Conclusion
In this paper, a new low voltage low power BD-QFG RGC CM circuit is presented. It is the modified version of the conventional GD RGC CM. This proposed BD-QFG RGC presents a better linearity performance than the GD RGC. The proposed BD-QFG RGC has a 0.2% error current which 11.8% better than the GD RGC (12%), a high output impedance (15 GΩ) and a low power consumption (22.71 µW). The proposed circuit enjoys a higher frequency value (2.31 GHz) near to the frequency value of the GD-MOST (2.36 GHz). The THD value of the proposed RGC CM is 0.4% which is 1.1% less than the conventional circuit (1.5%). The mismatch variation of the proposed RGC is presented using Monte Carlo analysis and this layout simulation is also presented. An application of the proposed BD-QFG RGC CM is presented in the form of squarer circuit to ensure the workability of the proposed CM.