Effect of Polymer Liners in Different Via Shapes: Impact on Crosstalk Induced Delay

The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material SiO 2 is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 nm and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T -type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.

Three-dimensional integrated circuits (3D ICs) have been proposed as a prospect for developing more-than-Moore technology. A Through Silicon Via (TSV) based threedimensional integration has the capability to provide the highest vertical interconnect density while providing a compact footprint, enhanced efficiency, and heterointegration capacity [1,2]. TSVs with shorter interconnect lengths, and higher density primarily provides smaller form factor, lower power consumption, and higher bandwidth than wire bonding and micro-bump chip stacking techniques [3,4]. A cylindrical TSV is advantageous over the square, coaxial, and tapered TSVs due to its uniform structure, high breakdown voltage, and simplicity of electrical modelling. At low frequencies, it also outperforms other TSV structures in terms of heat dissipation [5]. However, the cylindrical TSV demonstrates a significant worst-case crosstalk induced delay and less conductivity compared to the other shapes due to more footprint area [5]. In this regard, a coaxial shaped TSV can be considered in terms of less footprint area and improved noise performance. Additionally, a coaxial TSV provides a reduced coupling with its surroundings due to the insulator based guard ring structure. However, as per the fabrication house, the formation of this guard ring between the inner and outer conducting filler is still a challenging task. Therefore, a tapered TSV is preferred due to its straightforward fabrication, less footprint area, balanced power and thermal distribution in 3D ICs [5]. Additionally, the tapered TSV has a reduced electrical resistance [6], less reflection noise, and power loss. Apart from the different via shapes, it is equally important to choose an appropriate filler material for TSV. In general, copper (Cu) is preferred as via filler material for its silicon compatibility, straightforward fabrication and testing process [7]. However, the coefficient of thermal expansion (CTE) of Cu (16.5ppm/K) is significantly higher than that of silicon (Si) substrate (2.6ppm/K), and hence a CTE mismatch can occur between the Cu and Si. It results in Cu pumping and interfacial delamination that affects the overall performance of a TSV [8]. In this regard, polymer liners with lower CTE values, elastic modulus, dielectric constants, and more uniform thicknesses can be adopted in TSVs to prevent the thermal stress problem commonly encountered in Cu filled TSVs. The capacitive coupling of TSVs can be reduced by substituting polymer liner instead of silicon dioxide (SiO 2 ) liner that results in superior performance. Therefore, a proper TSV shape with an appropriate liner material is important for the analysis of via performance.
Previously, Savidis and Friedman [9] demonstrated the electrical modelling of cylindrical shaped TSVs to obtain closed-form expressions of resistance, inductance, and capacitance. However, a maximum difference of 8% between the results obtained from the closed-form expressions and the simulations have been observed. Afterwards, Katti et al. [10] encountered the difference while demonstrating the validity of the proposed RLC model using numerical simulators and experimental measurements. However, the suggested approach was only appropriate for the modelling of TSVs with small-geometries. Later, Gerakis and Hatzopoulos [11] proposed an Improved Transmission Line Model (ITLM) to compute the resistance and inductance of the cylindrical TSVs operating at high frequencies. However, the authors limited their discussion only to the cylindrical shaped TSVs. In order to address the other different via shapes, Xu and Lu [12] investigated the electrical performance of a coaxial TSV in terms of latency, crosstalk and power by considering the processing materials and physical geometries of the TSV configuration. Although the researchers addressed the via performance using a coaxial TSV but neglected the impact of a cylindrical and tapered shape. Afterwards, Su et al. [13] developed closed-form expressions based on Maxwell's equations to calculate the capacitances of the insulator and substrate for a tapered shaped TSV. The results indicated that the tapered TSVs had a longer delay and less crosstalk than cylindrical TSVs. Moreover, the expressions were considered suitable for TSVs with a high aspect ratio (AR), and a maximum of 4% errors between the calculated and simulated results was observed. Later, Nabil et al. [14] addressed the error by presenting electrical modelling of tapered TSVs at high frequency using the Transmission Line Method (TLM). In the proposed electrical model, the authors have considered substrate coupling and MOS effects. Although detailed analyses have been performed for modelling of TSVs with different shapes but the impact of the coupling capacitance is constrained only to the SiO 2 liner. In recent, Murugesan et al. [15] used a TSV structure wherein a Polymide (PI) liner with a low modulus value was employed instead of SiO 2 to reduce Cu extrusion, interfacial delamination, thermal stress between the TSV metal and the Si substrate, and the keep-out zone. However, the charge-trap density in the PI layer is relatively high that resulting in modulation of the parasitic capacitance existing between TSV metal and the Si substrate. Apart from this, Kino et al. [16] used Polybenzoxazole (PBO) as the polymer liner material of TSV to reduce the capacitance modulation. Subsequently, a Polypropylene Copolymer (PPC) liner was also used to further reduce the insulating capacitance of the TSV, which resulted in a 25 % [17] and 30 % [18] reduction in crosstalk compared to the conventionally used TSV structures. Later, Su et al. [19] proposed the development of low capacitance TSVs by replacing the SiO 2 liner layer with a Benzocyclobutene (BCB) polymer liner, as well as the reduction of thermal expansion stress and leakage current. Based on the above state-of-the-art research [9][10][11][12][13][14][15][16][17][18][19], it can be inferred that a comprehensive analysis of modelling of various TSV shapes with the impact of different liner materials is required to address. Moreover, a detailed investigation is required to apostrophize the worst case crosstalk induced delay of TSVs by taking all physical geometries into consideration.
In order to address the above-mentioned research problems, the paper, for the first time, presents electrical modelling of different TSV shapes along with the impact of liner materials to address the crosstalk performance. A crosstalk induced delay and noise can be demonstrated by Miller's effect, according to which a victim line experiences an increased coupling capacitance when opposite input signals are sent to the neighbouring TSVs. Due to this, a voltage spike (peak noise) can be observed on the victim line that affects the TSV performance. In order to observe this phenomenon on different via shapes, a closed-form expression is obtained for modelling of cylindrical, tapered, and coaxial TSVs. During the RLGC modelling of the TSV, the influence of Metal Oxide Semiconductor (MOS) is also taken into account. The liner and depletion layers are used to insulate the TSV from the Si substrate that helps to reduce the crosstalk effect between neighbouring TSVs. Similarly, the Inter Metal Dielectric (IMD) layer isolates the bumps from the Si substrate to minimize leakage. An underfill layer is provided to separate the bumps to avoid cross-coupling and inter-bump leakage. Considering all the aforementioned facts, the crosstalk induced delay performance of a TSV pair is investigated in detail using a driver-via-load (DVL) setup wherein the TSVs are modelled using Cu as a filler material with several liner materials such as SiO 2 , PI, PPC, PBO, and BCB. The equivalent circuits are modelled at the 32 nm and 45 nm technology employing a coupled DVL with a CMOS driver. The fundamental reason behind choosing the aforementioned technology parameters is that the use of a liner beyond 32 nm increases the leakage and is hence inappropriate for low-power and highperformance applications. Additionally, the electrical circuit models are implemented using a specific T-type network. Due to such modelling of the via line, the capacitive charging current flows through half of the via line, which results in reduced crosstalk interference between the coupled TSVs.
The following is the structure of this paper: Section I provides an insight into the current state-of-the-art research situation and describes the modelling of differently shaped TSVs while considering the effects of polymer liners. The physical configuration of various TSV structures, the critical design parameters and their equivalent electrical models are presented in Section II. The detailed analytical equations for modelling cylindrical, tapered, and coaxial TSVs employing various liner materials are also developed in this section. Section III examines the impact of various liner materials in TSV, examining the impact of liners for different aspect ratios of TSV and the impact of liners in various TSV shapes. Finally, this work is summarized in Section IV.

TSV Configuration and Equivalent Model
This section includes the modelling configurations of cylindrical, tapered, and coaxial TSVs at 32 nm and 45 nm technology. Furthermore, a high-frequency equivalent electrical model of a TSV pair is presented for a variety of via shapes that consist of the effect of the liner, underfill layer and the bump. The analytical RLGC model expressions are used to develop these models based on the T-type network with 20 distributed sections. Accurate physical parameters and material properties are used as variables in the analytical RLGC equations. Consequently, novel equivalent electrical models of cylindrical, tapered, and coaxial TSVs are presented, considering the impact of various liner materials in the following sub-sections

TSV Structure and Physical Configuration
This sub-section presents a thorough understanding of the TSV structure and quantitative values of physical parameters and material properties that are employed in the modelling of equivalent RLGC models. The physical configurations of cylindrical, tapered, and coaxial TSVs are shown in Figs. 1 (a), 1(b), and 1(c), respectively. The , , , and ℎ represent the thickness of the liner layer, TSV diameter, depletion layer thickness, and via height, respectively for cylindrical, tapered and coaxial shapes. For a tapered shaped TSV (shown in Fig. 1(b)), , 1 , and ,1 represent the slope angle, bottom radii of the TSV and the liner, respectively, whereas , represents the thickness of the inner insulating layer of a coaxial TSV (shown in Fig. 1(c)).
Considering the different TSV shapes, Tables 1, 2 and 3 summarize the via physical parameters, material properties of TSV, liner and filler, respectively. In order to consider the MOS effect (shown in Fig. 1(d)), it is required to surround the TSV metal with a dielectric, such as a liner layer, to isolate the via filler from the Si substrate. TSV liner can be composed of SiO2 or a variety of polymers such as PBO, BCB, PI, PPC, etc. Apart from this, a depletion layer is used to enhance the isolation between the TSV metal and the Si substrate to prevent inter-metal leakage. Lossless silicon is primarily utilized as the depletion layer, wherein the losses are at their lowest levels. Additionally, an Inter Metal Dielectric (IMD) layer is employed to minimize the leakage between the bump and Si substrate. An underfill layer, composed of anhydride resin polymers, is used to physically isolate the bumps while reducing cross-coupling and leakage. The bump comprises Cu as filler, is used to connect the TSVs with the functional block of the dies. Lossy silicon material is used as a substrate in this application.

Equivalent Electrical Model of TSV
This sub-section demonstrates the modelling of Cu based TSV by considering the geometry of tapered, cylindrical, and coaxial shapes (as shown in Fig Table 1) are used to develop closed-form equations of RLGC parasitics of TSVs, as demonstrated in the following sub-sections.

Equivalent Resistance
Using the accurate physical configurations (Shown in Fig.  1) of different TSV shapes, this sub-section demonstrates the modelling of equivalent resistance considering the physical geometries of TSVs. As shown in Fig.2, the equivalent electrical models of tapered, cylindrical, and coaxial TSVs are presented by following a 20-distributed T-type network.
When an induced electromagnetic field propagates along TSV metal and bumps and penetrates through the material surfaces, it causes equivalent resistance that represents the heat dissipation in TSV metal and bumps. Thus, the equivalent resistance ( ) can be defined as = × ℎ ; where is the p.u.h. equivalent resistance as shown in Fig. 2 Considering a tapered TSV, the equivalent resistance ( ) ) of Fig. 2(a) can be expressed as ) (1) The "skin effect" refers to the phenomenon in which high-frequency current flows near to the surface of a conductor due to the development of eddy current. Skin depth is obtained to model the TSV and bump resistances ( ) and ) ) with a non-uniform current distribution at high frequencies. Therefore, ) and ) (mentioned in Eqn. (1)) can be expressed as represent the skin depth of the bump and the proximity factor, respectively, and = , θ is taken as 15° [13].

Equivalent Inductance
Inductance is a property of a conductor that opposes the sudden change in amplitude and direction of current when the current flows through it. Equivalent via inductance plays a key role for an increasing operating frequency. As shown in Fig. 2, the equivalent inductance ( ) can be expressed as where is the p.u.h. equivalent inductance as shown in Fig. 2.
As the current-carrying conductor (ex. TSV and bump) generates a magnetic field which results in the development of emf that resists the change of current flowing through the conductor. Hence, the TSV and bump inductances ( ) and ) ) come into existence in TSV and bump, (c) respectively. Considering a tapered TSV, the equivalent inductance ( ) ) of Fig. 2(a) can be expressed as (4) where ) and ) represents the inductances of TSV and bump, respectively. Therefore the ) and ) can be obtained as Whereas, for a cylindrical TSV, the equivalent inductance ( ) = 1 ) = 2 ) ) can be calculated using Eqn. (4) wherein the ) can be derived as Also, the bump inductance ( ) = 1 ) = 2 ) ) of cylindrical TSV can be calculated from Eqn. (4b).
In addition, considering a coaxial TSV, the expressions of inner equivalent inductance (

Conductance
Another critical design parameter is the Si substrate conductance ( ) that exists between TSV pairs due to the lossy nature of the Si substrate. It has a substantial impact on the insertion loss of a TSV as Si conductivity ( ) is the primary cause of this conductance that is governed by majority carrier concentration. Therefore, the can be expressed as = × ℎ ; where is the p.u.h. Si substrate conductance as shown in Fig. 2.
For a cylindrical TSV, the expression of ) can be obtained as where ℎ = ℎ − ℎ Similarly, the expressions of Si substrate conductance of tapered TSV ( ) ) and coaxial TSV ( ) ) can be obtained from Eqn. (6).

Capacitance
The capacity to store electrical energy is referred to as capacitance. In TSV, the charge accumulation occurs because of the existence of dielectric material between the two conducting materials. Due to this, a potential difference across the conducting materials appears due to the accumulation of charge. Thus, the amount of charge accumulated is known as capacitance. There are different types of capacitive parasitics associated with TSVs that can be defined as ) in a coaxial TSV.
The above-mentioned capacitances are described in brief in the following subsections.

Substrate Capacitance
A capacitive coupling exists between the TSVs since the Si substrate is a semiconducting material with a considerable relative permittivity value that functions as an insulator. Hence, the substrate capacitance ( ) between two parallel TSVs is an important parameter that needs to be considered. In general, can be expressed as where is the p.u.h. Si substrate capacitance as shown in Fig. 2.
Considering a pair of tapered TSVs (shown in Fig. 2(a)), the TSVs are divided into an infinite number of small elements (as shown in Fig. 3(b)). The substrate capacitance of the element ) ) can be considered as the parallel-wire capacitance. Therefore, the total capacitance of the infinite differential capacitors in parallel is equal to the substrate capacitance ( ) ), which can be obtained as Eqn. (7) can be expanded in the Taylor series. After simplification, the expression of ) can be expressed as For a pair of cylindrical TSVs, the parallel-wire capacitance model can be used to describe the capacitance of the Si substrate (as shown in Fig. 3). The expression of ) can be obtained as Similarly, the Si substrate capacitance of a pair of coaxial TSVs ( ) ) can be obtained by using Eqn. (9).

Equivalent Capacitance
The equivalent capacitance ( ) is a parallel combination of insulating capacitance ( ), upper bump capacitance ( 1 ) and lower bump capacitance ( 2 ). In general, can be defined as = × ℎ ; where is the p.u.h. equivalent capacitance as shown in Fig. 2.
Considering a pair of tapered TSVs, the expression of ) can be obtained as Where an insulating capacitance ( ) ) is the series combination of liner and depletion capacitances ( ) and ) ) that can be obtained as A liner capacitance ( ) is formed between the TSV metal and the Si substrate due to the presence of a liner layer. In order to obtain the expression of ) , a tapered TSV without a depletion layer is depicted in Fig. 3(a). Here, , h, , 1 and 2 represent the liner thickness, TSV height, slope angle, lower radius and upper radius of the tapered TSV, respectively. As indicated in Fig. 3 (b), the tapered TSV can be subdivided into an infinite number of small cylindrical sections with a height of dz. There is a de charge associated with each small cylindrical element and the potential difference between the TSV metal and the Si substrate can be defined according to the Gauss law [13] as = ∫ ⃗ .
,1 + 1 + ⃗⃗⃗⃗ = 2 ( where, = 2 , = , ,1 = . and θ is taken as 15° [13]. Therefore, the equivalent liner capacitance is constituted of the capacitances of infinite differential capacitors connected in parallel. Hence, ) can be obtained as After simplification, the first three terms of the Taylor series expansion of Eqn. (11b) can be given as where, = 0.07 5 ) 3 1+ 5 ) 3 is defined as an error factor. The lower cross-sectional view of a tapered TSV with a depletion layer is demonstrated in Fig.3 (c). Since the depletion layer has a structure that is similar to that of the liner layer, the capacitance of the depletion layer ) ) can be calculated from Eqn. (11d) considering 1= ,1 , ,1 = , and = ( − ,1 ). 1 ) and 2 ) exist between the upper bump and the Si substrate due to the IMD layer and between the lower bump and the Si substrate due to the bottom insulating layer, respectively. These capacitances can be represented mathematically as parallel-plate capacitors.
Similarly, considering a pair of cylindrical TSVs, the expression of equivalent capacitance ) ) can be expressed using Eqn. (10)

Underfill, IMD, and Bottom Capacitances
As shown in Fig. 2, the and are the parallel combinations of IMD ) and bottom ( ) capacitances with an underfill capacitance ), respectively and can be defined as where and are the p.u.h. UI and UB capacitances as shown in Fig. 2.
Considering a pair of tapered TSV, an underfill capacitance ( ) ) exists between the upper (or lower) bump of 1 and the upper (or lower) bump of 2 due to an underfill layer. Likewise, an IMD capacitance ( ) ) occurs between 1 and 2 due to the presence of an IMD layer. Similarly, a bottom capacitance ( ) ) forms between 1 and 2 due to a bottom insulating layer. The TSV and bump have circular cross-sectional areas, so, ) , ) , and ) are derived from the parallel-wire capacitance model. These capacitances are expressed as Considering a pair of cylindrical TSV, the expressions of ) , ) , and ) can be calculated using Eqn. (17), (18), and (19) respectively, considering 2 1 = .
Similarly, for a pair of coaxial TSVs, the expressions of ) , ) , and ) can be calculated using Eqn. (17), (18), and (19) respectively representing 2 1 = . Apart from these capacitances, in a coaxial TSV, an inner-liner capacitance ( , ) ) exists between the inner and outer parts of a coaxial TSV due to the inner insulating layer. The The via parasitics are obtained based on the technology-dependent physical parameters of the TSV. Table 4 presents a list of these parasitic values for different TSV shapes considering an AR of 2.4 at 32 nm and 45 nm technology. Table   4 Parasitic

Aspect Ratio
TSVs at 32 nm technology node using SiO 2 liner TSVs at 32 nm technology node using BCB liner TSVs at 45 nm technology node using SiO 2 liner TSVs at 45 nm technology node using BCB liner

Impact of Liner on TSV
This section examines the effects of various liner materials on the crosstalk induced delay performance of different TSV shapes at the 32 nm and 45 nm technology nodes using their presented RLGC models (as shown in Fig.2). Fig. 4 illustrates a 2-line DVL setup employed for electrical modelling of the TSV with 20 distributed Tnetwork.
As shown in Fig. 4, each TSV line is represented by a set of RLGC parasitic elements, as depicted in Fig. 2. Each TSV line is driven by a CMOS driver with a supply voltage of 0.9V and 1V at 32 nm and 45 nm technology, respectively. As shown in Fig. 4, the capacitive loadings ( ) of 0.1aF at the aggressor and victim lines are taken into consideration. Using the above mentioned DVL setup in Fig. 4, the subsequent sections have analyzed the impact of liner materials on the overall performance of TSVs in terms of crosstalk induced delay for different via shapes and aspect ratios.

Impact of Liners on Different Aspect Ratios of TSVs
This sub-section presents the crosstalk induced delay analysis of cylindrical, tapered, and coaxial TSVs for different aspect ratios of 2.4, 3.0 and 4.0 while considering via heights ranging from 9.6μm to 12. 6μm and 12μm to 20μm at 32 nm and 45 nm technology, respectively. The out-phase dynamic crosstalk induced delay occurs for opposite switching phenomenon that causes worst-case crosstalk induced delay with a significant Miller Coupling Factor (MCF). Hence, in order to calculate the worst-case crosstalk induced delay, the out-of-phase switching transition state is considered in this work. By varying the aspect ratios of TSVs, Fig. 5 (a), (b), and (c) present the crosstalk induced delay of tapered, cylindrical, and coaxial TSVs, respectively with SiO2 and BCB liners at 32 nm and 45 nm technology nodes. It is observed that the TSVs with BCB liners exhibit lesser crosstalk induced delay than the TSVs with SiO2 liners, irrespective of the shape and AR of the TSVs under consideration. The reason behind this is that the BCB polymer dielectric has less ability to support electrostatic forces between TSV metal and Si substrate, and hence the of TSV using BCB is lower than that of SiO2. It is due to a substantially lower dielectric constant of BCB ( =2.65) than that of the SiO2 ( =3.9). In addition, a more consistent thickness of BCB polymer liner (1-5μm) compared to the SiO2 liner (typically 0.1-1μm) results in a reduced liner capacitance in TSVs. From Fig. 5, it is observed that the worst-case crosstalk induced delay at the 32 nm is lesser when compared to the 45 nm technology, regardless of the liner material used or the AR of the TSV. The improvement in crosstalk induced delay using a tapered TSV (as shown in Fig. 5 (a)) at 32 nm w.r.t. 45 nm technology can be observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner. The primary reason behind this is that the quantitative value of via resistance at a lower technology is smaller than that of higher technology, as presented in Table 4. This is owing to the fact that the reduced physical dimensions of TSVs (ex. height and diameter of TSV) at lower technology results in the lesser value of via resistance. Another important observation is that the crosstalk induced delay reduces for a lower via aspect ratio, as presented in Fig. 5. It can be perceived that for a tapered TSV with BCB liner, crosstalk induced delay at an AR = 2.4 is improved by 48.37% and 15.14% at 32 nm and 45 nm technology, respectively compared to the AR = 4. Therefore, it can be inferred that TSVs with a smaller aspect ratio exhibit a large reduction in crosstalk induced delay when compared with TSVs with a larger aspect ratio. This is due to the fact that the crosstalk induced delay of a coupled TSV with a smaller aspect ratio reduces because of its substantially lower value of via resistance and coupling capacitance. The resistance and capacitance primarily reduce for an overall reduction in footprint area at a smaller via aspect ratio.
Considering the crosstalk induced delay in different scenarios (shown in Fig. 5), Table 5 summarizes the percentage reduction in crosstalk induced delay in cylindrical, coaxial, and tapered TSVs for different aspect ratios using SiO2 and various polymer liners w.r.t. the crosstalk induced delay of TSVs using BCB liner. It is observed that using BCB liner rather than SiO2 liner results in a considerable percentage reduction in crosstalk induced delay. With respect to crosstalk induced delay using BCB liner, the overall % reduction in crosstalk induced delay of cylindrical TSV with aspect ratio=2.4 is 39.27%, 34.35%, 29.54%, and 29.38% using SiO2, PI, PBO, and PPC liners respectively at 32 nm technology node; similarly, the overall % reduction in crosstalk induced delay with aspect ratio=4 is 9.36%, 8.54%, 6.04%, and 0.64%, respectively. It is noted that the primary cause for this reduction is the lower quantitative values of liner capacitances in TSV when polymer liners are employed. The reason for this is that the dielectric constants of polymer liners are significantly lower than that of SiO2 liner. In comparison to SiO2 and other polymer liners with relatively larger dielectric constants, the lower dielectric constant of BCB significantly reduces capacitance value that is resulting in reduced crosstalk induced delay. Another observation from Table 5 is that as the aspect ratio changes from a higher value to a lower value, there is a significant percentage reduction in crosstalk induced delay.  This can be observed as the differences in % reduction in crosstalk induced delay of cylindrical, coaxial, and tapered TSVs using SiO2 liner w.r.t. crosstalk induced delay of these TSVs using BCB liner are 29.91%, 16.64%, and 9.03% respectively at 32 nm technology node. Similarly, these differences at 45 nm technology node are 14.42%, 3.99%, and 3.64%. This is because TSVs with a smaller aspect ratio have smaller heights, so the overall areas of the TSVs are reduced, and as a result, the overall crosstalk induced delay is lowered by substantial percentage values.

Impact of Liners on Different TSV Shapes
This sub-section examines the impact of various liner materials on the via performance as defined by the crosstalk delay between the TSV lines. When the TSVs are exposed to high temperatures during the manufacturing process, the large mismatch in CTE values of Cu (16.5 ppm/K); the Si substrate (2.6 ppm/K) and SiO2 (0.5ppm/K) causes considerable stress in the Cu, Si substrate, and SiO2 liner. This phenomenon primarily results in severe physical reliability issues such as die cracking or breaking, copper pumping, and interfacial delamination. The Cu pumping and current leakage caused by the insulator/barrier failure can be prevented by an increasing thickness of the liner. Additionally, the low dielectric constants of polymers and their large thicknesses enable them to achieve low capacitance and improved electrical performance. Figures 6(a) and 6(b) demonstrate the crosstalk delays of cylindrical, coaxial, and tapered TSVs using SiO2, PI, and BCB liners at 32 nm and 45 nm technology, respectively. It is observed that the crosstalk delay of the cylindrical TSV is significantly higher compared to the other via shapes, whereas the least delay can be witnessed using the tapered shape. The cylindrical TSV has larger via resistance and coupling capacitance (as presented in Table 4) than other via shapes that causes a worst-case crosstalk delay. This is due to the lower conductivity of cylindrical shaped TSV owing to its large cross-sectional area and uniform surface. Consequently, the cylindrical TSV possesses a higher value of coupling capacitance that is a function of radius, length, via pitch, and dielectric thickness and increases monotonically for higher radius and reduced via pitch. However, the tapered TSV outperforms the other via shapes in terms of crosstalk delay since it has a lower via resistance and coupling capacitance due to its smaller cross-sectional area and radius, as evidenced from Table  4.
Apart from this, Fig. 6 also demonstrates that the SiO2 liner introduces more worst-case crosstalk delay compared to the BCB irrespective of the via shapes. It is due to the lower dielectric constant of BCB with a thicker polymer liner than the SiO2 that allows to obtain a reduced coupling capacitance. This fact can be demonstrated in terms of the MCF wherein it is stated that during opposite switching transitions of TSVs, the charge provided to the coupling capacitor becomes Q= ΔV, where ΔV is the change in voltage between the TSVs. In this scenario, ΔV becomes 2VDD, where VDD is the supply voltage, and hence the equivalent coupling capacitor can be considered as being effectively twice as large as switching through VDD. As a result, the total charge becomes twice as much required, and the MCF becomes 2 in case of worst-case crosstalk delay [20,21]. Thus, the cumulative effect of the ΔV and the dielectric constant possesses lower worst-case crosstalk delay in the case of BCB liner based TSV. Furthermore, it can be inferred that considering a tapered TSV, the worst-case crosstalk delays using a BCB liner are improved by 32.16% and 26.93% at 32 nm and 45 nm technology, respectively compared to a SiO2. Whereas the improvements using the BCB compared to the PI liner are only 26.48% and 10.21% at 32 nm and 45 nm technology, respectively. Therefore, the BCB liner based tapered shaped TSV has the lower relative dielectric constant ( =2.65) that results in a significant reduction in liner capacitance and hence a reduced crosstalk induced delay.

Conclusion
The paper presented a novel 20 distributed T-type electrical model of cylindrical, tapered, and coaxial TSV configurations at 32 nm and 45 nm technology. The impact of different liner materials on the crosstalk delay of various TSV shapes at a frequency of 20 GHz is investigated. It has been observed that the crosstalk delay is significantly improved at an advanced technology due to its lower via resistance and coupling capacitance. This improvement using a tapered TSV at 32 nm w.r.t. 45 nm technology can be observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner. Moreover, considering a tapered TSV, the improvement in crosstalk delay using a BCB liner has been observed as 32.16% and 26.93% at 32 nm and 45 nm technology, respectively, compared to the SiO2 liner. The above-mentioned results are obtained by considering the influence of the dielectric permittivity, which implies that BCB is the most appropriate liner material for crosstalk applications. Moreover, it is noticed that the tapered shaped TSV causes the least crosstalk delay as it offers a consistent insulating layer that minimizes the leakage from the TSV metal to the Si substrate. Also, its parasitic values are significantly lower due to the smaller surface area compared to the cylindrical and coaxial TSVs. Thus, it can be predicted that a tapered shaped TSV with BCB liner is an appropriate configuration for reduced crosstalk induced delay in 3D integrated circuits.