A wafer-scale van der Waals dielectric made from an inorganic molecular crystal film

Van der Waals dielectrics, such as hexagonal boron nitride, are widely used to preserve the intrinsic properties of two-dimensional semiconductors in electronic devices. However, fabricating these materials on the wafer scale and integrating them with two-dimensional semiconductors is challenging because their synthesis typically requires mechanical exfoliation or vapour deposition processes. Here we show that a high-κ van der Waals dielectric can be created on wafer scales using an inorganic molecular crystal film of antimony trioxide (Sb2O3) fabricated via thermal evaporation deposition. Monolayer molybdenum disulfide (MoS2) field-effect transistors supported by this dielectric substrate exhibit enhanced electron mobility—from 26 cm2 V−1 s−1 to 145 cm2 V−1 s−1—and reduced transfer-curve hysteresis compared with when using SiO2 substrate. MoS2 transistors directly gated by the Sb2O3 film can operate with a supply voltage of 0.8 V, on/off ratio of 108 and subthreshold swing of 64 mV dec−1 at 300 K. Inorganic molecular crystal films of antimony trioxide can be fabricated using thermal evaporation deposition and used as a van der Waals dielectric in molybdenum disulfide field-effect transistors.

of structure, which was confirmed with theoretical calculations. The resulting films are free of dangling bonds and offer superior performance as a substrate to SiO 2 in MoS 2 FETs. In particular, our MoS 2 /Sb 2 O 3 FETs exhibit an on/off ratio of 10 8 , a higher on-state current, enhanced electron mobility (145 cm 2 V −1 s −1 at 15 K, compared with 26 cm 2 V −1 s −1 for the same device on SiO 2 ) and reduced hysteresis by more than an order of magnitude. Based on a quantitative analysis of the hysteresis, we estimate a far lower density of trap states on an Sb 2 O 3 substrate compared with a standard SiO 2 substrate. We also show that by using an ultrathin Sb 2 O 3 film as a gate dielectric, top-gated and back-gated MoS 2 FETs can exhibit a low supply voltage of 0.8 V, on/off ratio of 10 8 and subthreshold slope of 64 mV dec −1 at 300 K.

Fabrication of vdW film
Our vdW dielectric film is fabricated via STED (Fig. 1a) at room temperature. We use the inorganic molecular crystal Sb 2 O 3 (as a powder) as the evaporation source. It consists of ultrasmall Sb 2 O 3 molecules in the form of bicyclic cages (Sb-O bond length of 1.98 Å) [20][21][22] . All the molecules are bonded together via vdW interaction (Fig. 1b). Due to such a weak intermolecular interaction, Sb 2 O 3 molecules are prone to sublimation at elevated temperatures in a high vacuum before melting, without breakage of the Sb-O bonds. Its evaporation temperature is measured to be around 490 °C via thermogravimetric analysis at ambient pressure ( Supplementary  Fig. 1b)-much lower than its melting point (656 °C), which implies the sublimation process of molecules at elevated temperatures. In addition, the evaporation temperature in our high-vacuum chamber with a pressure of 10 −6 torr is estimated to be 186 °C ( Supplementary  Fig. 1c). The molecular vapour evaporated from Sb 2 O 3 powder, A wafer-scale van der Waals dielectric made from an inorganic molecular crystal film Kailang  free of dangling bonds, deposits on the substrate and forms a vdW substrate (Fig. 1a). Our STED process permits the fabrication of a homogeneous wafer-scale film ( Fig. 1c and Supplementary Fig. 2), and the film thickness can be precisely controlled with an ultralow deposition rate of 0.06 Å s −1 (Fig. 1d and Supplementary Fig. 2). Atomic force microscopy (AFM) is used to characterize the morphology of our film. It reveals the homogeneity and flatness of our deposited film at the micrometre scale, without discernible voids or bumps (Fig. 1e,f). The homogeneity of morphology and elemental distribution are also confirmed by scanning electron microscopy and elemental maps of energy-dispersive X-ray spectroscopy ( Supplementary Fig. 3).
To confirm the molecular structure of our deposited film, Raman spectroscopy is employed to probe the vibrational modes of the molecules. We find that all the Raman peaks of the Sb 2 O 3 film can be assigned to the intra-molecule Raman mode (Supplementary  Table 1) and match well with those of the Sb 2 O 3 powder used as the deposition source, implying that Sb 2 O 3 evaporates in the form of molecular vapour with the molecular structure preserved. The stability of Sb 2 O 3 molecules can be confirmed from the perspective of theoretical calculations by investigating the vacancy formation energy within the molecule. The formation energies of typical O, Sb and double O vacancies are found to be over 5 eV (Supplementary   Table 2), indicative of a robust molecule, without the formation of vacancies and dangling bonds. Moreover, we investigate our resultant Sb 2 O 3 film with X-ray diffraction, high-resolution transmission microscopy and selected-area electron diffraction pattern, which further reveal the polycrystalline structure of our Sb 2 O 3 film ( Supplementary Fig. 4). It is worth noting that the benign grain boundaries in the Sb 2 O 3 film are generally free of dangling bonds 23 , which, in principle, would not introduce effective defects into the dielectric.

Dielectric properties of Sb 2 o 3 film
We now investigate the dielectric properties of our Sb 2 O 3 film. To determine its bandgap, a 40 nm Sb 2 O 3 film is deposited on a glass substrate for absorption spectroscopy measurement (Methods). The bandgap of the Sb 2 O 3 film is determined to be 3.95 eV from its absorption spectrum (Fig. 2a), in good agreement with its density of states distribution (Fig. 2b). Such a wide bandgap renders our Sb 2 O 3 film an insulator, as ascertained by the conductive test of a two-terminal device (Fig. 2c). Its resistivity of over 10 9 Ω cm at 300 K can be extracted from the I-V curve (Fig. 2c) Fig. 2d, the current leakage is maintained below 10 −7 A cm −2 (dynamic random access memory (DRAM) limit) at an electrical field of about 2 MV cm −1 for a 10 nm Sb 2 O 3 film. The breakdown electric field of the Sb 2 O 3 film is measured to be around 2.7 MV cm −1 . The measurement for various temperatures ( Supplementary Fig. 7a) and thicknesses ( Supplementary Fig. 7b) demonstrate no obvious impact on such dielectric properties, whereas the charge carriers start to directly tunnel through the ultimate thin dielectric film of 5 nm.
To determine the dielectric constant of Sb 2 O 3 , we fabricate a series of parallel-plate capacitors, using 300 nm Sb 2 O 3 as the dielectric sandwiched between a degenerately doped Si substrate and metal pads. The capacitances are measured with respect to area S at increasing frequency (Fig. 2e, inset). We then extract the static capacitance at low frequency (10 kHz) and estimate the capacitance per unit area as C = 0.34 nF mm −2 . Then, the relative dielectric constant of our Sb 2 O 3 film can be calculated as ε r = 11.5 via the formula C = ε r ε 0 /d, where ε 0 is the permittivity of vacuum and d is the thickness of the Sb 2 O 3 film. Such a high dielectric constant is comparable to typical high-κ Al 2 O 3 dielectric. The low dielectric constant of hBN (~5) (ref. 12 ) is one of its limitations for use in FET applications, whereas our Sb 2 O 3 vdW dielectric, in contrast, possesses a high dielectric constant ( Supplementary Fig. 8) and excellent dielectric properties (Supplementary Table 3) compared with the reported vdW dielectrics.

High-performance device using Sb 2 o 3 substrate
Our Sb 2 O 3 molecular crystal film is free of dangling bonds and has a low density of charge-scattering centres and charge trap states, similar to the typical vdW dielectric hBN. Our vdW film can potentially support high-performance 2D electronic devices of higher mobility and smaller hysteresis. To demonstrate its advantages in this regard, we fabricate 2D FETs on our Sb 2 O 3 vdW substrate and a standard SiO 2 substrate and then systematically investigate their temperature-dependent device characteristics.
The well-studied 2D semiconductor MoS 2 is chosen as a representative channel material and all the FET devices are fabricated using the same processes (Methods). For a clear comparison, our Sb 2 O 3 substrate is composed of a 40 nm film deposited on the standard SiO 2 /Si substrate to fully screen the charged centre and trap states on the SiO 2 substrate (Fig. 3a). Then, 2D MoS 2 flakes are prepared via mechanical exfoliation and transferred onto the substrates. Their thickness is confirmed via optical measurement (Supplementary Fig. 9) and AFM ( Supplementary Fig. 10a,b) before device fabrication. Degenerately doped Si serves as the FET back gate in our measurement (Fig. 3a). To minimize the effect of contact resistance in our devices, we use In/Au metal to form a low-resistance contact 24 with MoS 2 and four-terminal measurement is performed to determine the intrinsic mobility of MoS 2 . Moreover, we also degas all the devices in a high vacuum (10 −6 torr) for 3 h to reduce air adsorption on our device surface before the tests are carried out 25 . The FET based on monolayer MoS 2 supported on Sb 2 O 3 substrate is demonstrated in Fig. 3b. For monolayer MoS 2 , the band offsets at the valence band maximum and conduction band minimum can be estimated from its band alignment to Sb 2 O 3 (the vacuum level at 0 eV, whereas the well-known valence band maximum and conduction band minimum of MoS 2 are extracted from ref. 26 ) (Fig. 3c). These band offsets over 1 eV effectively confine the charges within the MoS 2 channel during device measurement. The ohmic contact of electrodes to 2D MoS 2 and gate control of our FET can be verified from the linear output curves (I ds -V ds ) at 300 K (Fig. 3d). From the typical double-sweep transfer characteristic curves (I ds -V bg ) of monolayer MoS 2 /Sb 2 O 3 FET measured at 300 K (Fig. 3e), we observe a negligibly small hysteresis window. For a clear comparison of the dielectric effect (Sb 2 O 3 and SiO 2 ) on FET mobility, we plot together their electron mobility determined by four-terminal measurement at various back-gate voltages (V bg ) (Fig. 3f). At a low temperature (15 K), when phonon scattering is greatly suppressed and scattering of interface disorders can be more easily identified, it is clear that monolayer MoS 2 supported on the Sb 2 O 3 substrate demonstrates about four times higher mobility (145 cm 2 V −1 s −1 ) than that on the SiO 2 substrate (~30 cm 2 V −1 s −1 ). The temperature-dependent mobility of monolayer MoS 2 decreases at higher temperatures, exhibiting obvious phonon-limited behaviour (Fig. 3g). Quantitatively, the mobility curves governed by phonon scattering follow a simple formula 3,9 : μ FE (T) ≈ T -γ , from which we can estimate γ to be 0.55 and 0.29 for MoS 2 supported on Sb 2 O 3 and SiO 2 substrates, respectively. At room temperature, the mobility of MoS 2 /Sb 2 O 3 remains over 60 cm 2 V −1 s −1 , higher than that of MoS 2 /SiO 2 (19 cm 2 V −1 s −1 ). Considering the application of FETs, we also plot the temperature-dependent mobility of MoS 2 with various thicknesses by two-terminal measurements together for comparison . The comparative advantages of our vdW substrate for a thicker MoS 2 can also be clearly identified, although the mobility improvement becomes less apparent by a factor of 2 (from 40 cm 2 V −1 s −1 on SiO 2 to 90 cm 2 V −1 s −1 on Sb 2 O 3 for trilayer MoS 2 at 40 K). This is generally attributed to the rise in the screening effect for thicker MoS 2 to charged disorders on the underlying dielectric. Interestingly, the MoS 2 thickness more sensitively affects the mobility for SiO 2 -supported devices (mobility changes by a factor of two for monolayer and trilayer MoS 2 ), whereas MoS 2 layers of various thicknesses on Sb 2 O 3 demonstrate similar mobility ( Supplementary Fig. 12). This also implies the low density of disorders on our Sb 2 O 3 substrate, without apparent scattering to the carrier transport of all the MoS 2 channels.
We next investigate the charge trap states of our vdW Sb 2 O 3 and SiO 2 substrates using the hysteresis of our MoS 2 FET. The hysteresis of the transfer characteristic curves features the instability of an FET at work, usually caused by the trapping states located in the channel semiconductors, dielectric, and at their interface, as shown by the schematic in Fig. 4a (ref. 27 ). Using a vdW dielectric has been proven to be effective in reducing the hysteresis of 2D semiconductor FETs 12,28 . In Fig. 3e, we already demonstrated the ultrasmall hysteresis in the double-sweep transfer curves using a fast sweeping rate (t sweep = 0.12 ks). To fully activate the trap states, we use an ultraslow sweep rate (t sweep = 6.67 ks) to test the hysteresis for MoS 2 /Sb 2 O 3 and MoS 2 /SiO 2 FETs 29 . At a low temperature (40 K), we observe a negligible hysteresis for MoS 2 /Sb 2 O 3 FETs and a considerable hysteresis window for MoS 2 /SiO 2 FETs. The variation in onset voltage ΔV on , which is usually used to quantify the FET hysteresis, reduces over an order of magnitude from 4.2 V for MoS 2 /SiO 2 to 0.5 V for MoS 2 / Sb 2 O 3 FET at 40 K. We also investigated the dependence of ΔV on on temperature ( Fig. 4c and Supplementary Fig. 15d). With any sweeping rate, the temperature variation from 40 to 300 K leads to a slight increase in hysteresis for the MoS 2 /Sb 2 O 3 FET. Such a small dependence implies a low density of effective trap states within our Sb 2 O 3 dielectric as the hysteresis is generally induced by the charge carriers trapped in the trap states during the FET on/off switching (Fig. 4). In contrast, the hysteresis of monolayer MoS 2 /SiO 2 FET sensitively depends on the temperature (Supplementary Fig. 14). The double-sweep transfer curves exhibit a large hysteresis window at 300 K and its ΔV on reaches 12 V. This observation accordingly points to a higher density of trap states on the SiO 2 substrate, for which more charge carriers can be thermally activated and transferred into the trap states at a higher temperature 30 .
To confirm the source of the trap states, we also investigate the thickness-dependent hysteresis of MoS 2 FETs. For all the MoS 2 /Sb 2 O 3 FETs at various temperatures, the transfer characteristic curves exhibit a small hysteresis window and ΔV on negligibly depends on the MoS 2 thickness (Fig. 4d). Such an observation implies that the trap states are not caused by the bulk defects in MoS 2 considering that the density of such trap states is, in principle, dependent on the thickness. For MoS 2 /SiO 2 FETs, as anticipated, the hysteresis demonstrates no obvious dependence on MoS 2 thickness but considerably increases with temperature due to the thermal activation of trap states at higher temperatures. As our Sb 2 O 3 substrates are exposed to air for a long time (a few days), air adsorption onto our Sb 2 O 3 film may introduce some trap states and lead to hysteresis 24 . However, our experimental results rule out this possibility and our theoretical calculations reveal that the typical gas can hardly adsorb onto Sb 2 O 3 molecules owing to its inert surface (Supplementary Table 4).  To estimate the density of the trap states on Sb 2 O 3 and SiO 2 substrates, we investigate the variation in threshold voltage ΔV th in the double-sweep transfer characteristic curves, which correlates to the charge of the density of trap states, ΔQ, according to ΔV th = ΔQ × C (ref. 27 ), where C and ΔQ stand for the gate capacitance and trapped charges, respectively. The values of ΔV th for all our MoS 2 /Sb 2 O 3 devices cannot be precisely extracted by linearly extrapolating the transfer curves due to the almost negligible hysteresis window ( Fig.  3e and Supplementary Fig. 10c). We estimate ΔV th for the monolayer MoS 2 /Sb 2 O 3 device to be lower than 0.2 V without any observable dependence on temperature, thus corresponding to a density of trap states of 1.3 × 10 10 cm −2 . In contrast, the density of trap states on SiO 2 demonstrates ΔV th = 4 V at 40 K. It increases to 6 V at 300 K under thermal activation, corresponding to a density of trap states of 2.9 × 10 11 cm −2 , which matches well with the reported value extracted from MoTe 2 FET 27 . We, thus, confirm a reduction in trap states by more than one order of magnitude for our Sb 2 O 3 substrate with respect to SiO 2 .

Sb 2 o 3 film as direct gate dielectric
Direct integration of high-quality dielectrics via the well-developed atomic layer deposition process on 2D materials has been shown to be cumbersome 30,31 . Thermal evaporation deposition of conventional dielectrics usually results in poor dielectric properties. Towards scalable device integration, we demonstrate that our Sb 2 O 3 film deposited via STED is dense and exhibits high-performance dielectric properties, probably due to its particular molecular structure.
As for the integrated devices, MoS 2 FETs using only an Sb 2 O 3 thin film as the gate dielectric exhibit intriguing device performance. Top-gated MoS 2 FETs using an Sb 2 O 3 film of various thicknesses t as the dielectric is schematically demonstrated in Fig. 5a. Figure 5b shows an image of the device with t = 20 nm. The conductivity of channel MoS 2 can be effectively controlled by the top-gate voltage (V tg ) and such an FET exhibits a similarly high on/off ratio (~10 8 ) owing to the low gate current leakage of ~10 −14 A (Fig. 5c,d). Such a low leakage current is attributed to the dense Sb 2 O 3 film deposited on MoS 2 , which is free of pinholes ( Supplementary Fig. 18 shows the cross-section transmission electron microscopy (TEM) image of the device). The hysteresis of this top-gated FET was also investigated using the pulsed voltage measurement mode with various pulse time widths at different temperatures 32,33 ( Supplementary  Fig. 19). Although some chemical residues inevitably remain at the interfaces between the MoS 2 , Sb 2 O 3 and gate metal during the device fabrication process, the FET still exhibits extremely small hysteresis ( Supplementary Fig. 19).
We also fabricated MoS 2 FET with a thinner Sb 2 O 3 film (10 nm) as the top gate (Fig. 5c), corresponding to an equivalent oxide thickness (EOT) of 3.3 nm, which still exhibits an ultralow gate leakage current, large on/off ratio and smaller supply voltage. The device performance further confirms the excellent dielectric properties of the Sb 2 O 3 film even though a further reduction in the thickness of the Sb 2 O 3 film to 5 nm results in higher gate leakage (Fig. 5c). The top gate only controls its underlying MoS 2 channel (Fig. 5b), whereas we can operate the whole channel in combination with the back gate (Fig. 5e). For given back-gate voltages (V bg ), we observe that I on increases with larger V bg because a larger V bg may gradually switch on the whole channel and increase the conductivity of the whole channel. At the same time, it needs a more negative V tg to switch off the channel underlying the top-gate electrode. The transfer curves of double-gated MoS 2 demonstrate similar behaviours as the same double-gate FET using hBN as the dielectric 34 and the subthreshold slope at any given back-gate voltage reaches a low value of 68 mV dec −1 , approaching the thermionic limit of the subthreshold slope (60 mV dec −1 ) at room temperature. Sb 2 O 3 can also be deposited on few-layer graphene as the back-gate electrode, enabling the integration of FET composed of all vdW materials . The subthreshold slope of such FETs reached 64 mV dec -1 for 10 nm Sb 2 O 3 film as the dielectric (Supplementary Fig. 21) and the supply voltage can be reduced to 0.8 V with a high on/off ratio of 10 7 , suggesting the possibility to fabricate low-power FETs. Moving towards a thinner dielectric, we use 5 nm Sb 2 O 3 (EOT, 1.6 nm) to fabricate both top-gate (Fig. 5c) and back-gate MoS 2 FETs (Supplementary Fig. 22). The supply voltage is reduced to below 0.5 V although the gate leakage current starts to increase and the on/off ratio of such FETs reduces to 10 4 , probably due to the direct tunnelling of current through the Sb 2 O 3 film. This result is in good agreement with our leakage current measurement (Supplementary Fig. 7b). Scalable MoS 2 FETs rely on the scalable fabrication and integration of MoS 2 . We used chemical vapour deposition to synthesize MoS 2 flakes and then transfer them onto the Sb 2 O 3 substrate for fabricating a top-gated FET array ( Supplementary Fig. 23). Such FETs are found to exhibit similar device performance as exfoliated MoS 2 flakes.
Our approach substantially relies on the particular structure of Sb 2 O 3 and its excellent insulating properties. Our results may merely open up the opportunities for the scalable fabrication of vdW dielectrics via compatible processes with respect to other dielectrics 18,31,35,36 . Evidently, such an approach of compatible fabrication is not limited to Sb 2 O 3 , but applicable to other inorganic molecular crystals. In this regard, it would be of great interest to explore other inorganic molecular crystals (for instance, with a large bandgap and higher dielectric constants) so that we can probably realize the fabrication of 2D FETs with a gate dielectric of sub-1-nm EOT. As to our Sb 2 O 3 film, the fabrication process can still be optimized via the modulation of substrate temperature and deposition rate in more advanced deposition systems. For instance, deposition at a low temperature may lead to the formation of an amorphous Sb 2 O 3 film, which may further modulate the film morphology and dielectric properties. As a representative example, monolayer MoS 2 /Sb 2 O 3 FETs demonstrated large mobility enhancement. However, the fabrication processes of our MoS 2 FET inevitably left some contaminants on the MoS 2 surface, limiting the low-temperature mobility. More elaborate fabrication processes enabling cleaner device fabrication may further increase the mobility and reduce the hysteresis of such FETs. Based on the excellent device performance clearly presented in this work (Supplementary Table 5 provides a comparison with other dielectrics) and its advantages in device integration, such a vdW dielectric can improve the performance of devices based on other 2D materials 2 and can be potentially used in other device architectures [37][38][39] .

Conclusions
We have shown that a vdW dielectric layer of inorganic molecular crystals of Sb 2 O 3 can be fabricated using thermal evaporation deposition. The approach offers precise deposition control, wafer-scale fabrication and simple integration with other 2D materials. Also, 2D MoS 2 FETs supported by an Sb 2 O 3 substrate exhibit improved device performance, including enhanced electron mobility and reduced hysteresis, compared with devices made with SiO 2 . MoS 2 FETs gated by ultrathin layers of Sb 2 O 3 as the dielectric gate also exhibit high performance, including a supply voltage of 0.8 V, on/off ratio of 10 8 and subthreshold slope of 64 mV dec −1 . The scalable fabrication of vdW dielectrics via techniques that are compatible with CMOS processes is a prerequisite for the scaling up of high-performance 2D devices. Our approach to fabricate vdW dielectrics using inorganic molecular crystals should be more CMOS compatible than the fabrication method required with other vdW dielectrics (such as hBN), and can provide electronic devices with superior performance to devices created with non-vdW dielectrics. Our approach could, thus, lead to the scalable fabrication of 2D devices that have their intrinsic properties preserved.

Methods
Thermal evaporation deposition. The thermal evaporation deposition of Sb 2 O 3 is carried out via a standard deposition system (Nexdep, Angstrom Engineering) in a high vacuum (10 −6 torr). The deposition rate is precisely controlled by an in situ crystal quartz monitor. We use a low deposition rate of 0.06 Å s −1 for the entire fabrication process of the Sb 2 O 3 film to maintain the flatness of the Sb 2 O 3 film.

AFM.
The morphology characterization and thickness calibration of the Sb 2 O 3 film as well as thickness measurement of MoS 2 are carried out with an AFM instrument (Bruker Dimension FastScan).
Absorption spectroscopy. The absorption spectrum of the Sb 2 O 3 film deposited on a glass substrate is obtained via a Shimadzu SolidSpec-3700i ultraviolet-visiblenear-infrared spectrophotometer.
Optical spectroscopy. Raman spectra and photoluminescence are obtained in a confocal Raman system (WITec alpha300) with an excitation laser of 532 nm at 2 mW.
Computation methods. First-principles calculations were performed using the Vienna ab initio simulation package. The computation details for the density of states for Sb 2 O 3 , vacancy formation energy within the Sb 2 O 3 molecule and gas adsorption are described in the Supplementary Information.

MoS 2 FET fabrication and test.
Two-dimensional MoS 2 is prepared via mechanical exfoliation using scotch tape and polydimethylsiloxane (PDMS). The SiO 2 substrates are firstly well cleaned with argon plasma (Diener Pico). The fabricated Sb 2 O 3 substrates are normally exposed in air before the exfoliation of MoS 2 . After the confirmation of MoS 2 via optical measurement, (polymethyl methacrylate) PMMA is spin coated onto the substrates with MoS 2 . Afterwards, the electrodes are defined via standard electron-beam lithography, followed by the deposition of 10 nm In and 90 nm Au evaporated via the electron beam. After metal lift-off in acetone, the devices are transferred into a chamber equipped with a semiconductor analyser (Keithley 4200). We pump the chamber and keep it in a high vacuum (10 −6 torr) for 3 h to eliminate the gas adsorption on device surfaces before the device test. Afterwards, the devices tests are carried out at an increasing temperature from 15 to 300 K.

Growth of MoS 2 and transfer.
We use a tube furnace system for chemical vapour deposition to grow the MoS 2 flakes. MoO 2 mixed with NaCl is used as the Mo precursor. The SiO 2 /Si substrate is covered on the MoO 2 powder for the nucleation and growth of MoS 2 , which is heated up to 670 °C together with the Mo precursor. Then, sulfur powder (as the sulfur precursor) loaded in a crucible is moved to a position with a temperature of 300 °C. Argon gas (30 s.c.c.m.) is used as the carrier gas to transfer the evaporated sulfur to the substrate. The reaction lasts for 3 min and the furnace is cooled down naturally to room temperature. The obtained MoS 2 flakes are then transferred using a PMMA-assisted method onto our Sb 2 O 3 substrate, and fabricated into a device using a similar process as the exfoliated MoS 2 flakes.
FET mobility extraction. The FET mobility is extracted from the transfer curve via the formula where L and W are the width and length of the channel material, respectively; C is the gate capacitance, V ds and I ds are the biased voltage and current between the source and drain, respectively; and V gs is the gate voltage. For mobility extraction from the four-terminal measurement, V ds is the voltage difference between the two terminals in the middle. The capacitance of the SiO 2 substrate is estimated to be 1.15 × 10 −8 F cm −2 for a dielectric constant of 3.5 and thickness of 300 nm. The capacitance of our Sb 2 O 3 substrate deposited on SiO 2 /Si is calculated via the formula where C is the capacitance of the stacking layers of Sb 2 O 3 /SiO 2 and C 1 and C 2 are the capacitances with only SiO 2 and Sb 2 O 3 layer, respectively. We estimate the capacitance of Sb 2 O 3 /SiO 2 to be 1.15 × 10 −8 F cm −2 for a dielectric constant of 11.5 and thickness of 40 nm.
TEM sample preparation and characterization. The deposited Sb 2 O 3 film is transferred onto the TEM grid with PMMA as the carrier film. The cross-section lamella for scanning transmission electron microscopy is prepared using a standard lift-out method in a dual-beam focused ion beam instrument (Helios NanoLab TM 650, FEI). TEM and diffraction patterns are acquired via FEI Tecnai G2 F30 operated at 300 kV and FEI Titan ChemiSTEM G2 operated at 200 kV.

Data availability
The data that support the plots within this paper and other finding of this study are available from the corresponding author upon reasonable request.