Scaling Behavior of Sub-100 nm InAlN/GaN HEMTs on Silicon for RF Applications

Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 10, an average subthreshold swing (SS) of 72 mV/dec, a low draininduced barrier lowing (DIBL) of 88 mV, an off-state threeterminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figureof-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Background nAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions due to the low cost and the scaling capability of Si substrate [1][2][3][4]. L. Li et al. demonstrated a InAlN/GaN HEMT on Si with a gate length (L g ) of 55 nm and a source-drain spacing (L sd ) of 175 nm [5]using n ++ -GaN regrowth source/drain contacts. The device presents a maximum drain current (I d, max ) of 2.8 A/mm, a peak extrinsic transconductance (g m ) of 0.66 S/mm, and a current/power gain cutoff frequency (f T /f max ) of 250/204 GHz. H. Xie et al. reported that a record f T of 310 GHz was achieved on a InAlN/GaN HEMT on Si with a 40-nm gate length [6]. P. Cui et al. demonstrated an 80-nm-gate-length InAlN/GaN HEMT on Si with a record high on/off current (I on /I off ) ratio of 1.58 × 10 6 , a steep subthreshold swing (SS) of 65 mV/dec, and a f T of 200 GHz, resulting in a record high f T × L g = 16 GHz•µm [7]. on Si with a f T of 210 GHz and a three-terminal off-state breakdown voltage (BV ds ) of 46 V, leading to a record high Johnson's figure-of-merit (JFOM = f T × BV ds ) of 8.8 THz•V [9].
However, to the best of our knowledge, the highest f T /f max of 454/444 GHz and 348/340 GHz were achieved on 20-nm-gatelength AlN/GaN HEMT [10] and 27-nm-gate-length InAlN/GaN HEMTs on SiC [11], respectively. Although excellent performances have been demonstrated, InAlN/GaN HEMTs on Si still presents much room to be improved compared with GaN HEMTs on SiC substrate. Hence, exploring the possible limiting factors of InAlN/GaN HEMTs on Si is significant to further improve the device performance. In this paper, high-performance InAlN/GaN HEMTs on Si are fabricated and demonstrated. The extrinsic and intrinsic parameters of devices with different gate lengths are extracted and the scale behavior of InAlN/GaN HEMTs on Si is predicted. It presents that a f T /f max of 230/327 GHz can be achieved when L g scales down to 20 nm with the technology developed in the study, and an improved f T /f max of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMTs with regrowth ohmic contact technology and 30% decreased parasitic capacitance. This confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Figure 1(a)
shows the used lattice-matched In 0.17 Al 0.83 N/GaN heterostructure, which is grown on a Si substrate by metalorganic chemical vapor deposition (MOCVD). The epitaxial layer structure consists of a 2-nm GaN cap layer, an 8-nm In 0.17 Al 0.83 N barrier layer, a 1-nm AlN interlayer, a 15-nm GaN channel layer, a 4-nm In 0.12 Ga 0.88 N back-barrier layer, and a 2-μm undoped GaN buffer layer. The electron sheet concentration and electron mobility measured by Hall measurements were 2.28 × 10 13 cm -2 and 1205 cm 2 /V•s, respectively. Figure 1(b) shows the detailed device fabrication steps. The device fabrication started with mesa isolation using Cl 2 /CH 4 /He/Ar inductively coupled plasma etching. Then Ti/Al/Ni/Au stack was deposited and annealed at 850˚C for 40s in N 2 to form the alloyed ohmic contacts. The ohmic contact resistance is 0.3 Ω•mm. An oxygen plasma treatment was then Scaling behavior of sub-100 nm InAlN/GaN HEMTs on silicon for RF applications applied to form the oxide layer on top of the InAlN layer, which can effectively reduce the gate leakage current and improve RF erformance [12][13][14][15]. Finally, a Ni/Au T-shaped gate with a gate width (W g ) of 2 × 20 µm was fabricated by electron beam lithography. Figure 1(c) shows a plan-view scanning electron microscopy (SEM) image of the InAlN/GaN HEMT with a gate head length (L head ) of 400 nm and a source-drain spacing (L sd ) of 600 nm. Figure 1(d) shows a SEM image of T-shaped gate structure depicting a gate footprint of 50 nm.

Results and discussion
A. DC performance The DC current-voltage (I-V) measurements are carried out by using an Agilent B1500A semiconductor parameter analyzer. Figure 2(a) shows the output characteristic of the InAlN/GaN HEMT with a 50-nm gate length. The device on-resistance (R on ) extracted at gate-source (V gs ) of 0 V and drain-source voltage (V ds ) between 0 and 0.5 V is 1.33 Ω·mm. The gate-to-channel distance t bar (including a 2-nm GaN, an 8-nm InAlN, and a 1nm AlN) is 11 nm. Since L g is 50 nm, the device presents an aspect ratio (L g /t bar ) of 4.5. Due to the low L g /t bar , the shortchannel effects (SCEs) start to appear when V ds is larger than 5 V and V gs is between -4 to -1 V. At V gs = 1 V, drain current (I d ) in saturation region presents a decrease with increased V ds , an indication of the thermal effect.  shows the transfer characteristic with the extracted extrinsic transconductance (g m ) of the InAlN/GaN HEMT with a 50-nm gate length at V ds = 10 V. The maximum saturation drain current (I d, max ) is 2.01 A/mm at V gs = 1 V and V ds = 10 V. The g m perk (g m, peak ) is 493 mS/mm. To the best of our knowledge, the record high I d, max of 2.8 A/mm and g m,peak of 660 mS/mm were achieved on a 55-nm-gate-length InAlN/GaN HEMT on Si with regrowth technology and L sd of 175 nm [5]. The lower both I d and g m,peak in this study result from the regrowth-free technology and the larger source-drain spacing (L sd = 600 nm). Figure 3(a) shows the transfer and gate current (I g ) characteristics in semi-log scale of the InAlN/GaN HEMT with a 50-nm gate length at V ds = 5 V and 10 V, respectively. At V ds = 10 V, the device off-current (I off ) is 2.76 × 10 -7 A/mm and the I on /I off ratio is 7.28 × 10 6 , which are higher than the record reported values (I off of 7.12 × 10 -7 A/mm and I on /I off ratio of 1.58 × 10 6 ) achieved from the InAlN/GaN HEMT on Si [16]. An average subthreshold swing (SS) of 72 mV/dec over more than two orders of I d is extracted from the transfer curve. The draininduced barrier lowering (DIBL) of 88 mV/V is extracted at I d = 10 mA/mm between V ds = 10 V and V ds = 5 V, which is the lowest value among the reported GaN HEMTs on Si. The lowest DIBL value suggests a suppressed SCEs for the sub-100nm gate-length device. Figure 3(b) shows the off-state three-terminal breakdown characteristic of the 50-nm InAlN/GaN HEMT measured at V gs = -8 V. The device features a BV ds of 36 V at a drain leakage current of 1 mA/mm.

B. RF performance
The device RF performance is measured with a frequency range from 1 to 65 GHz. The network analyzer is calibrated using a two-port short/open/load/through method. On-wafer open and short structures is used to eliminate the effects of parasitic elements. Figure 4(a) shows the the current gain (|h 21 | 2 ), unilateral gain (U), and the maximum stable gain (MSG) as a function of frequency at V ds = 10 V, V gs = −3 V after deembedding. f T /f max of 140/215 GHz for the InAlN/GaN HEMT with a 50-nm gate length is obtained by extrapolation of |h 21 | 2 with a -20 dB/dec slope. An (f T × f max ) 1/2 of 173 GHz is obtained, which is the highest record values among the reported InAlN/GaN HEMTs on Si with regrowth-free ohmic contact technology. To the best of our knowledge, the highest (f T × f max ) 1/2 of 226 GHz (f T /f max = 250/204 GHz) was achieved on a 55-nm InAlN/GaN HEMT on Si with regrowth technology. Here for our device, the alloyed ohmic resistance (R C : 0.3 Ω•mm) is higher than the reported regrowth ohmic contact resistance (R C : 0.05 Ω•mm) [5]. This presents a high potential for the RF performance improvement by further decreasing the ohmic contact resistance. Due to f T /f max of 140/215 GHz, products of f T × L g and f max × L g of 7.0 and 10.75 GHz·µm are achieved, respectively. Although neither passivation nor field plate technology is used, the 140-GHz InAlN/GaN HEMT with an BV ds of 36 V presents a Johnson's figure-of-merit (JFOM = f T × BV ds ) of 5.04 THz·V. Figure 4(b) shows the measured f T and f max of the 50-nm InAlN/GaN HEMT as a function of V gs . Both f T and f max show a gradual decrease compared with their peak values, presenting a good device linearity.     The classical 16-element equivalent-circuit model is used for the InAlN/GaN HEMT, as shown in Figure 5 (a) [17,18]. Based on this model, the device extrinsic and intrinsic parameters are extracted in Table I [17][18][19]. The slight discrepancy between the simulated and measured S-parameter values is observed in Figure 5 (b), verifying the accuracy of the extracted extrinsic and intrinsic parameters. The f T and f max can be calculated using [17,20]

C. Equivalent circuit model
where Gm and G0 are the intrinsic transconductance and drainsource conductance, respectively; Cgs and Cgd are the gatesource and gate-drain parasitic capacitance, respectively; Rs, Rd, Rg, and Ri are the parasitic source access resistance, drain access resistance, gate electrode resistance, and input resistance, respectively. The calculated f T /f max = 145/218 GHz is very close to the value (f T /f max = 140/215 GHz) extracted by extrapolation of |h 21 | 2 with a -20 dB/dec slope, which confirms the excellent device RF performance. The high intrinsic transconductance/drain-source conductance (G m /G 0 ) ratio of 10.6 contributes to the high f max .

D. Scaling behavior
The InAlN/GaN HEMTs with L g between 50 nm and 350 nm are fabricated. Figure 6(a) shows the measured f T /f max of the InAlN/GaN HEMTs with different L g at V gs = -3 V and V ds = 10 V. The devices with L g of 50, 70, 100, 150, 250, and 350 nm present f T /f max of 140/215, 135/205, 120/170, 90/160, 60/136, 36/128 GHz, respectively. f T × L g and f max × L g are obtained in Figure 6(b). A f T × L g peak of 15 GHz•µm is achieved on the 250-nm-gate-length InAlN/GaN HEMT with a f T of 135 GHz. f max × L g presents a decrease from 44.8 GHz•µm (L g = 350 nm) to 10.75 GHz•µm (L g = 50 nm). The decrease of both f T × L g and f max × L g as L g scales down means that the effect of parasitic parameters is more pronounced, thus hindering the improvement of f T and f max . Due to the large head length of Tshaped gate (L head = 400 nm), the transistors features higher f max and f max × L g . To shed more light on the scaling behavior, the extrinsic and intrinsic parameters of these devices are further extracted using the equivalent circuit model discussed above. C gs can be separated to two parts: gate-source intrinsic capacitance (C gs,int ) and gate-source extrinsic capacitance (C gs, ext ). It means C gs = C gs,int + C gs,ext [21]. C gd is the same with C gs and can also be written as C gd = C gd,int + C gd,ext . Figure 7 shows the extracted C gs and C gd as a function of L g . Both C gs and C gd present a linear dependence upon L g . By linear fitting, the C gs,ext and C gd, ext are obtained from C gs and C gd at L g = 0 nm [21], as shown in Figure  7. Here C gs,ext of 93.05 fF/mm and C gd,ext of 97.65 fF/mm are determined, respectively.
The total delay (τ) of transistors can be written as [21] [22] Here τ is partitioned into three components: transit time (τ t ), parasitic charging delay (τ ext ), and parasitic resistance delay (τ par ). τ t is the transit time under the gate region. It is related to the gate length as well as the electron velocity (v e ) under the gate region, and can be calculated by [21,22] τ ext is parasitic charging delay through C gs,ext as well as C gd,ext , and can be written as [21] [22] ,, ext m Cgs ext Cgd ext G  + = .
(4) τ par is parasitic resistance delay mainly associated with R s as well as R d , and can be written as [21] (2) and (3). As L g decreases, τ shows a monotonous drop, which corresponds to the increased f T . With decreased L g , v e increases to a maximum value of 1.08 × 10 7 cm/s (at L g = 150 nm) and then drop to 0.80 × 10 7 cm/s (at L g = 50 nm). Figure 9 shows the extracted G m and G 0 as a function of L g . G 0 shows an increase with decreased L g . The dependence of G m and v e on L g present the same trend. Based on (3), because C gsi and C gdi linearly depends on L g , we conclude that the change of G m is attributed to v e difference. The same trend of G m and v e on L g is also observed in InAs HEMTs [23,24] and the reason is not clear. Here we attribute it to the effect of increased electric field on the electron velocity and suggests further work is needed. Figure 10 exhibits the calculated τ t , τ ext , and τ par using (3) to (5). τ ext and τ par is almost unchanged. Conversely, τ t decreases with decreased L g and dominates the total delay in all devices. This makes it possible to decrease delay and improve f T through downscaling of device gate length. However, for the device with L g below 100 nm, the effect of τ ext and τ par become nonnegligible. The ratios of (τ ext + τ par )/τ t are 39% and 40% for the InAlN/GaN HEMTs with L g of 70 and 50 nm, respectively. This means the parasitic capacitance and resistance significantly hampers further L g scaling benefits in RF performance of sub-100 nm InAlN/GaN HEMTs.  Therefore, downscaling and decreasing parasitic resistances as well as capacitances are very important for further improving device performance of InAlN/GaN HEMTs on Si. Figure 11 plots the calculated f T and f max based on the model and the extracted parameters (Blue-line in Figure 11), which shows a good agreement with the measured results. The model results present that f T /f max of 230/327 GHz can be achieved when L g scales down to 20 nm with the technology developed in the study. To decrease the parasitic resistance, the regrowth ohmic contact can be used. Here R s (0.30 Ω•mm), R d (0.32 Ω•mm), and G m (573 mS/mm) are changed to 0.10 Ω•mm, 0.08 Ω•mm, and 620 mS/mm [5]. Then new model results with regrowth technology are plotted (Green-line in Figure 11) and a f T /f max of 265/397 GHz is achieved on the device with a 20-nm gate length. Optimizing the detailed structure of T-shaped gate can decrease C gs and C gd . Hence when 30% decreasing of C gs and C gd is added into the model, new results (Red-line in Figure 11) are plotted and an improved f T /f max of 320/535 GHz on 20-nmgate-length InAlN/GaN HEMT is demonstrated. These values are comparable to the 27-nm InAlN/GaN HEMTs on SiC with f T /f max of 348/340 GHz, suggesting the possible of further improvement of InAlN/GaN HEMTs on Si.

Conclusions
In summary, high-performance 50-nm InAlN/GaN HEMT on Si with an I on /I off ratio of 7.28 × 10 6 , a SS of 72 mV/dec, a DIBL of 88 mV/V, a BV ds of 36, a f T /f max of 140/215 GHz, and a JFOM of 5.04 THz•V are demonstrated. The extrinsic and intrinsic parameters of transistors with different L g are extracted and the scaling behavior of InAlN/GaN HEMTs on Si is demonstrated. Based on extracted model, a f T /f max of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrowth ohmic contact technology and 30% decreased parasitic capacitance. This study confirmes the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.