Design of Low Power Architecture for Approximate Parallel Mid-Point Filter


 Approximate computing is a modern techniques for design of low power efficient arithmetic circuits for portable error resilient applications. In this work, we have proposed a Adaptive Parallel Mid-Point Filter (APMPF) architecture using proposed imprecise Max-Min Estimator (MME)targeting digital image processing. Parallel architecture for the MME can trade-off hardware at the expense of accuracy are proposed and used in the proposed APMPF. In APMPF, we use three level of sorting to estimate the mid-point of 3 x 3 window. Switching based trimmed filter is proposed for precise estimation of the selected window. Experimental Results interms of Area, Power and Delay with 90nm ASIC technology exposed that to the least, Proposed filters demonstrate 7% and 9% Area Delay Product (ADP) and Power Delay Product (PDP) reductions, respectively, compared to precise filter design.


INTRODUCTION
Digital images are often degraded by the noise resulting from image sensors or transmission of images. Hence, Image denoising is implemented to restore the noisy pixels with a likely value.To achieve the high visual performances, many algorithms were intended to increase the computational complexities and hardware requirements. These imparts the researchers to design an efficient hardware architectures attended to meet high visual performances.
Approximate computing is done better in error resilent applications for signal and image processing. Approximate compressors were proposed [1,2] and implemented in various multiplier designs for the image and signal processing applications. In ref [3] approximate subtractors proposed for various signal and image enhacement applications. Approaches in [4,5] various imprecise adders were intended for the low power circuits.
Approximate computing is an energy efficient approach to design low power architectures applicable for error tolerant applications. For the digital image processing applications, the visual quality degradation is less, eventhough the small error persist. In literature the various approaches were proposed for hardware implementation that use approximate computing. Two hybrid CMOS imprecise adders were designed [6] and implemented in gaussian filter for image processing application. Simple and efficient novel imprecise comparators were proposed and implemented in median filter for low power image processing application was proposed in Ref [7,8]. A novel sorting algorithm to design high speed area efficient median filter was proposed by Vasanth etal in Ref [9]. Novel mid-point filter was proposed in ref [10] using quantum cells in its buiding blocks for salt and pepper noise removal. 2-D median filter was proposed to focus on low cost design in ref [11]. approaches in [12][13][14][15] proposed to reduce hardware complexity in median filter architecture in imaging applications. In ref [16] gaussian filter was proposed for efficiently reduce the latency by the compact architecture and error introduced adder which play the role major role in the circuit. In Ref [17] , new architecture was designed to estimate the median for the 25 input values.
In this research work, we use the approximate computation in the Max-Min Estimator, for enhancing the performance of the Adaptive Parallel Mid-Point filter (APMPF). we propose the novel design of PMPF to perform at higher noise densities of Salt and Pepper Noise affected image and three designs Max-Min Estimator units (MME). The filter uses the first order neighbourhood of the processing pixel in design. The novelty of the proposed work is that the architecture, we employ the trim to corrupted pixels for processing, so as to reduces the major negative aspect of the mid-point filter in salt and pepper noise removal. This will equalize the error occurred due to the approximation in the MME for the error tolerant imaging applications.
The rest of the paper is organized as follows. A brief description about the related approaches on filter architectures is discussed in section-2. Detailed explanation of the proposed MME architectures and its building blocks are in section-3. The novel proposed APMPF has discussed in section-4. Performance evaluation and comprehensive comparison with earlier approaches is given in Section-5. Finally, the proposed work done is concluded in Section-6 2. RELATED WORKS Mid-point filter perform sorting on a set of inputs in a processing window to replace corrupted processing pixel with the mid-point value. Sorting algorithm employed in MF design fall into three main categories viz., systolic array, sorting network-based architectures and radix method or Threshold Decomposition Filter (TDF) [7]. Parallel operation can be performed with sorting based algorithms to design high speed MPF architectures. A brief comparison of various sorting architectures to estimate the Maximum and minimum for the filter is discussed in following sub sections.

Quantum midpoint Filter (2020)
Abdalla Essam Ali et al [10] proposed a novel approach for Quantum Mid point Filter (QMPF) with Quantum MME and other building blocks. The proposed Reversible logic based, three basic modules and four composite modules are implemented in the mid-point filter architecture. Filter

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter
architecture is based on sorting of rows and colomn values so as to estimate the required value to restore the corrupted. Three cell sorter consists of three MME to processs the three input,produces the Qmax and Qmin based on Quantum Circuit. It uses 13 MME units for a 3 X 3 processing window and has 6 units in the critical path.

Low Latency Filter(2017)
Vineet kumar et al [17] proposed a design of efficient architecture for 5x5 processing window. Row and colomn sorting based approach implemented in five input sorter. The architecture is modified to estimate the mid point is shown in fig. 2. A Five Cell Sorter (FCs) consists of twelve MME unit which includes 4-three cell sorter. Note from the LLF architecture it uses 84 MME units and 24 MME units in its critical path.
In this work we focus on to reduce the Power-Delay Product (PDP) and Area-Delay Product (ADP) with little sacrification of precise MME circuit which plays the essential role in the filter architecture.

PROPOSED MID -POINT FILTER
The Adaptive Parallel Mid-Point Filter is proposed, which process the neighbourhood to replace the processing pixel with the Mid-Point of the N-inputs. It consists of Impulse detector and Mid-Point Filter (MPF) which are the two basic blocks in the proposed structure, shown in figure 2. The various filters were discussed in literature, which conclude that the median filter works better in terms of visual enhancement of impulse noise corrupted image but requires more hardware for the implementation. Hence, it generates high power and area. To maintain the quality and reduce the hardware requirements, modified architecture is designed to estimate the mid-point which requires less hardwarea and performs well in high density corrupted images.A brief about the blocks are discussed in the following subsections.

Impulse Detector
Detect an impulse noise is an interesting task due to its variable high-low characteristics. Direct detection works well in the range of 1 to 2n-1, i.e. n-number of bits, but fails to detect in the range [0-2n]. The resultant of the adaptive detection fail to achieve the 100% accuracy more than 30% noise corrupted in the first order neighbourhood. Overcome this issues the higher order neighbourhood should be considered for impulse noise detection.

Proposed Filter
In this Proposed filter, Novel architecture for adaptive pixel selection of uncorrupted neighbourhoods and process to improve the performances in filtering. Here, We designed with three stages of sorting network based architecture to estimate the mid-point. The three stages are required for adaptive Max-Min selection to exclude the corrupted from processing. In the first stage all the n-inputs are processed by Max-Min Estimator. For n-8, four Max-Min Estimator (MME 1-4 )

Processing pixel Sliding Window
Mid-Point Filter Impulse Detector 1 0

8[A 8 -A 5 & A 3 -A 0 ]
8 Output produces the n/2 maximum and n/2 minimum. Similarly, the second stage (MME 5-7 ) produces n/4 maximum and n/4 minimum. Finally, The third stage (MME 8-10 ) produces the overall maximum and overall minimum from the n-input. The Select Signal for the PMPF is explaind as the algorithm below. Algorithm Steps: 1. initialize the count=0, input[n]=0. 2. check for the uncorrupted from neighbourhood pixels using NDU.

Mid-Point Computation Unit
The Mid-Point Computation Unit (MCU) Consists of Ripple Carry Adder (RCA) and shifter. At first, the shifter plays the right shift operation of the given two input(OMx and OMn) then the RCA produce the result that Mid Point of the given n-input. The block diagram for the Mid-Point Computation Unit is shown in figure 5.

RESULTS AND DISCUSSIONS
In this Section, the performance of the proposed filters are discussed in terms of circuit metrices. The proposed architectures Circuit metric and visual quality results for the proposed designs are compared with other state-of-the art designs and the performances for the same is analysed to verify its functional ability. For the circuit metric analysis, Power, area and delay are evaluated. The circuit metrics are synthesized by the Cadence Encounter tool in 90nm ASIC technology. All the designs including state of the art filters are designed using verilog HDL. The circuit metrics comparison table is shown in table-1. It clearly shows that the proposed PMPF reveals high efficiency than the other designs. Note from table 1, the power dissipation of the proposed filter is low compared with the other state-of the art designs. This is due to the low logical depth of the filter architecture.Hardware testing for the midpoint filter using Xilinx system generator was used.
The APMPFs performance and state-of the art designs, interms area, delay, power, PDP and ADP are shown in Tables 1. Note from Table 1, that PF-MME_A1, PF-MME_A2, PF-MME_A3 is 16%, 11 & 10% power reduction compare to the PF-MME_P1 design. Also note the power dissipation of PF-MME_A1 is significantly low compared to other PF designs. QPMF-MME_A1 and LLMF-MME_A1 is best in its respective MME designs, Circuit level performances are high when compared to the PF Designs.Conversly the average error of increases compare to other proposed methods.
Implementations of the proposed filters are carried out with verilog HDLusing Xilinx ISE 14.2 compiler tool and spartan 6 (XC6XLX45-CSG324). 6. RESULTS AND DISCUSSIONS This paper has presented a low power mid point filter architecture is implemented in image denoising application. Stage-2 Stage-3 Parallel implementations exposed reduce the physical properties and detection based approach precise the results with high accuracy. Also this paper presents three approximate max-min estimators plays key role for low power architectures. Different architectures are being analyzed its functional efficacy for the size of nine input with same size of state -of-art designs. The proposed filters shows better result in circuit metrices compared to QPMF and LLMF designs.