Vertical MoS2 transistors with sub-1-nm gate lengths

Ultra-scaled transistors are of interest in the development of next-generation electronic devices1–3. Although atomically thin molybdenum disulfide (MoS2) transistors have been reported4, the fabrication of devices with gate lengths below 1 nm has been challenging5. Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 105 and subthreshold swing values down to 117 mV dec–1. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore’s law of the scaling down of transistors for next-generation electronics. Ultra-scaled transistors based on two-dimensional MoS2 with physical gate lengths of 0.34 nm are reported, which show relatively good electrical characteristics and can be switched off.

Ultra-scaled transistors are of interest in the development of next-generation electronic devices [1][2][3] . Although atomically thin molybdenum disulfide (MoS 2 ) transistors have been reported 4 , the fabrication of devices with gate lengths below 1 nm has been challenging 5 . Here we demonstrate side-wall MoS 2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS 2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 10 5 and subthreshold swing values down to 117 mV dec -1 . Simulation results indicate that the MoS 2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore's law of the scaling down of transistors for next-generation electronics.
Since the first integrated circuit was built in the 1960s, silicon (Si) transistors have shrunk, following the guide of Moore's law, so that more devices can be built on one chip 6 . Si transistors are now approaching the scaling limit when the gate lengths (L g ) scale down to below 5 nm (ref. 7 ). Theoretical analysis indicates that short channel effects (SCEs), including direct source-to-drain tunnelling currents and the drain-induced barrier lowering (DIBL) effect, can influence the scaling down procedure 8 . The L g of state-of-art Si transistor is 3 nm based on V-shaped grooves wet etching technology (ref. 9 ). It is very important to explore new materials with further L g scaling down potential.
In recent years, two-dimensional materials, covering a wide range of electrical conductivity from semi-metal, semiconductor to insulator, have attracted great attention for next-generation electronic devices 4,10,11 . Graphene, as a semi-metal material, shows high intrinsic electrical conductivity, and can be used as electrodes [12][13][14] . MoS 2 , as a representative for two-dimensional (2D) transition metal dichalcogenides (TMDCs), has a larger bandgap (2.0 eV for monolayer) than Si (1.12 eV) 4 . Also, its native n-doped behaviour, larger electron effective mass 15 and lower dielectric constant 16,17 lead to superior resistance to SCEs 18 . Therefore, MoS 2 is expected to be an ideal candidate to replace Si as the channel material in future transistors 3,19 .
Nowadays, for 2D material-based transistors, there are three typical device structures, as shown in Fig. 1a-c. Global back-gated transistors are widely used, because of the simple fabrication process 20 , but the relatively large effective oxide thickness (EOT) restrains the performance improvement. Another device structure is the local(top)-gated transistor. The EOT can be scaled down to sub-1 nm through atomic layer deposition (ALD) of oxide with high dielectric constant (k). Therefore, subthreshold swing (SS) can be greatly reduced. However, whether for a global gate or a local gate, the L g is typically determined by the resolution of lithography. Even using electron-beam lithography (EBL) technology, the L g can hardly be scaled down below 5 nm (ref. 21 ). In 2016, Desai et al. promoted a prototype of a junction-less 2D MoS 2 transistor using metallic single-wall carbon nanotube (SWCNT) as the gate electrode that demonstrated 1 nm L g (ref. 5 ). Among the three typical transistor structures, it is hard to further scale down L g below 1 nm. To date, it is very important to explore 2D TMDC transistors with gate length approaching the ultimate scaling limits.
In this work, we demonstrate side-wall 2D transistors gated by the edge of graphene that only have sub-1 nm gate length controlling the atomic MoS 2 channel (Fig. 1d). Large-area chemical vapour deposition (CVD) graphene and MoS 2 are used for wafer-scale production. The additional aluminium (Al) layer screens the vertical electrical field from the upper surface of graphene, so that the effective gate electrical field comes from the edge of graphene, which can only influence part of the vertical MoS 2 channel. The CVD graphene films have high electrical conductivity that can minimize the voltage drop along the gate layer. The 0.34 nm gate length side-wall transistors show good switching characteristics, with the On/Off ratio up to 1.02 × 10 5 . Sentaurus technology computer-aided design (TCAD) simulation results show that 2D planar characteristics of graphene provide the ability for gate control, which can deplete the vertical MoS 2 side-wall channel that align to the graphene plane. This work promotes a wafer-scale production method for scaling L g down below 1 nm. More importantly, it provides a great insight into the ultimate scaling, which can be regarded as the smallest gate-length transistor to date based to the best of our knowledge (Fig. 1e).

Fabrication and characterization
To fabricate the 0.34 nm gate-length side-wall transistor, a monolayer CVD graphene film was first wet-transferred to a highly p-doped

Article
Si/295 nm SiO 2 substrate followed by patterning graphene as the gate electrode (Fig. 2a). After that, EBL was performed and a 25 nm Al layer was deposited by electron-beam evaporation (Fig. 2b). To verify the electrical conductivity, the as-fabricated graphene transistor with Al contact is measured (Extended Data Fig. 1). The samples were naturally oxidized in the air for more than 3 days to form an approximately 5 nm dense oxidization layer (AlO x ) around Al, including the formation of AlO x at the Al-graphene interfaces (Fig. 2c). The high-quality and dense AlO x layer at the Al-graphene interfaces are also confirmed (Extended Data Fig. 2). The Al layer also serves as the self-aligned mask for further graphene and SiO 2 inductively coupled plasma etching. Extra approximately 20 nm SiO 2 was etched to form the side-wall structure (Fig. 2d) and 14 nm high-k HfO 2 as the gate dielectric was grown by means of ALD (Fig. 2e). The monolayer CVD MoS 2 film was then wet-transferred and patterned on the substrate. The Ti/Pd (2 nm/35 nm) as source and drain contacts were made on the MoS 2 to complete the device (Fig. 2f). The final device has five electrical terminals named source (S), drain (D), the Al screening layer (Al), 0.34 nm graphene edge gate (G) and the fixed back-gated Si (B). By applying a negative voltage to the edge of the graphene gate to locally deplete the vertical MoS 2 channel, the transistor can be completely turned off. The idealized device structure is shown in Fig. 2g. The more detailed fabrication process can be seen in the Methods section.
To confirm the device structure, a representative sample after fabrication was characterized (Fig. 2h, i). For the false-coloured scanning electron microscopy (SEM) image, the purple region contains a monolayer graphene/AlO x /Al/AlO x /HfO 2 stack. The yellow and blue regions represent the MoS 2 channel and Ti/Pd metal contacts. The cross-section transmission electron microscopy (TEM) image shows the profile of the device core region; the layered structure of a vertical MoS 2 channel gated by the edge of graphene can be recognized. The topography MoS 2 film/HfO 2 stack was smooth. The whole MoS 2 channel length is designed to be at most 1 μm (approximately 500 nm in the device of Fig. 2i) by considering the lift-off process. The spatial distribution of aluminium, hafnium, carbon, molybdenum, sulfur and oxygen was observed in the energy dispersive spectrometer (EDS) mapping of the core region ( Fig. 2j and Extended Data Fig. 3), thus confirming the location of the monolayer graphene, HfO 2 , Al, AlO x and monolayer MoS 2 in this device. In the fabrication flow, the CVD graphene and MoS 2 films were applied as gate and channel materials, which realizes wafer-scale production (Fig. 2k).

Electrical measurement
For the proposed side-wall gated transistor, there are three terminals that can modulate the carrier density of a MoS 2 channel: (1) the graphene layer terminal; (2) the Al screening layer terminal; and (3) the back-gated Si terminal. In the experiment, the graphene acts as the unique gate, while the back-gated Si terminal is fixed at 50 V and the Al layer is fixed at 0 V. The Al layer screens the vertical electric field from the upper surface of graphene gate, so that only the electrical field from the edge of graphene can influence the vertical MoS 2 channel, realizing a 0.34 nm physical gate length, as shown in Fig. 1d (Fig. 3c). By varying V BS from −30 V to 50 V, which can affect the extension of MoS 2 region, the On-state current increases from 4.1 × 10 −9 A to 3.4 × 10 −7 A at V DS = 1 V (Fig. 3c). Non-ideal On-state current (3.4 × 10 −7 A) at V DS = 1 V and V BS = 50 V also proves the ultra-thin gate length owing to the present of an ungated region in the MoS 2 channel. In addition, the transfer curves slightly left shift under larger V BS because the V Gr has to be more negative to deplete the vertical MoS 2 channel owing to the ultra-thin 0.34 nm gate length. The I DS -V BS transfer characteristics with different V Al and V Gr at V DS = 1 V can verify the modulation ability of the side wall ( Fig. 3d and Extended Data Fig. 5). The screening function of the Al layer is further verified by tuning both the Al layer and the graphene layer from 0 V to 3 V; the On-state current effectively increases from 3.8 × 10 −8 A to 6.9 × 10 −7 A. In the transfer characteristics (Fig. 3a, c, d), the leakage current from the monolayer graphene side-wall gate (I Gr ), the Al screening layer (I Al ) and the highly p-doped Si substrate (I BS ) are shown, close to the noise level (less than 10 −11 A). The Off-state current of our 0.34 nm gate-length side-wall transistors are also constrained by the leakage current level, which is 3.7 × 10 −12 A in the device of Fig. 3a-d.
Considering the 4 μm channel width, the Off-state current density is less than 10 −12 A μm -1 , meeting the requirement of 10 −11 A μm -1 for 7 nm node low stand-by power transistors 22 . The discussed electrical characteristics above are from one typical device. The detailed electrical characteristic that demonstrates the tunability of the Al layer can be seen in Extended Data Fig. 6. To prove the reproducibility, another 49 devices were measured, including 28 devices with 1 μm channel length (L ch ) and 21 devices with 0.5 μm L ch , see details in Extended Data Fig. 7. The I DS -V Gr transfer curves from 10 representative devices with L ch = 1 μm at V DS = 1 V, V BS = 50 V and V Al = 0 V (Fig. 3e) show the uniformity of these 0.34 nm gate-length side-wall transistors. The distribution of On/Off ratio and SS value are collected (Fig. 3f), with the maximum On/Off ratio of 1.02 × 10 5 at V DS = 1 V and the minimum SS value of 117 mV dec -1 . Among the 50 measured devices, the maximum drive current density is 0.545 μA μm -1 at V DS = 1 V and V GS = 2.4 V (device 40 in Extended Data Fig. 7). The On-state current can be further improved by decreasing the whole MoS 2 channel length. Details are discussed in the following TCAD simulation section.

TCAD simulation
To understand the electrical behaviours and the underline device physics, Sentaurus TCAD was performed (Fig. 4a). The detailed parameters about the graphene, MoS 2 and dielectric are shown in Extended Data Tables 1 and 2. The lower plane of the extended lateral MoS 2 channel is 10 nm below the graphene gate plane in the simulation. The simulated I DS -V GS curves have similar trends with the experimental curves (Fig. 4b).
Both simulated and experimental curves show negative shifts as V DS becomes more positive, which indicates DIBL in small size transistors. The threshold voltage (V th ) in the simulation is slightly more negative than that in the experiment, which can be attributed to the idealized materials and interfaces.
The electric field contour plots in the On state (V DS = 3 V, V Gr = 2.4 V, V BS = 50 V, V Al = 0 V) and Off state (V DS = 3 V, V Gr = −1.5 V, V BS = 50 V, V Al = 0 V) are shown in Fig. 4c, d. In the Off state (Fig. 4d), the effective gated electric field comes from the edge of graphene, proving the 0.34 nm physical gate length. The electron density along the vertical MoS 2 channel in the On state (V Gr - V th = 0.26 V) and Off state (V Gr - V th = −0.47 V) under V DS = 50 mV, V BS = 50 V and V Al = 0 V are also shown in Fig. 4e, f, which has a region of low electron density and electric field. By defining the effective channel length (L eff ) as the channel region with electron density n < n threshold = 1.3 × 10 5 cm −2 , the approximately 4.54 nm side-wall MoS 2 channel close to the graphene plane can be regarded as the effective channel 19 (Extended Data Fig. 8)  Article the Off state can be further decreased by reducing the EOT of gate dielectric (14 nm HfO 2 , approximately 3.03 nm in this work). In the On state (Fig. 4e), the whole MoS 2 channel is at relatively high electron density. Therefore, the L eff can be regarded as L g , which is approaching the physical limit. The 0.34 nm gate-length side-wall transistors with scaling L ch of MoS 2 down from 500 nm to 4.54 nm are also simulated to boost the On-state performance (Extended Data Fig. 9). As L g reaches the physical limit, the semiconductor thickness is also required to be scaled down to the atomic level, to minimize the SCEs 23 . Therefore, MoS 2 layer dependent I DS -V Gr characteristic of the 0.34 nm gate-length side-wall transistor has also been simulated (Fig. 4g). With the thickness of the MoS 2 channel increasing from 0.65 nm (1 layer) to 20.8 nm (32 layers), although the On-state current improves for thicker MoS 2 , the channel cannot be completely depleted at the same V Gr , as both the On/Off ratios and SS values become undesirable. In addition, the monolayer MoS 2 channel is suitable for scalable production, which is promising for next-generation electronics.
Realization of small size transistors is a critical requirement. The iterative progress of gate length as a function of time is shown in Fig. 4f (refs. 9,18,[24][25][26][27][28][29][30][31][32][33][34][35][36][37][38]. From a 2D planar device to a three-dimensional fin field-effect transistor (FinFET) and further gate-all-around FET, the structure of Si transistors has gradually changed with better gate controllability. In the meantime, low-dimensional materials have come into sight, in 2016 SWCNT-gated MoS 2 transistors reached the smallest physical scale of 1 nm and the gate length has been levelling off for the past four years. This work promotes the side-wall structure and achieves monolayer material gating atomic channels. The side-wall structure utilizes the natural thickness direction, and the value of 0.34 nm achieved in this work is, to the best of our knowledge, the ultimate gate length to date. Wafer-level CVD monolayer materials can also be realized for future logic and circuit integration. This work sheds light on Moore's law going down below 1 nm.
2D materials provide us with opportunities to scale down electronic devices to the atomic level. TMDCs show good resistance to SCEs and On/Off max = 1.02 × 10 5 Typical ten devices graphene has high electrical conductivity and ultra-thin thickness. In this work, MoS 2 and the edge of graphene act as channel and gate, respectively, which enabled the achievement of 0.34 nm gate-length side-wall transistors. The side-wall structure effectively utilizes the natural ultrathin thickness of graphene and shows wafer-scale production. The On/Off ratio and SS value could reach 1.02 × 10 5 and 117 mV dec −1 , respectively. Scaling down EOT, decreasing channel length, improving the MoS 2 film quality and developing ideal contacts to MoS 2 are essential for further performance enhancement. Nevertheless, this work provides insight into the scaling down of transistors to approach the physical limit and sheds light on next-generation electronic devices below 1 nm.

Online content
Any methods, additional references, Nature Research reporting summaries, source data, extended data, supplementary information, acknowledgements, peer review information; details of author contributions and competing interests; and statements of data and code availability are available at https://doi.org/10.1038/s41586-021-04323-3.

CVD growth of graphene and MoS 2
For monolayer graphene growth on Cu, 3 × 3 cm 2 CVD monolayer graphene on Cu was bought from Hefei Vigon Material Technology Co., Ltd. The monolayer graphene coverage is higher than 99%. For monolayer MoS 2 growth on Si/SiO 2 , 2 × 2 cm 2 CVD monolayer MoS 2 on Si/SiO 2 was bought from Shenzhen 6Carbon Technology Co., Ltd. The monolayer MoS 2 coverage is higher than 99%.

Wet transfer of graphene and MoS 2
For graphene wet transfer, the poly(methyl methacrylate) (PMMA) layer with 400K molecular weight was first spin coated at 3,000 rpm for 60 s on graphene/Cu/graphene. After coating the PMMA layer on the top graphene, the graphene under Cu layer on the other side of the graphene was then etched by oxygen plasma treatment for 4 min, with O 2 at 300 sccm and 300 W power, by an Alpha Plasma AL18 system. Then 20 wt% dilute hydrochloric acid (HCl) was used to etch the supported Cu layer, serval drops of H 2 O 2 solution were added to facilitate the etching rates. After the Cu was completely etched, the graphene/PMMA was transferred into fresh deionized water six times, to remove the HCl residue. Then, the cleaned graphene/PMMA stack was transferred to the target sample and the excess deionized water was air-dried naturally for more than 12 h. Further annealing at 85 °C for 30 min enhanced the adhesion between the graphene and the substrate. The PMMA was removed by 30 min soaking with fresh acetone, with this being done at least twice.
For the MoS 2 wet transfer, the PMMA layer with 400K molecular weight was first spin coated at 3,000 rpm for 60 s on Si/SiO 2 /MoS 2 . After coating the PMMA layer, 3 wt% potassium hydroxide solution at 110 °C was used to lift off the MoS 2 /PMMA from the Si/SiO 2 substrate. Then, the MoS 2 /PMMA was transferred to fresh deionized water six times, to remove the potassium hydroxide residue. The cleaned MoS 2 /PMMA stack was transferred to the target sample and the excess deionized water was air-dried naturally for more than 12 h. Further annealing at 85 °C for 30 min enhanced the adhesion between the MoS 2 and the substrate. The PMMA was removed by soaking for 30 min with fresh acetone, with this being done at least twice.

Device fabrication
As a substrate we used a 2-inch highly p-doped silicon wafer, with 295 nm thermal oxidized SiO 2 . The bottom metal layer Ti/Pd (2 nm/30 nm), used as a mask for further EBL by a laser scribing system, was first prepared with AZ1500 as the photoresist. Then, a 3 × 3 cm 2 CVD monolayer graphene film was wet transferred to the central region of the 2-inch wafer, followed by a normal lithography process with AZ601 as the photoresist. After that, the excess monolayer graphene was etched by oxygen plasma treatment for 4 min, with O 2 at 300 sccm and 300 W power, by an Alpha Plasma AL18 system. After carrying out the EBL process with a 70K molecular weight PMMA layer as the photoresist, the 30 nm Al screening layer was then deposited on the graphene through a PVD75 e-beam evaporation system. Then, the samples were naturally oxidized in the atmosphere for more than three days. After carrying out another EBL process with a 70K molecular weight PMMA layer as the photoresist, the 30 nm palladium (Pd) layer used as a probing layer for graphene was then deposited through a PVD75 e-beam evaporation system. The Pd layer was partially overlapped with the Al layer. The Al layer and Pd layer served as a self-aligned mask for graphene and SiO 2 etching. An inductively coupled plasma-etching process with C 4 F 8 /O 2 treatment by a NE-550H system was carried out on the sample. The CVD monolayer graphene and its lowered 20 nm SiO 2 were etched to form the side-wall structure. The 14 nm HfO 2 was then grown by means of ALD at 200 °C by a Beneq TFS200-106 system. After carrying out the normal lithography process with AZ601 as a photoresist, 14 nm HfO 2 on the probe region of the Al layer and Pd layer was removed by a reactive ion etching process with Ar plasma. Then, a 2 × 2 cm 2 CVD monolayer MoS 2 film was wet transferred to the central region of the 2-inch wafer, followed by a normal lithography process with AZ601 as the photoresist. The excess monolayer MoS 2 was etched by oxygen plasma treatment for 10 min, with O 2 at 150 sccm and 150 W power, by an Alpha Plasma AL18 system. Finally, after carrying out an EBL process with a 70K molecular weight PMMA layer as a photoresist, the Ti/Pd (2 nm/35 nm) layer as source and drain contacts for the MoS 2 channel were deposited through a PVD75 e-beam evaporation system. Device characterization SEM imaging was performed by using a Quanta FEG 450 field emission scanning electron microscope. A 10 kV accelerating voltage was used to image the MoS 2 channel and contacted metal. TEM and EDS imaging were performed by Themis Z (Thermo Scientific) with a Super-X (Thermo Scientific) EDS system. The system operated at a 200 kV accelerating voltage. TEM was carried out with a 23.8 mrad convergence angle electron beam and the collection angle was set to 90-370 mrad. The sample first deposited was carbon by the electron beam and Pt by the ion beam to protect the surface from the damage of the ion beam. Electrical measurements were performed under vacuum (less than 10 −2 Pa) in a Lakeshore vacuum probe station with an Agilent Technologies B1500A Semiconductor Device Analyzer.

Data availability
The data that support the findings of this study are available from the corresponding author upon reasonable request.