Ultimate 0.34 nm Gate-length Side-Wall Transistors with Atomic Level Channel

Despite 55 years of efforts into short gate length transistors following the Moore’s law, the gate length below 1 nm has not been realized. Here, we demonstrated a side-wall monolayer MoS 2 transistors with ultimate 0.34 nm gate length using the edge of graphene as gate electrode. Moreover, large area of chemical vapor deposition graphene and MoS 2 are used for 2-inch wafer production. These ultrashort devices show excellent ON/OFF current ratio of 2 × 10 5 . Simulation results indicate that the MoS 2 side-wall effective channel length approaches 0.34 nm in the ON state. This graphene edge gate combined with MoS 2 vertical channel structure provides an ecient gate control ability and enables the physical gate length scaling down to atomic level, which shows great potential to build next generation electronics.


Main Manuscript
Since the rst integrated circuit built in 1960s, silicon (Si) transistors have shrunk following the guide of Moore's law so that more devices can be built on one chip 1 . Until now, Si transistors are approaching the scaling limit when the gate length (L g ) scales down to sub-5 nm 2 . Theoretical analysis indicates that short channel effects (SCEs), including direct source-to-drain tunneling currents (I SD-LEAK ) and draininduced barrier lowering (DIBL) effect, can in uence and even terminate the scaling down process 3 . It is theoretical predicted that the minimum L g for Si-based transistors is ~2.67 nm 4 . So, there is of great signi cance to explore new materials with further L g scaling down potential.
In recent years, two-dimensional materials, dispersing wide range of electrical conductivity from semimetal, semiconductor to insulator, have attracted great attention for next generation electronic devices [5][6][7] .
Nowadays, for 2D material-based transistors, there are three typical device structures, as shown in Fig. 1a-c. Global back gate 2D material-based transistors are most widely studied due to the simple fabrication process 17 . But the relatively large effective oxide thickness (EOT) restrains the performance improvement. Another is the top gate 2D material-based transistors (6). EOT can be greatly scaling down to sub-1 nm through atomic layer depositing (ALD) high-k dielectric material. Therefore, subthreshold swing (SS) can be greatly reduced. However, whether for global gate or local gate, the L g is typically determined by the resolution of lithography. Even using electron beam lithography (EBL), the L g can be hardly scaled down below 5 nm 18 . In 2016, Desai et. al promoted a prototype of junction-less 2D MoS 2 transistor using metallic single-wall carbon nanotube (SWCNT) as gate electrode, which demonstrates the L g down to 1 nm 19 . Among the three typical transistor structures, it is hard to further scaling down L g below 1 nm. To date, it is of great signi cance to explore the 2D TMDC transistors with the gate-length approaching the ultimate scaling limits.
In this work, we demonstrate a new concept of side-wall 2D transistors gated by the edge of graphene, which only have 0.34 nm L g controlling the atomic MoS 2 channel (Fig. 1d). Large area CVD graphene and MoS 2 are used for wafer-scale production. The additional metal layer screens the electrical eld from the upper surface of graphene, so that the electrical eld comes from the edge of graphene, which can in uence the vertical MoS 2 channel. The intrinsic CVD graphene has the high electrical conductivity, which can minimize the voltage drop along the gate layer. The 0.34 nm side-wall gated transistors show good switching characteristic with 2×10 5 ON/OFF current ratio. Sentaurus technology computer-aided design (TCAD) simulation results show that 2D planar characteristic of graphene gate provides e cient gate control ability, which can effectively deplete the MoS 2 side-wall channel close to the graphene plane.
Our work promoted a production method for scaling down L g beyond the resolution of lithography. And most importantly, it provides a great insight into the ultimate scaling, which can be regarded as the smallest node to date based on our best knowledge (Fig. 1e).

Fabrication and Characterization
To fabricate the 0.34 nm gate-length side-wall transistor, monolayer chemical vapor deposition (CVD) graphene with 3 cm×3 cm size was rst wet-transferred to a highly p-doped Si/ 300 nm SiO 2 substrate followed by patterning graphene as gate electrode. After that, EBL was performed and a 25 nm aluminum (Al) layer was deposited by electron-beam evaporation. Graphene transistors were rst measured to verify their electrical conductivity (Fig. S1). The samples were naturally oxidized in the air for more than 3 days to form ~5 nm dense oxidization layer (AlO x ). The high quality dense AlO x was also con rmed by the breakdown measurement (Fig. S2). Al layer serves as not only screening layer, but also self-aligned layer for further SiO 2 inductively coupled plasma (ICP) etching. Extra 20 nm SiO 2 was etched to form side-wall structure and 13 nm high-k HfO 2 as gate dielectric was grown via ALD. Then, monolayer CVD MoS 2 lm with 2 cm×2 cm size was wet-transferred and patterned on the substrate. Ti/Pd (2 nm/ 35 nm) as source and drain contacts were made on MoS 2 to complete the device. The nal device has four electrical terminals named source (S), drain (D), 0.34 nm graphene edge gate (G), and the highly p-doped Si substrate back gate (B). By applying the edge of graphene gate a negative voltage to locally deplete the vertical MoS 2 channel, the device can be turned off. The device structure and the main fabrication ow of the 0.34 nm gate-length side-wall transistor are shown in Fig. 2a&b.
The devices after the fabrication were characterized, the SEM image with false-colored and TEM image from a representative sample are shown in Fig. 2c and Fig. 2d. For SEM image, purple region contains monolayer graphene/AlO x /Al/AlO x /HfO 2 stack. The yellow and blue regions represent the MoS 2 channel and Ti/Pd metal contacts. TEM image shows the pro le of the device core region, the layered structure of atomic vertical side-wall MoS 2 channel gated by the edge of graphene can be recognized clearly. The topography MoS 2 lm/HfO 2 (~13.8 nm) stack was smooth. To reduce the ungated channel resistance, source electrode was made very close to the edge of graphene (<50 nm, 14 nm in this device). The spatial distribution of aluminum, hafnium, carbon, molybdenum, sulfur and oxygen was observed in the energy dispersive spectrometer (EDS) mapping of the core region ( Fig. 2e & Fig. S3), thus con rming the location of the monolayer graphene, HfO 2 , Al, AlO x and monolayer MoS 2 in this device. In the fabrication ow, the CVD graphene and MoS 2 were applied as gate and channel materials, which realizes wafer-scale production (Fig. 2f).

Electrical Measurement and TCAD Simulation
A back gate MoS 2 transistor was rst measured (Fig. S4). It indicates that by applying positive back gate voltage (V BS =50 V), the lower extension MoS 2 region on 275 nm SiO 2 / 13 nm HfO 2 can be tuned to relatively high electron carrier density (n + -type). Therefore, the I DS -V GS transfer characteristic at V DS =-50 mV, -1 V, -2 V and -3 V of this side-wall transistor in Fig. 3a is carried out at V BS =50 V, which demonstrate the feasibility of the graphene edge as the gate of side-wall transistor to turn off the channel. The SS is 210 mV/dec and ON/OFF current ratio can reach up to 2×10 5 . Due to the present of SCEs, the value of DIBL is ~1 V/V. Leakage current from monolayer graphene side-wall gate (I G ) and highly p-doped Si substrate (I B ) are both close to the noise level (10 -13 A).
The I DS -V DS output curves under different V GS bias at V BS =50 V is shown in Fig. 3b with a linear-like characteristic. By varying V BS from 0 V to 50 V, which can affect the extension of MoS 2 region, the ON state current increases from 10 -9 A to 10 -7 A and in I DS -V GS transfer characteristic at V DS =-1.0 V (Fig. 3c).
Non-ideal ON state current ~10 -7 A also proves the ultra-thin gate length due to the present of ungated region in the MoS 2 channel. Besides, the transfer curves slightly left shift under larger V BS because the V GS has to be more negative to deplete the vertical MoS 2 channel owing to the ultra-thin 0.34 nm gate length. Three I DS -V GS transfer curves at V DS =-1.0 V and V BS =50 V from different devices are shown in Fig.   3d, the SS and ON/OFF current ratios of the three devices in the same batch are shown in Fig. 3e. These results demonstrate good uniformity of this 0.34 nm L g side-wall transistors.
To understand the electrical behaviors and device physics, Sentaurus TCAD was performed based on this experimental side-wall transistor (Fig. 4a). All the parameters in simulation are close to the actual devices. The lower plane of the extension MoS 2 region is 13 nm below the graphene gate plane in simulation. The comparison of experimental and simulated I DS -V GS curves are shown in Fig. 4b, which have similar trends. The curves negative shifts as V DS becomes more negative, which calls DIBL in small size transistors. The SS in simulation is slightly lower than that in experiment and the ON state current is slighter higher, which is due to the idealized materials and interfaces in the simulation. The electron density and band diagram of ON (V GS -V TH =1.5 V) and OFF (V GS -V TH =-0.5 V) state can demonstrate the ultra-thin 0.34 nm gate control ability. To have a better visibility, the circumstances of MoS 2 channel along the side-wall are shown in Fig. 4c-d and Fig. S6. In the OFF state (Fig. 4c), there is a region of low electron density. The location that graphene edge gate counterparts does not possess the lowest electron density because of the electric eld contributing from the 2D planar surface (Fig. S5). Meanwhile, the reduced electron density (Fig. 4c) and E F (Fig. S6a) shifts downward also veri es the e cient gate control. The extension region is still at high electron density due to the controlling of global back gate. The effective channel length (L eff ) is de ned as the channel region with electron density n<n threshold (n threshold =1.3×10 5 cm -2 ) (19), therefore the ~13 nm side-wall MoS 2 channel close to the graphene plane can be regarded as effective channel. In the ON state ( Fig. 4d & Fig. S6b), the whole MoS 2 channel is at relative high electron density. Therefore, the L eff can be regarded as L g , which is approaching physical limitation.
As the L g reaching the physical limitation, the semiconductor thickness is also required to be scaling down to atomic level, in order to minimize the SCEs 20 . Therefore, MoS 2 layer dependent I DS -V GS characteristic of the 0.34 nm gate-length side-wall transistor has also been simulated (Fig. 4e). With the thickness of MoS 2 channel increases from 0.65 nm (1 layer) to 20.8 nm (32 layers), although the ON state current improves for thicker MoS 2 , the channel can not be completely depleted at the same V GS -V TH , both the ON/OFF current ratio and SS become undesirable. Besides, atomic layer MoS 2 channel is suitable for scalable production, which is promising for next generation electronics.
Realization of small size transistors is a critical demand. The iterative progresses of gate length as a function of time line is shown in Fig. 4f 14,[21][22][23][24][25][26][27][28][29][30][31][32][33] . From 2D planar device to 3D FinFET and further GAAFET, the structure of Si transistors gradually changes with better gate control ability. In the meantime, low dimensional materials come into sight, SWCNT gated MoS 2 transistor reached the smallest physical node 1 nm in 2016 and the gate length has been leveling off for 4 years. Our work promotes the side-wall structure and realizes atomic thickness material gating atomic channel. The side-wall structure utilized the naturally thickness direction, and 0.34 nm in this work is the ultimate gate length to date. Wafer-level 2D CVD monolayer materials can also be realized for future logic and circuit integration. This work shed the light of the Moore's law going down to 0.34 nm node.
2D materials provides us opportunities to scale down the electron device to atomic level. TMDCs show good resistance to SCEs and graphene has high electrical conductivity and ultra-thin thickness. In this work, MoS 2 and the edge of graphene act as channel and gate respectively, which realized ultimate 0.34 nm gate length side-wall transistors. The side-wall structure effectively utilizes the nature ultrathin thickness of graphene and shows the wafer-scale production. The ON/OFF current ratio and SS value could reach 2×10 5 and 210 mV/dec. Further scaling down EOT, improving the MoS 2 lm quality and developing ideal contacts to MoS 2 are essential for device performance enhancement. Nevertheless, this work promotes a new insight to scale down the transistors approaching physical limitation and shed light on next generation electronics.

Methods
(1) CVD growth of graphene and MoS 2 : i. Monolayer graphene growth on Cu: The 3 cm×3 cm CVD monolayer graphene on Cu was bought from Hefei Vigon Material Technology Co., LTD. The monolayer graphene coverage is higher than 99%.
ii. Monolayer MoS 2 growth on Si/SiO 2 : MoO 3 powder (Alfa Aesar 99.95%) contained in a ceramic crucible and adequate sulfur powder (Alfa Aesar, 99.999%) was placed in Zone 2 and at the upstream of furnace in Zone 1, respectively. Cleaned Si/SiO 2 substrate was placed on the crucible. After purge 300 sccm Ar gas 20 min as carrier gas, the growth temperature for the sulfur and MoO 3 precursors was 180 ℃ and 650 ℃, respectively. Continuous monolayer MoS 2 lm was synthesized at room pressure with 10 min sul dation time.
(2) Wet transfer of graphene and MoS 2 : i. Graphene wet transfer: PMMA was rst spin coated on Cu/graphene. Dilute hydrochloric acid (HCl) solution with 20% mass fraction was used to etch supported Cu layer. After Cu was completely etched, graphene/PMMA was transferred to the target sample. Further 85 ℃, 60 min annealing can enhance the adhesion between graphene and substrate. PMMA was removed by acetone for more than 30 min soaking.
ii. MoS 2 wet transfer: PMMA was rst spin coated on Si/SiO 2 /MoS 2 . Potassium hydroxide (KOH) solution with 3% mass fraction was used to lift off MoS 2 /PMMA from the Si/SiO 2 Then, MoS 2 /PMMA was transferred to the target sample. Further 85 ℃, 60 min annealing can enhance the adhesion between MoS 2 and substrate. PMMA was removed by acetone for more than 30 min soaking.
(3) SEM (scanning electron microscopy) imaging was performed by Quanta FEG 450 eld emission scanning electron microscope (FESEM). A 10 kV accelerating voltage was used for imaging the MoS 2 channel and contacted metal.
(4) TEM (transmission electron microscopy) and EDS (energy dispersive spectroscopy) imaging was performed by Themis Z (Thermo Scienti c) with a Super-X (Thermo Scienti c) EDS system. The system operated at 200 kV accelerating voltage. TEM was carried out with a 23.8 mrad convergence angle electron beam and the collection angle was set to 90-370 mrad. The sample was rst deposited carbon by electron-beam and Pt by ion-beam to protect the surface from the damage of the ion-beam.