Logic-in-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback eld-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor eld-effect transistor (p-MOSFET). Further, we investigated the hybrid logic and memory operations of the inverter using mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption.


Introduction
Although the von Neumann architecture, a revolutionary development in the semiconductor industry, has improved integration density and performance in modern computers, physical separation between the processor and memory hierarchy causes energy-hungry data transfer and long latencies [1][2][3] . Considering the rise of data-intensive applications, such as arti cial intelligence, the 5G communication standard, and Internet of Things since the fourth industrial revolution, a novel computing paradigm is essential for the massive data processing requirements.
The logic-in-memory (LIM) architecture is gaining attention owing to its space-saving structure and increased energy e ciency on integrating logic processes and data storage 4 . Most studies on LIM utilize emerging memories, such as resistive random-access memory (ReRAM) 5,6 , spin-transfer torque RAM (STT-RAM) 7,8 , and ferroelectric eld-effect transistors (FEFETs) 9,10 . However, they comprise non-silicon components that are expensive and require additional fabrication procedures. Moreover, owing to the high off-current, ReRAM and STT-RAM require high supply voltages and peripheral circuits to guarantee a su cient sensing margin 11,12 . Additionally, although FEFETs exhibit a relatively high ON/OFF current ratio, reducing the gate voltage based on the high voltage drop across the interface oxide is a challenge 13 , thereby limiting the possibility of achieving high endurance. Therefore, LIM architecture comprising silicon-based devices needs to be explored further to utilize the metal-oxide-semiconductor (CMOS) technology while maintaining a simple structure and high endurance. Therefore, in this study, we propose a CMOS-compatible LIM inverter comprising an n-channel feedback eld-effect transistor (n-FBFET) made of a silicon nanowire (SiNW) and a SiNW p-channel metal-oxidesemiconductor eld-effect transistor (p-MOSFET) made of a SiNW. FBFETs have demonstrated steep switching characteristics and gate-controlled memory behavior, making it a suitable choice for the LIM inverter [14][15][16] . Also, the stable performance of FBFET was proved against the charge trap and electrical bias stress in recent research. 17,18 The proposed LIM inverter provides a high voltage gain while retaining the output logic at zero input voltage. Its memory behavior under zero supply voltage is a result of the FBFET storing electrons and holes in the channel region. Additionally, we demonstrated the hybrid logic and memory functions of the inverter using mixed-mode technology computer-aided design (TCAD) simulation, indicating the possibility of a novel computing paradigm beyond von Neumann's computing.

Methods
All simulations were carried out using 2-D structures via a mixed-mode simulation supported by the Sentaurus TCAD simulator (Synopsys Sentaurus (O_2018.06)), which is a commercial device simulator 20 . The physics models of n-FBFET and p-MOSFET include the Fermi-Dirac statistics, Auger recombination, bandgap narrowing, and Shockley-Read-Hall recombination with doping dependency, whereas the mobility models include doping dependence, normal mobility, and high eld saturation, to analyze the electrical characteristics in the silicon region. Additionally, surface Shockley-Read-Hall recombination was applied to the interface between silicon and Al 2 O 3 in n-FBFET.

Results And Discussion
Device structure and simulation The cross-sectional views of an n-FBFET with a p + -n + -p + -n + SiNW and a p-MOSFET with a p + -n + -p + SiNW are illustrated in Figs   feedback loop was seen in the conduction and valence bands ( Fig. 4(b)). As V IN increases, the barrier height reduces and the electrons ow into the channel region and accumulate in the potential well, which caused a further decrease in the barrier height, and further induced injection of holes into the channel region. This iterative operation resulted in the collapse of the potential barrier, leading to activation of the positive feedback loop. As V IN decreases from 0.5 to 0.0 V, logic '0' is followed by hold '0'. Although the barrier height in the conduction band is higher, the charge carriers accumulated in the potential wells impede the regeneration of potential barriers, thereby enabling the device to maintain the energy level of the drain region that corresponds to hold '0'.
Further, the repetitive time response of the LIM inverter was veri ed by applying positive and negative input voltages with an absolute value of 0.5 V and a pulse width of 100 ns (Fig. 5). The time values when V OUT increases to 63% of its initial value, were denoted as t0 and t1 for logic '0' and '1', respectively. At 63% of the initial logic '1', V OUT was 3.2 ms, and t1 was 3.2 ms (Fig. 7(a)). Alternatively, logic '0' takes much longer to lose the stored logic '0', and, hence, t0 was ~127 s (Fig. 7(b)). It was worth noticing that logic '0' showed a substantially long t0 over 100 s, based on the charge carriers accumulated in the n-FBFET channel region. As a result, the proposed inverter can store over 63% of output logic voltage in 127 s (3.2 ms) for logic '0' ('1') without consuming static power.

Conclusion
We demonstrated the hybrid logic and memory operation of a LIM inverter using mixed-mode TCAD simulations. The inverter exhibited voltage gains of ~296.8 (V/V) when transitioning from logic '1' to '0' and 7.9 (V/V) when transitioning from logic '0' to '1', and it processed the output logic within 100 ns. The simulated energy band diagrams of n-FBFET demonstrated the holding operations implemented with zero input voltage by controlling the positive feedback loop. Furthermore, the proposed inverter was able to retain 63% of the initial output logic of logic '1' and logic '0' for up to 3.2 ms and 127 s, respectively, without supply voltages. The above results verify the possibility of merging logic and memory operations using the proposed LIM inverter while consuming zero static power.