Device structure and simulation
The cross-sectional views of an n-FBFET with a p+-n+-p+-n+ SiNW and a p-MOSFET with a p+-n+-p+ SiNW are illustrated in Figs. 1(a) and (b), respectively. The n-FBFET had dimensional parameters of a channel thickness (TSi) of 10 nm, a channel length (LCH) of 40 nm, and a Al2O3 gate oxide thickness (TOX) of 2 nm. The channel consisted of the p+-doped region below the gate metal and the n+-doped non-gated region; each region had an identical length of 20 nm (1/2 LCH). The doping concentrations of the source, drain, and non-gated channel regions were 1×1020 cm-3. The gated-channel region was heavily doped with a p-dopant concentration of 7 × 1019 cm-3. For the p-MOSFET, a channel thickness (TSi), a channel length (LCH), and gate oxide Al2O3 thickness (TOX) were 10, 40, and 2 nm, respectively. The p-channel had a doping concentration of 1 × 1019 cm-3 and the doping concentrations of the source and drain regions were 1×1020 cm-3. The gate metal work functions were tuned with 5.65 eV for n-FBFET and 4.8 eV for p-MOSFET to obtain the optimal function in logic and memory operation. The simulations were performed in the 2D structure via Synopsys Sentaurus 20.
Fig 1(c) shows the circuit diagram of the LIM inverter that is based on a conventional CMOS inverter, comprising the n-FBFET as a replacement to n-channel MOSFET (n-MOSFET), and a p-MOSFET. A load capacitor (CLOAD) of 1 fF was connected to the output node, assuming a parasitic capacitance existed between the line and logic gates. The circuit was biased with supply voltages VDD and VSS corresponding to the source voltages of p-MOSFET and n-FBFET, respectively, to calculate the output logic states, which were determined by sensing drain voltage of the n-FBFET (VOUT). The n-FBFET in the proposed inverter performs a key function in logic operation and data storage by implementing the memory function while retaining the conventional CMOS logic scheme structure.
Characteristics of the proposed LIM inverter
Fig 2(a) and (b) show the transfer curves of the n-FBFET and p-MOSFET, respectively, under several voltage conditions. The n-FBFET gate voltage (VG) ranges from -1.0 to 1.0 to -1.0 V to verify the hysteresis characteristics at VD = 0.5, 0.0, and -0.5 V (Fig. 2(a)). The latch-up phenomenon occurs during the forward sweep of VG, that is, IDS increases steeply at VG = ~0.6 V. The device shows an extremely low subthreshold swing (SS) of 2.3×10-3 mV/dec at VD = 0.5 V, which is caused by the generation of the positive feedback loop in the channel region. After the latch-up phenomenon, the device transitions to the ON state, showing a high ON/OFF current ratio of 1012. However, when VG sweeps reversely, IDS decreases at VG in a manner dissimilar to the latch-up phenomenon and is referred to as the latch-down phenomenon, after which the device transitions to the OFF state. The gap in VG where the latch-up/latch-down phenomena occur indicates the memory window wherein the FBFET maintains the ON and OFF states of the device before the phenomena occur again. The ON/OFF current ratio and memory window become larger on applying more bias to VD. However, VG remains unaffected. Fig 2(b) shows the absolute value of IDS versus VG for p-MOSFET. As VG decreases, the absolute value of IDS approaches the saturation region at VG = -0.5 V. The p-MOSFET exhibits over 60 mV/dec of SS due to the operation mechanism of thermal injection ; nevertheless, the high current ON/OFF ratio of ~1015.
Switching and memory operations in the LIM inverter
Fig 3(a) shows the voltage transfer characteristics (VTC) of the LIM inverter with supply voltages VDD (0.5 V) and VSS (-1.3 V). The output logic ‘0’ (or ‘1’) indicated the distinct low (or high) voltage value of VOUT when an input voltage VIN of 0.5 V (-0.5 V) was applied. Unlike a conventional CMOS logic inverter, the proposed inverter exhibits hysteresis characteristics, that is, the output logic states switch at different VIN. Therefore, the LIM inverter holds the logic data when VIN = 0.0 V, as illustrated in Fig. 3(a). Hold ‘0’ and ‘1’ were determined by the processed logic state with VIN = 0.0 V.
Fig 3(b) shows the inverter gains obtained from the absolute value of the differentiation of VOUT from VIN. When p-MOSFET was turned on, the device transitioned from logic ‘0’ to ‘1,’ and a relatively low inverter gain of ~7.9 V/V was observed, owing to the SS of over 60 mV/dec. Alternatively, logic ‘1’ steeply transitioning to ‘0’ resulted in a high gain of ~296.8 V/V owing to the latch-up phenomenon in n-FBFET. Because of the steep transition slopes, the proposed inverter obtains a sufficient voltage margin for memory operation, thereby enabling operation in a narrow VIN range.
Fig 4 shows the conduction and valence bands of the n-FBFET to analyze the holding operation. The dashed lines and solid lines in red indicate the logic and hold states, respectively. When the output logic is ‘1’ (VIN = -0.5 V), potential barriers were created in the channel region (Fig. 4(a)), and the positive feedback loop is absent in the energy band diagram. The barrier height in the conduction band decreased as VIN increased from -0.5 to 0.0 V. However, the potential barriers were high enough at VIN = 0.0 V itself to block the injection of electrons into the channel region. Therefore, the energy level in the drain region remained constant, corresponding to hold ‘1’. Alternatively, when the output logic was ‘0’ (VIN = 0.5 V), a positive feedback loop was seen in the conduction and valence bands (Fig. 4(b)). As VIN increases, the barrier height reduces and the electrons flow into the channel region and accumulate in the potential well, which caused a further decrease in the barrier height, and further induced injection of holes into the channel region. This iterative operation resulted in the collapse of the potential barrier, leading to activation of the positive feedback loop. As VIN decreases from 0.5 to 0.0 V, logic ‘0’ is followed by hold ‘0’. Although the barrier height in the conduction band is higher, the charge carriers accumulated in the potential wells impede the regeneration of potential barriers, thereby enabling the device to maintain the energy level of the drain region that corresponds to hold ‘0’.
Further, the repetitive time response of the LIM inverter was verified by applying positive and negative input voltages with an absolute value of 0.5 V and a pulse width of 100 ns (Fig. 5). To demonstrate the holding characteristics at VIN = 0.0 V, VIN is not pulsed for 200 ns after the logic process ends. The output logic transitions from ‘1’ to ‘0’, as a VIN of 0.5 V is applied to input logic ‘1’. Conversely, the output logic switches to logic ‘1’, as a VIN of -0.5 V is applied to input logic ‘0’. This stable logic process was conducted for 100 ns. It was observed that the inverter maintained a constant logic voltage value without voltage degradation, thereby verifying the logic processes and storage ability of the proposed inverter within a voltage range of -0.5 to 0.5 V for 100 ns, under the corresponding supply voltage conditions.
Operation of LIM inverter under zero-bias conditions
Recently, FBFETs have demonstrated superior memory characteristics under zero-bias conditions by controlling the charge carriers accumulated in the channel region 16. Thus, it was crucial to verify the memory behavior of logic circuits comprising FBFETs without supply voltages. As shown in Fig. 6, the supply voltages VDD and VSS were input to the circuit with the same pulse width as that of the input logic pulse. Hold ‘0’ and ‘1’ (VIN = VDD = VSS = 0.0 V) lasted for 10 μs after the output logic is processed. When input logic ‘0’ is applied for 100 ns with a VDD of 0.5 V and a VSS of -1.3 V, the LIM inverter displays the output logic as logic ‘1’. Further, when supply voltages were removed, VOUT decreased slightly and was affected by the current through p-MOSFET. Nevertheless, VOUT remained constant for hold ‘1’ because the potential barriers in n-FBFET prevented further injection of charge carriers. When input logic ‘1’ was applied with the same supply voltages, the output logic transitioned from logic ‘1’ to ‘0’. For hold ‘0’, VOUT consistently retained the initial value as of output logic ‘0’ without any voltage drops. Because the charge carriers were accumulated in the n-FBFET channel region, logic ‘0’ remained consistent by maintaining the positive feedback loop, which allowed the LIM inverter to retain data in the absence of a voltage supply. Furthermore, the LIM inverter did not consume static power because VDD and VSS became 0.0 V. Since the static power is calculated as multiple of supply voltage and current through the circuit, the LIM inverter consumed zero static power during hold ‘0’ and ‘1’ while not requiring alternate peripheral circuits.
Fig 7 shows the VOUT values of the time function after calculating the logic state for 100 ns to confirm the possible extent of the holding operation under VDD = VSS = VIN = 0.0 V. As time was increased to 1000 s, VOUT gradually approaches zero voltage during the holding operation, which affects the continuous leakage current running through the circuit. The time values when VOUT increases to 63% of its initial value, were denoted as t0 and t1 for logic ‘0’ and ‘1’, respectively. At 63% of the initial logic ‘1’, VOUT was ~3.2 ms, and t1 was 3.2 ms (Fig. 7(a)). Alternatively, logic ‘0’ takes much longer to lose the stored logic ‘0’, and, hence, t0 was ~127 s (Fig. 7(b)). It was worth noticing that logic ‘0’ showed a substantially long t0 over 100 s, based on the charge carriers accumulated in the n-FBFET channel region. As a result, the proposed inverter can store over 63% of output logic voltage in 127 s (3.2 ms) for logic ‘0’ (‘1’) without consuming static power.