Design and energy analysis of a new fault-tolerant SRAM cell in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is an emerging technology proposed in response to the limitations of CMOS technology. Moreover, static RAM (SRAM) is crucial for memory design, and efficient RAM design can play a significant role. This paper proposes a fault-tolerant QCA SRAM cell based on QCA three- and five-input majority gates. This cell is implemented on a single layer and does not require any rotated cell, which significantly improves the manufacturability and robustness of the design. Furthermore, our design can tolerate a single omission fault. The proposed 3-input majority gate improves complexity, area, and energy dissipation, on average, by 54%, 68%, and 67% in 1 Ek, respectively, as compared to its previous counterparts. The proposed fault-tolerant SRAM cell improves the complexity, area, and total energy dissipation by almost 13%, 25%, and 35% in 1 Ek, respectively, as compared to its state-of-the-art QCA-based single-layer fault-tolerant counterpart.


Introduction
The VLSI chip design industry has developed in recent decades. Following the Moore's law, the size of the transistors has reduced to the nanoscale, while the number of computations performed per unit of time increased immensely (AlKaldy et al. 2020;Majeed et al. 2019a;Taherkhani et al. 2017). In general, to design VLSI circuits, the critical performance parameters such as speed, area, complexity, power consumption, and reliability should be considered as the portable electronic devices face issues such as limited battery lifetime and excessive power consumption (Ahmad et al. 2019;Abutaleb 2017; Bagherian Khosroshahy et al. 2022;Majeed et al. 2019b). Supply voltage scaling has been a unique method for reducing overall power dissipation (Sabetzadeh et al. 2019). The energy dissipation within the VLSI chips is due to the interconnects and transistors. The chip designers have proposed many techniques such as charge recovery and energy recapturing to mitigate energy dissipation.
Moreover, by reducing the feature size, reliability and fault tolerance have been raised as critical issues in modern chips (Kumar and Singh 2019). As a result, to address this issue, circuit designers introduced fault-tolerant designs. Nowadays, there are many efforts to this issue. However, it is worth noting that different applications come with different requirements. Detecting and tolerating faults has been well studied and is an area of research in circuit design (Abdoli et al. 2015;Abdoli 2019).
Faults in QCA circuits can occur due to the production process and misalignment of cells on a surface. Considering the very small size of QCA cells and the high accuracy required for the cell alignment, these defects can be introduced during the deposition phase. The deposition phase is divided into cell omission, extra-cell deposition, and cell displacement (Bagherian . Thus, fault tolerance is crucial for the design and manufacturing of QCA integrated circuits.
This paper proposes a fault-tolerant three-input majority gate and a modified fault-tolerant five-input majority gate. Then, with the use of the proposed building blocks, we design a QCA-based SRAM cell. The advantages of the presented design compared to the other SRAM cells are its smaller area, lower cell count, and lower energy consumption. Moreover, we do not use any rotated cells in the proposed single-layer SRAM cell, facilitating the fabrication process and lowering the fabrication costs.
The remainder of this paper is organized as follows: Sect. 2 reviews the QCA preliminaries. The previous works are discussed in Sect. 3. Section 4 describes the implementation of proposed area-efficient fault-tolerant QCA logic gates. Simulation results and comparisons are presented in Sect. 5. Finally, Sect. 6 concludes the paper.

Fabrication of QCA circuits
QCA circuits can be fabricated with different materials such as metal islands, semiconductors, nano-magnetics, and molecular structures. The metal-island QCA can be fabricated on a silicon wafer. Aluminum islands and aluminum-oxide tunneling junctions are implemented on a silicon wafer to create metal-island QCA cells. This fabrication approach has been discussed in detail in (Orlov et al. 1997). In addition, the semiconductor QCA type can be implemented based on electron beam lithography on the GaAs/ALGas heterostructure material, as reported in Smith et al. (2003), Wang and Liu (2011). The semiconductor QCA cell simplifies encoding binary information and is more suitable for binary computation as each cell's two existing quantum dots can provide two distinct codes (Ottavi et al. 2006;Tougaw and Lent 1994). Besides, the fabrication of nanomagnetic QCA cells has been reported in Cowburn and Welland (2000). Moreover, a one-bit full adder cell has been fabricated based on nanomagnetic logic with three majority and four inverters gates (Breitkreutz et al. 2013). Furthermore, the molecular method can be implemented with different materials such as graphene (Wang and Lieberman 2004;Chaudhary et al. 2007;Pulimeno et al. 2013). The input 0 and 1 logics can be applied from the top layer because of the 3D structure of this approach (Bagherian Khosroshahy et al. 2016). In addition, scientists have made promising efforts to find new fabrication methods to decrease fabrication costs and increase stability for these systems. Accordingly, they have implemented the QCA building blocks based on The Ti/Al patterned with electron beam lithography on the GaAs/AlGaAs heterostructure (Turvani et al. 2017;Gu et al. 2022). The QCA clocking and signal propagation to provide fault tolerance capability in different situations have been evaluated, and the experimental results have been introduced in Cong and Blair (2022). Recently, in a new effort in this area, the experts have fabricated magnet QCA elements introducing a way to fabricate RAM based on Magnet QCA as described in Rana et al. (2021).
There are two different positions for electrons inside a QCA cell representing 0 or 1 logic. Given the quantum-mechanical mechanism, the electrons can tunnel between the dots and achieve cell polarization of P = −1 (logic 0) or P = 1 (logic 1) as illustrated in Fig. 1a. The polarity can be defined through Eq. 1, where i is the probability of the presence of an electron in quantum-dot i (Momenzadeh et al. 2005;Liu et al. 2014;Lent and Tougaw 1997;Dysart 2013).
The coulomb energy interaction force between the two electrons in each cell is calculated by Eq. 2 (Sheikhfaal et al. 2015).
where E ij is the kink energy, K = 9 × 10 9 J m/C 2 is the Coulomb constant, q i and q j are electric charges ( 1.6 × 10 −19 C ), and r ij is the distance between two electric charges i and j.
The electrostatic energy applied to electrons q i q j are calculated by Eq. 4.
In the QCA technology, inverter and majority gates are two essential gates for logical calculations, as shown in Fig. 2a and b. The majority gate votes among the input cells and propagates the majority polarization of the inputs to the output cell. Assuming that the inputs are a, b and c, the logic function of the majority gate is expressed in Eq. 2. By fixing one of the inputs to binary '0' or '1', the majority gate turns into a logic "AND" or "OR"  (Liu et al. 2014;Lent and Tougaw 1997;Dysart 2013;Wang and Lieberman 2004;Danehdaran et al. 2018).
The clock signal is the only source of power in QCA circuits. The clocking mechanism is used in pipelining and determining data direction. The mechanism consists of four-phase clock signals, used to propagate data through the logic circuits (Liu et al. 2014;Lent and Tougaw 1997;Dysart 2013;Wang and Lieberman 2004;Danehdaran et al. 2021;Abutaleb 2019). The clocking mechanism consists of the switch, hold, release, and relax phases, as illustrated in Fig. 2.
Another important issue is QCA circuit is wire crossover. Generally, there are three QCA crossovers methods: multi-layer crossover, coplanar crossover, and different phase crossover (Bagherian Khosroshahy et al. 2016) as shown in Fig. 3.
In multi-layer crossover, two separate substrates are required to prevent interference between intersecting QCA wires polarization. There have been no reports indicating the implementation of multi-layers crossovers based on semiconductor-QCA circuits. However, a hybrid method for implementing multi-layer crossovers based on molecular-QCA circuits has been introduced in which graphene is used as the substrate, and carbon nanotube is used to create multi-layer crossovers. In the coplanar crossover, a wire with normal cells crosses another wire with cells rotated by 45°. The binary polarization of the crossing wires does not affect each other. This method is not robust enough, and to mitigate this limitation, another kind of crossover is used in which there is a 180° phase difference from the clock signal of one crossing wire to the clock signal of the other wire (Bagherian Khosroshahy et al. 2016). In different phase crossover, the crossing wires should have  (Shin et al. 2013).
The defect is a critical issue in QCA cells. The defects in QCA technology occur in the deposition process. Various defects are shown in Fig. 4, which can essentially be divided into four categories: cell omission, cell displacement, cell misalignment, and extra cell deposition.

Previous work
In this section, the previous fault-tolerant QCA majority and RAM cells are reviewed. Majority and inverter gates are two crucial elements in the QCA technology, which serve as the building blocks for extending more complex circuits. Hence, these gates should be designed to accommodate a variety of different applications. Moreover, in some applications such as mission-critical systems, fault tolerance is a top priority, with area, latency, power, and complexity criteria coming next in terms of importance. Besides introducing fault-tolerant designs, decreasing other parameters is crucial. For example, one might need to have a low power device in some applications because maybe power sources are not available for an extended period (Khosroshahy et al. 2017a).

Fault-tolerant three-input majority gates
The authors Das and De (2010) proposed a fault-tolerant three-input majority gate with higher complexity and occupied a large area (Fig. 5a). Du et al. (2016) introduced a fault-tolerant three-input majority gate with higher complexity and occupied a large area (Fig. 5b). Kumar and Mitra (2016) provided a fault-tolerant three-input majority gate with higher complexity, occupied a large area, and required two clock phases (Fig. 5c). Sun et al. (2018) provided a fault-tolerant three-input majority gate with higher complexity and occupied a large area (Fig. 5d). Sen et al. (2004) suggested a fault-tolerant three-input majority gate with higher complexity and occupied a large area (Fig. 5e). Moghimizadeh and Mosleh (2019) proposed a fault-tolerant three-input majority gate with higher complexity and used rotated cells (Fig. 5f). Besides, Sen et al. (2004Sen et al. ( , 2016 in their designs use rotated cells, which can increase fabrication costs. Sen et al. (2016) proposed a fault-tolerant three-input majority gate with higher complexity and occupied a large area (Fig. 5g). Wang et al. (2018) proposed a fault-tolerant three-input majority gate with higher complexity and occupied a large area (Fig. 5h). Ahmadpour et al. (2020b) proposed a fault-tolerant threeinput majority gate with higher complexity, which occupied a larger area. Foroutan et al. (2021) proposed a fault-tolerant three-input majority gate that increased the complexity and occupied area.

Fault-tolerant five input majority gates
There have been many five-input majority gates for embedded applications. Figure 6a shows the design proposed in Farazkish (2014), which is implemented with a high number of cells and occupies a large area. In this work, the single-cell omission was investigated. The main disadvantage of this design is that the output cell is placed in the middle of the design, and hence, it is required to use a multi-layer structure for cascading.
Another design introduced in Farazkish (2014) is shown in Fig. 6b. This cell is implemented with an efficient number of cells and has a smaller area compared to the design of Farazkish (2014). The design presented in Goswami et al. (2016), which is shown in Fig. 6c, was implemented with a large area to tolerate single-cell omission. In Sun et al. (2018), another fault tolerant 5-input majority was presented, which is shown in Fig. 6d. In Moghimizadeh and Mosleh (2019) another fault tolerant five-input majority gate was presented (see Fig. 6e), which was implemented with a large area and high cell count for tolerating single-cell omission.

Fault-tolerant RAM
A fault-tolerant RAM cell based on a five-input majority gate was presented in Moghimizadeh and Mosleh (2019). This design, which is shown in Fig. 7, uses the corner type inverter instead of the fault-tolerant inverter gate in its structure. Besides, this design occupies a large area and suffers from high complexity and high power consumption to implement a fault-tolerant RAM cell.

The proposed fault-tolerant three-input majority gate
The proposed fault-tolerant three-input majority gate is shown in Fig. 8.
In this design, we add five cells to the baseline three-input majority to cover singlecell omission fault. It is worth noting that our cell's output is reachable, and no multilayer implementation is required for cascading. Furthermore, it does not require any rotated cells, which reduces the complexity and manufacturing costs. In this section, this structure is evaluated using physical verification based on the single-cell omission fault. Considering Tables 1, 2, 3 and 4, the design shown in Fig. 5a is more stable compared to the design shown in Fig. 5b. Considering the calculation results, the output value place in a stable level of energy when one pair electrons place with lower neighboring forces, so based on results of Table 3 output electrons placement in Fig. 9a have much stable and design could kept their functionality.

Analyzing the fault tolerance of the utilized five-input majority gate
The five-input majority gate used for designing the proposed RAM cell was introduced in Khosroshahy et al. (2017c). This cell is shown in Fig. 10. However, the original paper did not report any mathematical proof to show the fault tolerance capabilities of this design. Moreover, the original work exclusively used this five-input majority gate for low-power  applications. In this section, this structure is evaluated using physical verification based on the single-cell omission fault. We investigate the single-cell omission on the central voter cell as the energy at the center of the design is critical. Therefore, the worst-case scenario occurs when the central cell is missing. The assumed values of input cells are a = 1 , b = 1 , c = 1 , d = 0 , and e = 0 . The kink energies between the electrons in this design are given in Tables 5, 6, 7 and 8. Considering the results, the case shown in Fig. 11a is more stable than the one shown in Fig. 11b. The proposed majority gate implements in symmetric shape that issue help to designers for better physical management. Also, this design has a good output derive and can easily change the next levels of any circuit.     Considering the calculation results, the output value is placed in a stable energy level when one pair electrons place with lower neighboring forces, so based on Table 7, output electrons placement in Fig. 11a have much stable and design could keep their functionality.

Proposed fault-tolerant RAM design
RAM cells are among the most critical blocks in any electronic system. In the QCA field, RAM cell design is based on two types, which are loop-based and line-based (Khosroshahy et al. 2017a). In the loop-based type, the store mechanism works using a loop containing the clocks' entire zone. Besides, a QCA wire is used to store the previous output like a pipeline in line-based type.
In the QCA field, the loop-based type design is totally used for the SRAM memory cell design. In this structure, the storage mechanism is worked via circling a bit of data within a wire-loop of the QCA cells. In this case, usually, some popular logic functions such as D-latch, SR-latch, multiplexer, and majority gates are used (Khosroshahy et al. 2017b).
Despite the great importance of the QCA RAM cell, the fault tolerance aspect of this cell has not been much assessed. This section proposes two fault-tolerant line-based RAM   cells with the set/reset ability in QCA. In the proposed design shown in Fig. 12, we used the new 3-input fault tolerance majority gate in our structure. The fault tolerance proof of the proposed 3-input majority gate is shown in Tables 1 through 4. The proposed RAM design consists of four three-input majority gates and one five-input majority gate. Moreover, this design has four control lines, including Set, Reset, Select and write/(read). In the primary state, it produces (Set = '0' and Rest = '0') when the select line is activated ('1') and the write/(read) line is set to '1', that the input data will be transmitted to the output, and consequently, the write operation will be performed. Additionally, the read operation is performed by setting the select and the write/(read) signals to '1' and '0', respectively. In the set mode that Set = '1' and Reset =' 0' the bit stored on the RAM cell will be set to '1'. Similarly, in the reset mode that Set = '0' and Reset = '1' the bit stored on the RAM cell will be reset to '0'.

Fig. 12
The structure of the proposed majority-based SRAM cell It is worth noting that, in the previous fault-tolerant RAM cells (Moghimizadeh and Mosleh 2019) corner inverter gate was used instead of a fault-tolerant inverter gate to reduce the cell count. However, based on the fault tolerance design rule, all gates used in a fault-tolerant circuit must be implemented based on fault tolerance structures. Accordingly, using non-robust corner inverters in the RAM cell presented in Moghimizadeh and Mosleh (2019) is a critical violation of the fault-tolerant design. As a result, to address this issue in the proposed design, we use the fault-tolerant inverter gate to keep the privileged requirements.

Performance evaluation
In order to simulate our QCA circuits, the QCADesigner tool (Walus et al. 2004) is used as the most famous and powerful tool for QCA simulation purposes. The critical parameters used for the simulation are QCA cell size = 18 nm, diameter of quantum dots = 5 nm, number of samples = 50,000, convergence tolerance = 0.001, radius of effect = 65 nm, relative permittivity = 12.9, clock low = 3.8e −23 J , clock high = 9.8e −22 J , clock amplitude factor = 2.000, layer separation = 11.5 nm, and maximum iterations per sample = 100. The simulation results, shown in Figs. 16,17,and 18, validate the functionality of the proposed fault-tolerant RAM cells. Moreover, Tables 9, 10, and 11 compare the proposed fault-tolerant three-input, five-input, and RAM cells designs.
The QCAPro tool is widely used to evaluate the leakage, switching, and total energy dissipations of the QCA circuits (Srivastava et al. 2011). Tables 12, 13, and 14 present the energy dissipation analysis of the proposed fault-tolerant three-input majority gate, fault-tolerant five-input majority gate, and the proposed RAM cells. The simulation results are calculated in three levels of distinct tunneling energies (0.5Ek, 1Ek, and 1.5Ek), considering 2K as the conventional operational temperature for QCA energy analysis. Figures 13 and 14 show the thermal map of our designs at 2K temperature    Fig. 15 shows the thermal map of the proposed fault-tolerant RAM cell alongside some state-of-the-art designs at 2K temperature and 1Ek. It is worth pointing out that the darker the QCA cells are, the more energy is dissipated in the circuit. In general, leakage, switching, and total energy dissipations in QCA circuits are evaluated by the QCAPro tool (Srivastava et al. 2011). This model was derived from the quasiadiabatic model. The equation for calculating the instantaneous power is given by: where ⃗ is the coherence vector, ⃗ is the three-dimensional energy vector and ⃗ is total energy vector applied to the reference electron. The first term in this equation captures the power in and out of the clock and cell to cell power flow.  The graphical thermal maps of the RAM cells are depicted in Fig. 15, which reflect the total energy dissipation of the designs. This diagram attests to the energy efficiency of our proposed structure.
According to Fig. 15, it can be concluded that our design has much lower energy dissipation in comparison to the previously reported designs. Appropriate cell arrangements and avoiding rotated cells in the proposed design are the most important reasons for such minimized energy consumption.
The simulation results of the proposed designs are shown in Figs. 16, 17, 18. All simulations have been conducted using the QCAdesigner tool. In Fig. 16, when two or more inputs are equal to '1', the output produces '1', and when one or more inputs are '0', the output produces '0'. In Fig. 17, when three or more inputs are equal to '1', the output introduces '1', but when three or more inputs are equal to '0', the output shows '0'. In Fig. 18, the simulation results authenticate the correct operation of the proposed circuits according to the expected values given in Table 15. For instance, in the write mode that P = '0', Q = '1', Select = '1' and Write=Read = '1', the new input data appears at the output after 1.25 clock cycles. Also, in the read mode that P = '0', Q = '1', Select = '1' and Write=Read = '0', the previous output data, latched inside the loop, is held at the output to be read independent of the input data value. Moreover, by fixing both P and Q control signals to '0' or '1', the output data will be reset or set, respectively, after 1.25 clock cycles independent of the input data and the Select signal.
In an objective comparison of the total energy dissipation (over all of the possible vector pairs) to the previously reported fault-tolerant QCA SRAM Cells, our proposed design dissipates, on average, 26%, 35%, and 38% lower energy in 0.5Ek, 1Ek, and 1.5Ek tunneling energy levels, respectively.

Conclusion
In this paper, we proposed a fault-tolerant three-input majority capable of tolerating a single-omission fault. Our design, has less complexity, smaller area, and lower energy consumption compared to the other state-of-the-art implementations. Besides, we used a square shape for the proposed fault tolerant three input majority, which can help designers to develop with low garbage milieu in the cheap area. Accordingly, we designed a new fault-tolerant RAM cell with high efficiency regarding complexity, area, and energy consumption. Finally, comparing to the state-of-the-art QCA-based single-layer faulttolerant SRAM cells, we achieved considerable improvements in terms of complexity, area, and total energy dissipation by 13%, 25%, and 35% in 1Ek, respectively.