A Compact Model of Backscattering Coe�cient and Mobility of Graphene FET for SiO2 and h-BN Substrates

The ﬁeld dependent compact model of backscattering coeﬃcient and quasi-ballistic mobility of charge carriers in graphene have developed for two diﬀerent substrates: silicon dioxide (SiO 2 ), and hexagonal boron nitride (h-BN). The formulation of the backscattering coeﬃcient is performed using the Landauer and McKelvey Flux Theory (MFT) in quasi-ballistic regime. In graphene, acoustic phonon (AP), surface optical phonon (OP) and charged impurity (CI) scatterings are present among the charge carriers. That is carefully considered during the formulation of backscattering coeﬃcient (R) and quasi-ballistic mobility ( µ eff ) . We ﬁnd that the Graphene Field Eﬀect Transistor (GFET) with h-BN substrate has the lower backscattering and higher quasi-ballistic mobility. The modeled expression of backscattering coeﬃcient and quasi-ballistic mobility is substituted in drain current ( I DS ) of GFET devices having SiO 2 and h-BN substrate, have shown good agreement with the experimental results.


Device Fabrication
The graphene-on-BN structure shown in Figure 1(a), is fabricated by mechanical transfer process, where h-BN layers are exfoliated from Pristine h-BN single crystals and transferred onto predefined metal gates (1nm Cr/ 20nm AuPd). The device utilizes the same h-BN dielectric layer as both a supporting substrate and local-gate dielectric [22]. While in graphene-on-structure, the graphene monolayer sheet is grown by chemical vapour deposition (CVD) on copper substrates. After the growth, polymethyl methacrylate (PMMA) is coated on the graphene films, and the copper substrates are etched away in

Backscattering Coefficient
The backscattering coefficient (R) is the ratio between fluxes originated from source terminal and returning back to it after scattering. Here, the different scattering mechanisms are carefully consider during the formulation of R. Now the 2D backscattering mean path can be given as [20] where v x = (2/π)v f is the average velocity of the charge carriers, τ 2D is the electron-phonon scattering rates is given by where, τ AP , τ OP , and τ CI are the acoustic phonon, optical phonon and charge impurity scattering rates respectively. The AP scattering rate is [10] The OP scattering rate is The charge impurity scattering rate is described as, where ℏ = 1.05 × 10 −34 m 2 kg/sec is the reduced Plank's constant, k B is the Boltzmann constant, T = 300K is the room temperature, v f is the Fermi velocity, ρ m = 7.6 × 10 −7 kg/m 2 is the mass density, v ph = 2 × 10 4 m/sec is the AP velocity of charge carrier in graphene, h = 6.62 × 10 −34 m 2 kg/sec is the Plank's constant, N imp is the charge carrier impurity density at graphene/substrate interface [24], ℏω OP is the optical phonon energy, the surface OP energies of SiO 2 , and h-BN substrates, D AP is the deformation potential of acoustic phonons, D OP is the deformation energy of optical phonons, this energy for SiO 2 , and h-BN are 5.14 × 10 7 , and 10 6 to 1.29 × 10 9 eV /cm respectively [10]. E is the energy of the charge carrier in channel region of GFET, is given by following the Beranger and Wilkins (see Figure 1(b)) [25], [26] where, V (x) = xE x is the channel potential along (x-axis) the channel length, E x is the constant electric field in x-direction, and E 2D is the charge carrier average energy, which can be written as, where is the Fermi energy, and n 2D is impurity carrier density in graphene monolayer. One flux method is used to relate the positive and negative flux, is given by [17], [18] d where − → n (x) and ← − n (x) is the positive and negative moving charge carriers respectively. Here it is assumed that the velocity of positive and negative charge Using the boundary condition ← − n (x) = 0 and the current continuity equation − → n (x)v(L) = and integrating equation (9) with respect to x we have Now substituting the value of λ 2D (x) from equation (1) and solving the equation (10) using the boundary conditions (11) Now the expression for backscattering coefficient is the ratio of positive and negative going flux is given by, , and qEx is the distance at which the potential drops to the value (k B T )/q, and E 2D is the average energy of the charge particles.

Quasi-Ballistic Mobility
The field dependant expression of quasi-ballistic (µ ef f ) model for 2D GFET is given by [20]; where, h is the Plank's constant, T (⟨E 2D ⟩) is the transmission coefficient, and M (E F ) is the number of channel, which is given by, where, W is the width of the graphene monolayer, E = ℏv f k is the band energy. The transmission coefficient From (12), we see that backscattering coefficient is dependent on the carrier energy mean free path via different scattering mechanisms. Now the expression for the quasi-ballistic is, or, where, R is the backscattering coefficient given in equation (12), N 2D is the carrier concentration in graphene monolayer, which indicates that µ decreases with the increase in N 2D . While remaining symbols have their usual meanings.

Drain Current Calculation
The drain current expression for graphene FET in quasi-ballistic regime using the MFT is given by [28], [29] where, W is the width of the graphene monolayer, /πm * is the thermal velocity, m * is the effective mass of the charge carriers , n(x) = q 3 V ch V ch π(ℏv f ) 2 is the sheet carrier density in graphene monolayer, U DS = (qV DS )/(k B T ), V DS is the drain to source voltage R is the back scattering coefficient, which is defined thoroughly in the model development section, and V ch is the channel potentials, which is the depends on the oxide capacitances and bias voltages, is given by [30] where, C tox = ϵtox tox , C box = ϵ box t box is the capacitance per unit area formed by top, back oxide, t tox /t box is the thickness of top, back oxide layers and ϵ tox /ϵ box is permittivity of the top and back gate oxide materials. V T,ef f = (V T GS − V T GS,0 ) and V B,ef f = (V BGS − V T GS,0 ), where are the top and back gate overdrive voltages respectively. Theses overdrive voltages comprise of the work function difference between gate oxide and graphene channel as well as the possible additional charge density due to impurity or doping. C q is the quantum capacitance. The expression for quantum capacitance is [31], where, where, N G is the gate voltage induced channel charge density, and remaining symbols have their usual meanings.

Results and Discussion
The numerical computing software MATLAB [21] is used for the simulation of our proposed analytical compact model. Using this set of expressions in simulate the I DS for GFET device having SiO 2 and h-BN substrates are compared with experimental data extracted from [22] and [23]. The scattering rates are the important factor, because it strongly affects the backscattering coefficient and charge carrier mobility shown in figure 2 (a). The acoustic phonon scattering plays an important role in piezoelectric substrates, is considered in the formulation of backscattering coefficient and quasi-ballistic mobility. However, the optical phonon (OP) and charge impurity (CI) scatterings mechanism are induced by the substrate of GFET device. The CI scattering is depends upon the graphene/substrate interface trap carrier density, for h-BN substrate CI scattering is ten times lower than the SiO 2 substrate. The h-BN substrate has smaller backscattering coefficient as compare to the SiO 2 substrate. This is happen due to lower charge trap density at graphene/substrate interface, and higher optical phonon energy. The h-BN and SiO 2 substrates have the surface optical phonon energy of 200 and 55 meV respectively. The high optical energy of h-BN substrate will suppress the most of the surface OP scattering. While the lower optical energy is not sufficient to suppress the surface OP scattering by the Pauli exclusion Principle [32].
The figure 2 (b) presents the backscattering coefficient (R) of the charge carrier in graphene with respect to the drain to source voltage (V DS ) for h-BN and SiO 2 substrates. The backscattering coefficient in channel region is almost constant at lower values of V DS . While at higher value of V DS , R is deceases, i.e. the charge carrier in graphene channel is more directed at higher value of V DS and having less scattered with the in-plane and out-plane charge carriers.
The figure 2 (c) presents the carrier mobility in quasi-ballistic regime with respect to the drain to source voltage (V DS ) at constant value of the electric field (E x ) for h-BN and SiO 2 substrates. The mobility of charge carrier for GFET on a SiO 2 substrate decreases with respect to the N 2D , while it has lower dependency of the carrier density as compare to GFET on h-BN substrate. The quasi-ballistic mobility of charge carrier in GFET device for both substrates is decreased due to the CI scattering mechanism. The CI scattering mechanism is strongly depends on the impurity density of the substrates. The GFET device with h-BN substrates exhibits more fluctuations in mobility, due to charged impurities that are one or two orders of magnitude lower than the SiO 2 substrate. For lower value of N 2D the carrier mobility of GFET for h-BN has 165000cm 2 /V − s. From figure 2 (d), it appears that the mobility is increasing as a function of electric field (E x ≈ 10 6 V /m), and decreases sharply at higher value of electric field. Because according to equation (6) the average energy of charge carrier depends upon the Fermi energy, and the high electric field may increases the scatterings among the charge carriers, this may cause of decrease in quasi-ballistic mobility of the charge carrier. After investigation of these two substrates we found that the h-BN maintains high carrier transport and is reliable substrate of graphene based FET devices for high-speed circuit applications. After investigation of these two substrates we found that the h-BN maintains high carrier transport and is reliable substrate of graphene based FET devices for high-speed circuit applications.
The figure 3(a), shows the channel voltage (V ch ) dependent quantum capacitance (C Q ) and revealed the band symmetry of graphene material. However, C Q is used to measure density of states of graphene directly and also an efficient way to explore various peculiarity occurring near the Dirac point. The figure 3(b), is the plot of the carrier velocity versus the electric field for different trap charge densities, at graphene/substrate interface. The higher trap density will increase the charged impurity scattering rate, which has a large impact on the carrier velocity. For this purpose, the GFET device having the lower trap density at graphene/h-BN substrate interface, causes higher carrier velocity. Now using the expression of R from equation (12) and µ ef f from equation (17) in the I DS equation (18), the output characteristics of GFET device having the h-BN and SiO 2 substrate respectively are shown in figure 4. The figure 4(a) and (b) shows the output characteristics of top-gated GFET device having 1µm and 440nm gate lengths respectively. At V T,GS = −0.5V , the observed effect is known as 'kink' effect, which is describe the peculiar ambipolar behaviour of charge carrier in the channel region of GFET [31].

Conclusion
In this paper, we present an explicit model for backscattering coefficient and mobility of charge carrier for graphene-on-substrate (h-BN and SiO 2 ) FET devices. Here the substrate induced scattering rates are carefully considered during the formulation of quasi-ballistic mobility, and observed that h-BN is most suitable material for GFET device. It also observed that at high electric field the mobility of charge carrier is greatly reduced due to scattering among the charge carriers. The proposed expressions of R and µ are used in the I DS equation to simulate the peculiar output characteristics of GFET devices. Further from this paper it is clear that the h-BN substrate is more reliable for high performance GFET devices. It offers the higher carrier mobility and lower backscattering coefficient. The proposed expression of quasi-ballistic mobility and backscattering coefficient is used in I DS equation, which is simplified enough to implement in HDL (Verilog-A). The HDLs describes the behaviour of model in terms of their ports and parameters applied, and used for the circuit implementations in Cadence like circuit simulator environments.