A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis


 Background: Recording of electrical activity of neurons is indispensable for decoding the information in the brain. The amplitude of signals recorded by electrodes is small, and it must be amplified to the level that can be digitalized by the analog-to-digital convert (ADC). A micro-power low-noise neural recording amplifier is indispensable for implant hippocampal cognitive prosthesis. When the process turns into deep submicron, the gate leakage current of the metal oxide semiconductor (MOS) transistor becomes larger and mismatch between devices becomes worsen. It is necessary to keep the neural amplifier robust in all process corners. Methods: The proposed circuit is a two-stage amplifier which can achieve a good trade-off between power consumption and noise. Four second-stage amplifiers share a common reference amplifier to reduce area and power consumption. A pseudo-resistor with high resistance is utilized to realize a very-low frequency high pass corner without external components. In order to minimize process variation, a bulk-compensated (BC) technique is adopted to maintain adequate tolerance in all corner case. Results: The 4-channel neural amplifier is designed and fabricated in a 40 nm standard complementary metal oxide semiconductor (CMOS) process. It achieves a mid-band gain of 54 dB, a bandwidth of 70 Hz to 7.7 kHz, a total input-referred noise of 3.2 μVrms , and a Noise Efficiency Factor (NEF) of 3.3 while consuming 4.68 µW from the 1.1 V supply. The core area of one channel is only 0.032 mm 2 . Conclusion: A 4-channel integrated neural recording amplifier chip with bias-compensated circuits is presented in this paper. Extensive simulations insure that the design is “center”. The chip layout is verified using design rules check (DRC) and layout versus schematic (LVS) design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without bulk-compensated circuit. This makes the design robust and uniquely appropriate for low-power implant application.


Background
With the development of information science and technology, there are more diverse research and treatment methods for modern medicine. Although we can now cure many diseases, and even edit genes, there still is a long way to understand the brain.
As the most important and complex part of the human body, the brain contains more than 100 billion neurons and more glial cells. Each neuron may form up to 10,000 synaptic connections with other neurons, which constitutes more than 1,000 trillion synaptic connections [1]. Such a sophisticated structure has brought great challenges to the interpretation of the pathogenesis of brain diseases.
The hippocampus is a part of the limbic system of the brain, located below the cerebral cortex, and is mainly responsible for spatial positioning and the formation of new long-term memories [2]. Damage to the hippocampus can lead to the loss of the ability to convert short-term memory into long-term memory, causing cognitive dysfunction and disorientation. Hippocampal system damage can result from cerebral hypoxia, encephalitis or epilepsy. There is no known treatment for these debilitating cognitive deficits. According to the World Alzheimer Report 2020, there are currently estimated to be over 50 million people worldwide living with dementia. The number of people affected is set to rise to 152 million by 2050. A new case of dementia arises somewhere in the world every 3 seconds [3]. Since 1998, researchers have developed hundreds of drugs, but only 4 drugs have undergone clinical trials so far, and all ended in failure [4].
The dilemma of drug therapy motivates researchers to explore new treatments. With the development of technology, prosthesis and brain machine interface (BMI) have been applied in the treatment of various diseases [5]. Berger et al. outlined a plan for addressing this issue through the replacement of damaged tissue with microelectronics that mimics the functions of the original biological circuitry [6]. The microelectronic systems do not just electrically stimulate cells to generally heighten or lower their average firing rates. Instead, the prosthesis incorporates mathematical models and replicates the fine-tuned, spatio-temporal coding of information by the hippocampal memory system. Figure 1 shows the processing path and the major elements of the prosthetic device. The analog front-end, consisting of 16 micro-power low-noise amplifiers (LNA), 16 high-pass filters and 16 ADC. The digitized signals then are classified by 16 spike sorters [7] into spike-event channels, where events are represented by a single bit. Outputs are computed by a single multi-input multi-output (MIMO) model processor [8], which delivers up to 8 channels of output to a neural stimulator (NS) [9,10]. LNA, as the first module in the whole system, plays an extremely important role.

Results
The proposed 4-channel neural amplifier is fabricated in a 40 nm standard CMOS process. The layout of the neural amplifier is shown in Figure 2(a), and the dies photograph is shown in the left of Figure 2(b). A neural amplifier without BC circuit is presented for comparison, and its die photograph is shown in the right of Figure 2(b). The only difference between the dies of the two neural amplifiers is whether a BC circuit exists. Both two die area occupies 0.5 mm 2 , in which the core occupies 0.032 mm 2 . That means each channel only occupies 0.008 mm 2 . Performance summary and comparison are shown in Table 1. Here, "With BC" means the neural amplifier with bulk-compensated circuit, and "Without BC" means the neural amplifier without bulk-compensated circuit. The measurement results show that the high-pass cutoff frequency of the proposed neural amplifier is 70 Hz, and the low-pass cutoff frequency is 7.7 kHz. The right amplifier without BC circuit consumes 10.5 µA at 1.1 V power supply, and the input-referred noise is 3.6 µV rms when integrated in interested bandwidth, which leads to an NEF of 5.9. While the left amplifier with BC circuit consumes 4.25 µA at 1.1 V power supply, and the input-referred noise is 3.2 µV rms when integrated in interested bandwidth, leading to a NEF of 3.3. The neural amplifier with BC has lower power and better NEF than the amplifier without BC. With a BC circuit, the neural amplifier achieves lower power, lower noise, and robust in a deep submicron process.
The features discussed above are the best results in the measurements. We measured power consumption in 15 dies and compared the neural amplifier with and without BC. The total current of the dies is distributed among a certain range, as shown in Figure 3. The curve above shows current consumptions of amplifiers without BC circuit in 15 dies; while the curve below shows current consumptions of amplifiers with BC circuit in 15 dies. Power consumption reduced by approximately 60% using the BC circuit. Meanwhile, the current difference among 15 dies becomes small using BC circuit. Therefore, we can obtain a highly stable total current and low power consumption using a BC circuit, which is important for an analog design in deep submicron process.

Discussion
Different researchers have focused on different features in their design. For example, some studies have focused on the low power of the amplifier [11,12], some have pursued low noise [13,14,15], while others have paid more attention to the NEF [16,17,18,19], high input impedance [20,21], little distortion [22,23,24] and small area [25,26]. A tradeoff exists between power, noise and area and balancing these performances in design is important. When the process turns into deep submicron, the performance of the MOS transistor become worse. For example, the gate leakage current of the MOS transistor becomes larger, but the threshold voltage becomes slightly lesser, and the mismatch between devices could possibly worsen. Designing the front-end neural amplifier in deep submicron process becomes difficult due to the worse performances of the device and the harmful effects by process variation. This paper adopted a method to overcome process variation and presented a robust circuit in deep submicron process.

Conclusions
A 4-channel integrated neural recording amplifier chip with BC circuits is presented in this paper. Extensive simulations insure that the design is centered". The chip layout is verified using DRC and LVS design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without BC circuit. This makes the design robust in a deep submicron process and uniquely appropriate for low-power implant application.

Methods
This section discusses important specifications of the neural recording amplifier and the detailed circuits implementation of it.

Specifications
Typical neural action potentials, or spikes, have amplitudes up to 500 µV when recorded extracellularly, with energy in the 100-Hz-7-kHz band, while low-frequency local field potentials (LFPs) have amplitudes as high as 5 mV and may contain signal energy below 1 Hz [27]. In the hippocampal prosthesis, spike signals are mainly concerned, and thus the bandwidth of the LNA is designed as 100-Hz-7-kHz and the gain of the neural amplifier is designed as 54 dB. Considering the neural amplifier will be implanted in the brain, it must dissipate little power and occupy little area; thus a maximum power dissipation less than 15 µW and core area less than 0.1 mm 2 per channel is required.

Circuits implementation
System architecture As shown in Figure 4, each channel is composed of two amplifiers in cascade. The first stage is an open-loop pseudo differential amplifier which consists of two identical single-input-single-output amplifier. Its gain is 34 dB. The second stage is a closedloop fully differential amplifier. Its gain is 20 dB. The noise figure (NF) of the whole circuit is shown in Eq. 1.
Here, N F 1 is the noise figure of the first stage amplifier, N F 2 is the noise figure of the second stage amplifier, and G 1 is the gain of first stage amplifier. It can be seen that the greater the gain of the first stage, the smaller the system noise for the case of noise of the two stages is constant. Therefore, the gain of the first stage is designed to be large enough to achieve low noise in this design. In the architecture of the proposed 4-channel neural amplifier, first stage of each channel shares a reference amplifier as common input. Compared with simple combination of four single channel neural amplifiers, three single-input-single-output amplifiers are reduced; thus, 35% power consumption is reduced because the first stage amplifier consumes most of power.

Pseudo-resistor
A MOS-bipolar pseudo-resistor (PR) with high resistance and on-chip capacitors are employed to reject the large dc offsets generated at the electrode-tissue interface. The resistance of the pseudo-resistor is extremely high (>100 GΩ). More and more studies have adopted the pseudo-resistor in their designs since Harrizon proposed this concept in [28]. Figure 5 shows the structure of diode-connected positive channel Metal Oxide Semiconductor (PMOS) device. The PMOS works as a parasitic PNP transistor with the collector and the base connected. Thus, the current and conductance across PR can be described as follows.
Here, V BE refers to the base-emitter voltage difference of parasitic PNP transistor, and I S means the reverse saturation current. V t is the thermal voltage, n is the subthreshold slope factor, and I is the current across PR. The relationship between the resistance of PR and the current across PR can be written as, When turning into deep submicron technology, the supply voltage decreases while the threshold voltage of an MOS device is almost constant; thus the gate leakage current of the PMOS device increases. Based on the above analysis, when the gate of the PMOS device connects with one end of the pseudo-resistor, a larger leakage current of about a few picoamperes exists in the deep submicron process. Thus, the voltage difference between the two ends of the pseudo-resistor becomes larger in the order of a few decade millivolts.

The first-stage amplifier
In the design of the first stage, transistors M 1 -M 4 work as a cascode class C inverter [29], and the gain of the amplifier is decided by the ratio of capacitance C 1 and C 2 as shown in Figure 6. Given that the current of normal class C inverter cannot be controlled easily, transistor M 5 and connected devices (not shown in Figure 6) are added to provide a reference bias for M 1 . Transistor M 1 and M 2 work in the subthreshold region (weak inversion) to maximize the ratio of g m /I D while transistor M 3 and M 4 work in the strong inversion [30]. For the transistor working in the sub-threshold region, transconductance is shown in Eq. 5.
Here κ refers to the reciprocal of the subthreshold slope factor n in Eq. 2. The total input noise is given in Eq. 6, which indicates noise contributions of different devices. The first part is contributed by transistors M 1 -M 4 , and the second part is the contribution of PR 2 , with its noise decreased by a lowpass path composed of C 2 and PR 2 . The last part is contributed by PR 1 and transistor M 5 , which is decreased by another lowpass path composed of C 2 and PR 1 . Eq. 6 does not show the contribution of the flick noise of an MOS transistor. The flick noise of the MOS transistor can be neglected when the size of the transistor is large enough. The resistance of pseudo-resistors PR 1 and PR 2 are both high. Thus, the last two parts of Eq. 6 can be neglected. With the assumption of C 1 C 2 and g m3,4 g m1,2 , Eq.
6 can be simplified as, This design minimizes the noise of the first amplifier by obtaining a large transconductance g m of transistors M 1 and M 2 . Transistors M 1 and M 2 work in a subthreshold region to maximize g m in the same current I D .
The second-stage amplifier Figure 7 shows a fully differential amplifier, and Figure 8 is the structure of the operational transconductance amplifier (OTA) used in the second stage. Similar to the first stage, the gain of second stage amplifier is decided by the ratio of capacitance C 1 and C 2 . The common voltage V cm is decided by the pseudo-resistor that consists of M 11 and M 12 , and the resistance of it is far less than PR 1 -PR 2 in Figure 6. Given that a simple OTA is used, the second stage has considerable noise. However, it can be neglected because of the large gain of the first stage. The second stage must consume power less than 1 µW to meet the low power design target.

Bulk-compensated circuits
More unfavorable factors appear in the deep submicron process. As mentioned above, a voltage difference between two ends of pseudo-resistor PR 2 is about a few decade microvolts. By adopting a BC circuit proposed by Hao [31], as shown in Figure 9, the bulk voltage of M 5 is decreased; thus, its threshold voltage is decreased. Because the current across M 5 is constant, the gate voltage of M 5 increases to offset the difference voltage between the two ends of PR 2 . Meanwhile, the current across M 1 -M 4 is designed to be sufficiently low in the deep submicron process. As shown in Figure 9, the BC circuit that consists of M 10 -M 13 is designed to help transistor M 5 resisting process variation with negative feedback. The threshold voltage of transistor M 5 can be described as Here, V T H0 is the threshold voltage when V BS =0, γ is the body-effect coefficient, Φ F is Fermi potential and the V BS is the bulk-source potential difference. When the threshold voltage of M 5 decreases due to process varieties, transistor M 11 , as a sensor transistor, also decreases in threshold voltage. Thus, the current I 1 increases, and I 2 also increases because of the current mirror that consists of M 12 and M 13 . The bulk voltage of M 5 (V bulk ) decreases, and thus the threshold voltage of M 5 increases. When the threshold voltage of M 5 decreases or increases because of the process varieties, the bulk voltage of M 5 will be changed by the negative feedback path that consists of M 10 -M 13 to lessen the impact of threshold voltage variation. Thus, transistor M 5 can provide a highly stable bias current for transistors M 1 -M 4 in a deep submicron process. Figure 1 Block diagram of the hippocampal congnitive prosthesis