A Novel Hardmask-to-Substrate Pattern Transfer Method for Creating 3D, Multi-level, Hierarchical, High aspect-ratio Structures for Applications in Microfluidics and Cooling Technologies

doi:10.21203/rs.3.rs-1463619/v1

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A Novel Hardmask-to-Substrate Pattern Transfer Method for Creating 3D, Multi-level, Hierarchical, High aspect-ratio Structures for Applications in Microfluidics and Cooling Technologies

https://doi.org/10.21203/rs.3.rs-1463619/v1

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This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces (already etched wafers) to create more than one level to give rise to multi-level, 3D, hierarchical structures in the substrate. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate, which is first 3D patterned via multiple rounds of lithography. Then, this 3D pattern is scaled vertically by a factor of 200 – 300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable. Using features of different topographies and dimensions, the etch rates and selectivities were quantified, these characterization information were later used while fabricating specific target structure. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography, chip stacking and double-sided etching. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods – this makes the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.

Advances in lithography based micro-nano processing techniques have revolutionized the technology around the world for its ability to cost effectively mass produce structures ranging from sub-10 nm lengthscale all the way up to millimeter scale. Some of these structures include nanometer scale electronics components like FETs, IGBTs [1], sub-micron features like optical waveguides [2], Fresnel lenses [3], photonic devices [4], and micro-nanofluidic devices for DNA manipulation [5]. Slightly larger micro (1–100 µm) and meso (0.1–1 mm) scale features are even more useful in modern technology and has seen myriads of applications in microfluidics [6], cooling technologies [7, 8], battery research [9], sorption-desorption [10], desalination [11] and catalysis [12]. Although ubiquitous, versatile and indispensable as a micro-nano manufacturing technique, conventional cleanroom-based lithography suffers from one major limitation – it is unable to reliably create multi-level, hybrid, 3D hierarchical structures (structures with more than two levels of height or depth as shown in Fig. 1 (b, c)) of depths more than 1–2 µm. Conventional cleanroom processing can efficiently create only 2.5D or single-level structures (Fig. 1 (a)) but not true 3D multi-level ones (Fig. 1 (b, c)). Through conventional LELE (Litho-Etch Litho-Etch) route, a 2D design/pattern (full control available over the design in 2D) is first laid on a sacrificial mask layer deposited on the wafer using photolithography techniques. This mask is now used to cut/etch (or extrude if material is deposited/grown) that design onto the wafer. Through one round of (lithography + etching) the entire design can be etched to only one specific depth (different parts of the design cannot be etched to different depths). Conventional LELE cleanroom processes flows would normally require multiple rounds of (lithography + etching) to achieve the desired multi-level structures. The bottleneck arises due to unsatisfactory second round of lithography on wafers which have already gone through one round of (lithography + etching) and thus has etched features (~ 5 µm or more) in them. This comes as a major manufacturing hurdle in a time when hybrid surfaces hold the key to dramatic improvements in the performance of existing state-of-the-art devices.

Multi-level, 3D structures can be made with ease from soft materials like PDMS (polydimethylsiloxane), thermoplastics using deforming techniques (two-step soft lithography [36], sequential thermal [37] and UV [38] Nano Imprint Lithography (NIL), Capillary Force Lithography [39], Nano Transfer Printing (NTP) [40]) although reliable methods for fabrication of 3D multi-level structures in rigid material like silicon is still lacking [35]. Recently, two-photon lithography have enabled us to make complicated fully 3D patterns in photopolymers [41, 42], but these systems have an extremely small print volume (< 300 x 300 x 300 µm³ in the Nanoscribe GT, a state-of-the-art multi-photon system used in academia and industry) with equally long write times of more than 12 hours per structure. These reasons make two-photon lithography prohibitively expensive to use and difficult to integrate in commercial mass manufacturing scenarios [42, 43, 44]. Another technique called grayscale lithography (35–56) has gained some traction, which involves multiple steps of precisely controlled partial exposure (grey dose) of the photoresist to create a 3D multi-level structure, although, this method is often expensive, tedious, difficult to characterize. [] Waites et al. discussed the lack of standardization of grayscale lithography process steps because of severely limited control over several parameters that is inherently associated with gray-litho [47]. Some of these challenges encountered in grayscale lithography are complicated and expensive mask modelling, dose dependent dimension distortion, feature size dependent shifting of characteristic response curve of photoresists, profile welling and sidewall tapering at gray doses, all of which make the target resist profile difficult to achieve [44]. Waites et al. further states that making accurately controlled gray features is so heavily dependent on process conditions and operate within such tight tolerances that transferring recipe or process knowledge from one lab to another is almost impossible.

Recently, an ingenious double-sided processing technique (also demonstrated in Fig. 1 (d)) has been developed by Hazra et al. to create extremely high aspect ratio microchannel (~ 100 µm width) 2-level manifold structures [58, 62]. Although this method is not suitable for creation for all kinds of structures (Fig. 1 (c), (f)) since these 2-level structures are made via intersection of two designs etched from both sides of the wafer. Furthermore, the yield of 3D structures made via conventional or double-sided micro-lithography techniques on rigid Si wafers, drop drastically to about 50% because of manual handling of fragile wafers which have already gone through a round of deep Si etch. [57, 58]. Commercially, the creation of taller (> 50 µm) multi-level structures have traditionally been performed via chip stacking methods [24, 62]. In this approach, a fully 3D design is split into several different 2.5D structures, these 2.5D structures are fabricated in separate wafers using conventional lithography which are then stacked together using solder die-attach or thin eutectic bonding technologies. The wafer thicknesses determine the step heights achievable through this process and often to achieve small step heights, the wafers need to be thinned down using a back-grinding tool. Wafer thinning is also not possible below 30–50 µm which puts quite a large limitation on the minimum step height that is achievable through this process. Moreover, extremely thin wafers are prone to warping, chipping and breakage. The final bonded chip-stacked configurations are short-lived and unreliable, the bonding sites being the primary source of failure in devices that go through massive cyclical thermal or mechanical stresses [59, 60], especially, microfluidic cooling devices. Additionally, chip stacking techniques have their limitations in terms of the device configurations it can fabricate, since the middle wafer layers of the stack cannot have free standing structures (for e.g., multi-level pin fin array structures cannot be made using this technique). Thus, current microfabrication community is in desperate need of a standardized, easily characterized process to make high aspect ratio, tall (> 100 µm) micro-mesoscale multi-level structures that is cost-effective, uses commonly used microfabrication processes, can operate between reasonable process and tool tolerances, and thus can be translated easily from one lab to another.

In this paper, a novel Silicon Oxide to Silicon pattern transfer process is described to reliably create multi-level structures using photolithography techniques in order to solve several of the practical challenges that arise while employing existing state-of-the-art methods like chip stacking, double side processing and grayscale lithography. The pattern transfer process is achieved through a single shot deep silicon etching steps which translates into an improvement in manufacturing yield by more than 40%. Furthermore, Si : SiO₂ etch selectivity is more than an order of magnitude higher compared to Si:Photoresist etch selectivities [49–55], the use of Silicon dioxide as a sacrificial layer during this pattern transfer process, enables us to create really tall structures (up to 500 µm) the likes of which will be immensely useful in applications that rely on mesoscale structures and features. The process described is easy to standardize and thus, eliminates difficult characterization associated with grayscale lithography. Coupled with easy characterization, the process also employs very commonly used cleanroom-based tools and functions to create multi-level microstructure – this makes knowledge transfer from one lab to another much easier. This letter additionally details a one-shot characterization method and data of SiO₂ and Si etch specific to the tools and step conditions used. Finally, this letter shows SEM images of several 2-level and 3-level microstructure that were fabricated using 3D patterned SiO₂ hard-mask obtained via two rounds of lithography and etch, although the possibilities are endless. Finally, this letter ends by listing a few exciting structures whose fabrication is now made possible, and which could pave the way for the next generation of high-performance microfluidics and cooling devices.

The novel process described in this paper draws inspiration from multi-lithography techniques and grayscale lithography. It cleverly combines the two to solve several practical challenges associated with Photoresist based grayscale lithography technique for reliable fabrication of multi-level 3D structures. In conventional lithography, creation of etched features usually follows these steps delineated in Fig. 1 (h, i, j) – a) Coating Photoresist (PR) on the wafer; b) Exposing 2D design on the PR and developing the design and c) Deep Si etch to define the features. To achieve multi-depth structures using this conventional LELE (litho-etch-litho-etch) technique, where different parts of the wafer need to have different etch depths, the sequence of steps (a, b and c) needs to be repeated multiple times with a different exposure design in step b, and different etch time in step c. The primary challenge arises in the photoresist spinning step (a) itself when PR is attempted to be spun on the wafer with features already etched in them. The spinning process works via PR being puddle dispensed at the center of a Silicon wafer spinning at a high RPM, making it spread radially outward to create a thin (1 µm to 10 µm depending on PR viscosity and spin RPM), uniform and conformal coating over the wafer. The second step spinning process is satisfactory (thin and uniform) when the PR thickness (1–10 µm) is much larger compared to the etch height of the features. Thus, in cases (some cases of IC fabrication) where the already etched feature height is < = 1 µm, the LELE process works perfectly, but in several applications of microfluidics, liquid cooling, optics and semiconductor fabrication, these etch depths can range anywhere from 1 µm to 500–600 µm. PR spinning on such large step heights lead to unsatisfactory coating in step a (Fig. 1 (k)). Several problems like streaking (PR layer being wrinkled after hitting an etched feature), fingering (PR getting trapped in a deep cavity/channel and progressing along those channels only), and incomplete coverage (PR hitting the corner of an etched feature and failing to cover the rest of the wafer) mar the spin coating process in step a – thereby leading to failure of the whole process.

In this context, we have invented a novel process flow using commonly used cleanroom tools which mitigates all these problems and enables us to create multi-level hierarchical structures with ease. Inspired by grayscale lithography’s idea of 3D patterning the photoresist, we have first introduced an additional ultra-thin SiO₂ layer (< 3 µm) in between the PR and the Silicon wafer. The idea is to perform multiple rounds of conventional LELE lithography and SiO₂ etch to pattern this newly introduced SiO₂ mask layer, instead of attempting to pattern the Silicon directly. After this, by deep Si etching, this 3D multi-level pattern in the SiO₂ gets scaled vertically and transferred to the Silicon. In this new process flow (Fig. 2) the steps are as follows – i) Deposit Silicon Oxide hard-mask on the wafer; ii) Spin coat PR on the SiO₂ (same as step (a)); iii) Expose 2D design on the PR using appropriate UV light source and develop the exposed zone away (same as step (b)); iv) SiO₂ etch to desired height followed by stripping the remaining PR. Multiple rounds of step (ii, iii and iv) (lithography + SiO₂ etch) are performed on the wafer to create a hierarchical multi-level structure in the SiO₂ layer itself. In this situation, the most crucial step (step a or step ii) of spinning the PR on the SiO₂ coated wafer works perfectly since the PR coat (4 µm) is much thicker than the step heights (1–3 µm) in the SiO2 layer. These multiple litho rounds enable creation of a multi-level, 3D, structure in the SiO₂ hard-mask layer. The final step (v) single shot Deep Si etch enables us to translate the 3D structure that was created in the SiO₂ by scaling it vertically and transferring it to the Silicon layer underneath. The scaling ratio is the etch selectivity or ratio of etch rate of Si to etch rate of the mask layer, SiO₂ obtained using specific etching tools or recipes. Additionally, SiO₂ is much superior to hardened PR as an etch stop mask layer providing Si : SiO₂ selectivity of 200–300 during deep Si etch using the Bosch process (for comparison, same etching recipe provides a maximum Si : PR selectivity of 80–100), which enables us to create structures as tall as 400–500 µm. The specific process flow employed in this study can be found in the Supplementary Information.

Processes like lithography (step a, b, ii, iii), SiO₂ deposition or growth on Si wafer (step i), SiO₂ etch (step iv) and DRI Etch of Silicon (step v) are very commonly employed in the cleanroom microfabrication community, thus making it easy to characterize (using a simple mask with varying feature dimension) and standardize for general use. Preliminary tests have demonstrated the ability to create 3D hierarchical features of nominal dimensions (width) ~ 5–10 µm with aspect ratios (height/width) as large as 10–15. The resolution can be further improved by using e-beam lithography instead of conventional lithography.

The process flow of creating multi-level structures has been tested 3 times with different orders of step heights (250 nm through 900 nm) to establish reliability and repeatability. Moreover, this process employs only a single step of deep Si etch, thus making it much less expensive and time consuming as compared to the conventional lithography route which employs multiple rounds of deep Si etch (number of levels required in the structure = number of deep Si etch steps). This will increase throughput while simultaneously reducing cost per device when used in an industrial mass production scenario.

The proposed concept of fabrication, which involves multi-lithographically patterning a thin masking layer and then transferring that pattern to an underlying substrate through etching can be extended to other mask material and substrates as well. Instead of CVD Silicon dioxide, thin metal layers (Au, Pt, Cr, W, Al) or other oxide materials (Alumina) can also be used as the mask layer. Superior etch selectivity of 10⁵ has been observed during DRIE of Silicon with an Al mask layer [61] – thus combining this with our method will enable the creation of extreme aspect ratio (> 35) multi-level structures. These new masking materials can also be deposited or grown on our wafer through other techniques like evaporation, sputtering, ALD or electroplating. Similar to our current process, a single characterization run will be required to quantify the etch rates and selectivities specific to the tools and process conditions used – these parameters will then be used to design the process flow for obtaining our final target multi-level structures.

The resolution and repeatability of the process depends on our ability to precisely characterize the etch rate of Silicon, etch selectivity between Si and SiO₂ during DRI etching in the PTDSE and the etch rate of Silicon dioxide in the Oxford RIE. Three different characterization wafers with several designs of straight microchannels and square pillar arrays were used on three different days. They were etched for varying durations using a 600–800W plasma of CHF₃ and CH₄ in a 3:1 ratio in the Oxford RIE. The findings are summarized in Fig. 3.

Following detailed characterization of the oxide etch rate using our specific recipe, we can precisely construct 3D structures in Silicon oxide. The target structures for our extreme heat flux cooling devices are extremely tall (~ 500 µm) needing 3–4 µm SiO₂ layer as the mask. We have chosen an aggressive oxide etch recipe with good PR: SiO₂ selectivity of > 1. This is necessary in order to be able to etch the thick SiO₂ layers (up to 4–6 µm) using relatively thinner PR layer (4 µm, thus maintaining sub-10 micron resolution). Although, the drawback of choosing an aggressive etch recipe leads to increase in vertical resolution of our target structures. As seen in Fig. 3, which plots the etch per second (Å/s) as a function of the total etch time and feature dimension, the average etch rate was well controlled within 45 and 54 Å/s for a wide range of target structures and for all etch durations above 1 seconds (at 1 second, the etching is severely starved of plasma and etch rate is much lower, ~ 30 Å/s) Thus, the vertical resolution of the 3D structures using our etching recipe is limited around 10 nm (obtained through a 2 sec etch) in the SiO₂, which translates to around 2–3 µm when the step is scaled and transferred to the Silicon wafer through DRIE. The etching recipe can be tuned (flow rates of respective gases can be reduced, CHF₃ and CH₄ ratio could be decreased) to make it less aggressive, and thus reduce the etch per second value – this will lead to better control of the etch, and sub 10-nm resolution in the SiO₂ 3D structure (and sub-micron level vertical resolution in the final Silicon structure). Following characterization of the oxide etching step, the Deep Silicon etching recipe used in the PTDSE for pattern transfer was then estimated using a test wafer and straight channel dimensions of 100–200 µm. The average etch selectivity over 200 µm of etch was found to be around 270–275. This etching recipe was developed extensively by a previous work by Hazra et al. who reported etch selectivity of 220–240, and etch rate of 8 µm/min. [58] The DSE recipe used by Hazra et al. [58] was also extremely aggressive in order to accommodate their extreme total etch height of 1000 µm, although this aggressive recipe leads to a reduced Si : SiO₂ selectivity. In our present study, the recipe was slightly modified (etchA time was reduced to 3.1 sec from 3.3 [58]) to increase selectivity and attain straighter, more anisotropic etch profile. The progression of etch for our characterization structures (perpendicularly placed straight channels arrays of different widths and spacings between 100 and 400 µm) were investigated. 172 µm of Silicon was found to be etched for 0.61 µm of oxide, thus making the average Si : SiO₂ etch selectivity ~ 282.

Different types of multi-level features with varying feature widths and heights and topographies are presented in Fig. 4.

Usually, the number of (lithography + SiO₂ etch) steps is equal to the number of levels required in the multi-level structure (observe Fig. 2 (1)–(9)), although it was soon realized that further simplifications could be made easily to reduce the number of processing steps required for these structures. For example, the final step height in the SiO₂ layer could be entirely replaced with a baked Photopolymer, thus reducing one round of (litho + SiO₂ etch). Although this would require designing the fabrication flow while accounting for the different etch rates and selectivities of PR, SiO₂ and Si during the process. In addition to these simplifications, mask designs themselves can be cleverly combined and overlapped between different rounds of (litho + SiO₂ etch) which gives rise to more levels using lesser number of rounds of (litho + etch). An example has been demonstrated in Fig. 5, where two rounds of (litho + etch) involving 2 masks could generate a 3-level structure. More such structures are seen in Fig. 4 (g, i, j, l, m) all of which are made by overlapping 2 masks (the exact mask designs are left as exercises for the reader). Figure 5 also briefly discusses an issue that might arise during the design exposure phase of lithography while making extremely tall structures. The dimensional accuracy and exposure quality by the MLA Heidelberg Maskless aligner depends on two main parameters – the exposing light energy (dose) and the location of focus (defocus) with respect to the PR top surface, although the exposing energy is the primary determinant. It has been observed previously that a ± 1 µm change in the defocus value from the optimal does not affect the exposure step significantly – this suggests that if the 3D features and step heights in the SiO₂ is low enough (sub-micron), exposure quality is relatively unaffected. Overlapping designs were tested for step heights from 0.5 µm to 1 µm and exposures were found to be satisfactory on both the levels (Fig. 5a – c). When photolithography is attempted on SiO₂ step heights which are more than 1.5 µm apart, the exposure qualities on the two different levels of the SiO₂ might be slightly different (as shown in the schematic in Fig. 5d – e, one of the levels might be over or underexposed) and this should be taken into consideration during the exposure step. One easy and quick fix is to not alter the defocus value (indicating that the lower level might be under-exposed and residual PR might be left behind), but increase the downstream descumming step duration to 2 mins or more. The extra O₂ plasma step removes all the residual PR from both the SiO₂ step surfaces.

The novel method has been extensively compared with existing methods in Table 1.

Table 1

Detailed comparison between existing state-of-the-art fabrication methods with SiO2-Si pattern transfer process
	1. Chip Stacking	2. Double Sided Processing	3. Grayscale Lithography (Photoresist – Si substrate)		4. Novel SiO₂-Si pattern transfer (PR – SiO₂ – Si)
	1. Chip Stacking	2. Double Sided Processing	A. Optical Mask Assisted	B. Maskless Direct Write	4. Novel SiO₂-Si pattern transfer (PR – SiO₂ – Si)
Brief Description	Produces multi-level 3D structures by breaking them in multiple 2.5D structures – current commercial go-to (Fig. 1 (e), (g))	Double sided etching to make 2-level structures out of 1 wafer instead of 2 that would be needed by conventional chip stacking (Fig. 1 (d))	Relies on accurately designed micro-nano scale patterns in the gray zone of an optical photomask, which partially blocks the full exposure dose to achieve a gray dose and partial development of the PR. 3D pattern on the PR is transferred to Si through DRIE etch.	Instead of an optical photomask, this process depends on the exposure tool’s capability to directly modulate exposure energy between different parts of the design to achieve varying amounts of PR washed away from these zones during development.	Multiple rounds of (maskless direct write full exposure photolithography + SiO₂ etch) is performed to make a 3D pattern on a thin SiO₂ layer on top of the Si. Compared to grayscale lithography, an additional SiO₂ layer is introduced between the PR and Si substrate, which will now act as the etch stop layer during DRIE etch.
Lithography Mask	Optional. Both masked methods or maskless methods can be used for full exposure lithography.		YES, requires a physical optical photomask • Very expensive to fabricate [49–55] • Designing step requires multi-objective complex modelling to determine gray zone pattern dimensions – tedious [44] • Designing mistakes are costly – leads to wastage of processing time and money	NO, does not require a physical mask • Digital mask increased room for error during design • No wastage of time and money associated with physical Chrome-on-glass mask fabrication	NO, does not require a physical mask Although, our process involves full exposure lithography only, thus maskless litho can be replaced by multiple masked lithography for mass manufacturing scenarios (note, this is easy since no gray litho masks are involved)
Etch stop layer	Usually PR	PR or SiO₂	Photoresist (can be up to 5µm thick)	Photoresist (thin, usually < 2 µm)	Ultra-thin (up to 3–4 µm) SiO₂ layer
Etch Selectivity	Up to 100	180–240	Up to 100 for specific design and RIE recipe	Demonstrated up to 30	200–280
Total feature height demonstrated	Wafers in the middle of the stack can NOT have free standing structures. Eg. A micro-pillar array with different heights cannot be made using this method since pillars are free standing features.	Since double sided etching is needed, one of the levels must be the wafer backside (through etched) – this severely limits the type of structures that can be made	Up to 250 µm [46]	• Low height, 10 µm based on > 10 published research [49–55] • Eckstein et al. [53] developed a special illumination tool to achieve 75 µm tall structures • Heidelberg instruments, a premier maskless tool manufacturer reports an upper height limit of 60 µm [44, 53]	• No restrictions on structure type like in Chip stacking or double sided processing. • Capability more than 500–600 µm (demonstrated up to 350 µm) The use of high etch selectivity SiO₂ as the intermediate layer solves the issue of low feature heights. Using 3 µm of SiO₂ potentially enables us to create > 600 µm tall structures.
Feature lateral dimensions	Sub-10 µm resolution	Limited by aspect ratio achievable through DRIE	~ 10 µm or much more than the pixel dimension (1–2 µm) in gray zones.	Sub 10-µm resolution	Sub 10-µm resolution
Number of gray-levels (Maximum number of levels in the structure that can be made in the multi-level structure)	$n$ gray levels require $n$ wafers carefully ground to specified level heights	2 level only (1 level has to be through etched)	Limited by the mask fabrication capability, stepper resolution, upper dose level without pixel recreation	Limited by stepper resolution, PR response curve	No limit (number of lithography step which can be as few or as many = number of levels)
Etch stop layer profile control			Most issues regarding etch stop profile arises during the gray level exposure step
Etch stop layer profile control	Standard	Standard	Very difficult even with a perfectly difficult mask [44, 48] • Rough PR surface after partial development • Gray zone profile tapering, “well”-ing • Higher dose unwanted pattern recreation	Very difficult [52] • Gray zone profile tapering, “well”-ing • messy PR surface after partial exposure and development • High post etch surface roughness	Standard – Our process eliminates all gray exposure steps. Full exposure multiple round photolithography is used to 3D pattern the SiO₂ layer with the steps being perfectly vertical anisotropic (SiO₂ wall profile angle can be changed too by tuning oxide etch recipe)
Etch stop profile correction	Standard	Standard	Difficult – Expensive (physical mask) and time-consuming (mask making lead time)	Two methods which are both expensive and cumbersome [44] – • Through thorough characterization – tedious • 3D proximity effect correction (PEC) – expensive	Profile correction only involves characterizing oxide etch rate as a function of feature dimension which can be easily done using a simple characterization mask
Characterization Step	Difficulty of the etch stop layer profile control and correction directly correlates with the difficulty of the characterization step
Characterization Step	Only etch needs to be characterized Extremely low yield (50–60%) since it requires handling of fragile wafers with deep etches [57, 58]		Extremely difficult characterization step [49–55] – • Difficult profile control and correction • Each design requires extensive, individual, characterization • involves making a detailed dependence map from pattern dimension ◊ reduced light intensity ◊ PR height – this is difficult and cumbersome especially with physical masks • Dimensional inaccuracies by gray zone profile distortion	Extremely difficult characterization step [44, 49–55] – • Difficult profile control and correction • Each design requires extensive, individual, characterization • Feature dimension dependent PR response curve shifting • Dimensional inaccuracies in gray exposure regions • Almost impossible to correct profile distortion issues (e.g. Profile “well”-ing) that arise due to gray level exposure	Standard, only etching needs to be characterized – • Easy profile control and correction • Individual Characterization step NOT required for each design • Full exposure photolithography eliminates all the issues regarding profile distortion and dimensional inaccuracies • For each lab (set of tools), one etching run using a characterization mask is sufficient to quantify Si, SiO₂ etch rates and selectivities. These data can then to be used to design masks for the final target structure.
Standardizability	High level of failure at bond sites during stress cycling [59, 60]	Wafer breakage during handling [57, 58]	Difficult because of gray profile distortion issues	Difficult because of gray profile distortion issues	Easy (no gray exposure step). Single etch step replaces multiple ones thus eliminating any manual handling. Also, since the multi-level structure is made of one wafer no bonding required
Process tolerances		Tight	Tight (narrow window of process parameters)	Tight (narrow window of process parameters)	No tight process tolerance (easy to use tools and processes)
Knowledge transfer	Easy	Difficult	Difficult because of tight process tolerance	Difficult because of tight process tolerance	Easy, because of relatively simpler characterization and standardization steps.
Potential for commercial use	Commercially used	Usable	Difficult to use commercial because of poor process reliability, difficult characterization, tight process tolerance [49–55]	Difficult to use commercial because of poor process reliability, difficult characterization, tight process tolerance [44]	Easy since it is easy to characterize and standardize. This recipe also uses very commonly used tools and processes (SiO₂ CVD deposition, lithography, SiO₂ and Si etch) so easily integrable with existing cleanroom-based manufacturing lines
Process cost	$$$ (expensive)	$$$ (higher cost because of lower yield)	$$$$ (most of it coming from physical masks)	$ (process) $$ (profile correction, characterization, and distortion correction)	$$ (slightly additional cost compared to 3B, associated with multiple rounds of lithography and SiO₂ etch)

Impact

This novel approach delineated in the letter allows us to precisely create multi-level, hybrid structures through an easy to characterize and standardizable process flow. Additionally, this novel method can also be used to introduce well-ordered surface roughness elements at the base of the microstructure and can replace conventional methods of creating stochastic surface roughness elements (wires [32], tubes [31], needles [34], broccoli [33], polyp [29]) which are harder to control and repeat. The ability to create 3D, multifunctional and hierarchical structures is especially important to the academic and industrial research environment right now, since myriads of micro-meso scale applications can benefit in performance by merely replacing conventional single-level device structures into multi-functional and multi-level, hybrid features.

Hybrid structures have been used in optical waveguides [13], micro-lens array systems [14], solar cells [15], photonic crystals [16], IR sources, metamaterials, surface area enhancement for water absorption, desalination, Carbon capture, battery technology, catalysis [6–12]. Hybrid structures also form the working principle behind several bio-inspired designs with targeted functionality [17, 36] like superhydrophobicity of self-cleaning lotus leaf, antifouling and drag reducing textures of shark skin and mollusk shells, anti-reflective moth-eye, photonic band gaps in butterfly wings and superhydrophilicity or “water harvesting” capability of the micro-bumped Namib beetle skin [17]. Digital droplet microfluidics is hugely benefitted from hybrid structures, where structures with special surface enhancements can alter its wetting between the hydrophilic Wenzel and superhydrophic Cassie state [18, 31] Flow type microfluidic devices too are fully 3D multi-level hierarchical structures consisting of different types and sizes of features that have been etched to different depths in the substrate – microchannels for liquid flow (50–500 µm wide, 50–500 µm tall), inlet and outlet conduits (need to be etched through whole layer), and an active area (usually with much smaller feature dimension ~ 0.5–50 µm, which can consist of micro-pillar arrays for flow mixing [19], nanochannels ports and features for DNA manipulation [5], particle and cell sensing [20], sorting [21], separation [22] and analysis [23], contraction / expansion regions and jets for droplet generation) for device functionality. Moreover, hybrid structures probably have the most significant impact on improving the device performance in the field of microfluidic cooling. Hybridization of the Cold Plate side microchannel base (by introducing a microwick or surface features at the bottom of a straight microchannel) lead to increased thermal performance in forced fed microchannel cooling scenarios. [8] Zhu et al. reported heat transfer coefficient improvements from 17% to over 117% for microstructured microchannel compared to smooth microchannel, for 25 and 75 µm tall micropillars, respectively, using methanol as the working fluid without significant increase in pressure drop. [24] Passive heat spreaders like Heat Pipes and Vapor chambers with hybrid, bi-porous wicks instead of a conventional mono-porous one showed significant improvement in their heat spreading capabilities. [25] Dai et al. demonstrated that a complex hybrid wick when used in a heat pipe, leads to a massive 30 folds increase in maximum spreadable heat load as compared to solid Copper. [26] Zhou et al. validated the superior performance of hybrid two-level wicks in Vapor Chambers by reporting a 28% and 17% decrease respectively in device thermal resistance as compared to a state-of-the-art commercial monoporous and biporous wick TGP (Thermal Ground Plane) [27]. Moreover, our ability to reliably create multi-level hierarchical structures will allow us to aggressively scale up forced convection based active cooling device using a second 3D manifold layer for efficient fluid delivery. Pan et al. performed numerical simulations in ANSYS Fluent to compare Manifolded Coolers (MMC) design with Traditional 2D Coolers (TMC)s and showed that at same flow rates, the MMCs can achieve similar levels of thermal performance as the TMCs but achieve a massive 4x to 6x reduction in total device pressure and thus, 4x to 6x improvement in Coefficient of Performance (COP) [28]. Combining features of different dimensions and heights, within the same cold plate microstructure would also lead to increased device performance by increasing surface area and nucleation sites during single-phase and two-phase flow boiling respectively in forced feed microchannel coolers. Additionally, such hybrid wicks will also enable us to solve the mass transport limitations inherently imposed by thin evaporator wicks. In ultra-thin vapor chamber designs, the short pillars could be placed over the hot-spots to hold a very thin liquid film, leading to smaller thermal resistance and superior thermal performance and the tall pillars will act as liquid replenishment routes supplying enough wicking mass flow from the condenser back to the evaporator over large device areas. In addition to the above mentioned uses for multi-level structures, the active heat transfer 3D micro-featured surfaces themselves can be surface enhanced using this novel method. These surface enhancements lead to massive improvements in device metrics by enhancing the capillary wicking-based transport from the condenser back to the evaporator. This has been demonstrated by creating hybrid wicks using UV laser induced roughness [29, 33], hydrothermal ZnO Nanowire synthesis on silicon microstructure [24] and then performing capillary rate of rise tests and comparing with their non-hybrid smooth counterparts with no surface enhancements. Surface enhancements additionally increases the overall area available for heat transfer in forced fed convection and thin film evaporation scenarios [30], and leads to increased bubble nucleation sites in pool and flow boiling regimes. [7, 8, 32]

Some of the above mentioned applications help motivate the superiority of hybrid structures. Several orders of improvement will be achieved in many applications when conventional monoporous or single-level wicks are replaced by hybrid, multi-level wicks. We hope that this standardized recipe for manufacturing such multi-level structures will encourage more research, and eventually adoption of such structures in commercial devices and real life scenarios.

In this letter, we have detailed a novel Silicon Oxide (SiO₂) to Si pattern transfer process which uses multiple lithographically patterned thin SiO₂ layer to pattern the Si layer underneath. The extreme high etch selectivity between Si : SiO₂ etch of 200–300 enables us to create multi-level structures of extreme heights of > 500 µm in Silicon with a relatively thin (< 3) oxide layer on top. With the current oxide etch recipe selected, we obtain a stable resolution of 90–100 Å in SiO₂ for 2 secs of etch, this yields a vertical Si etch resolution of 2–3 µm in Si. With more tweaks to the etch recipe, the oxide etch per second can be reduced and resolution further refined. This process provides several advantages over conventional chip stacking, double-sided etching or grayscale lithography approaches, all of which have been summarized in detail in Table 1. The novel process has been used to create myriads of multi-level structures as shown in Fig. 4, furthermore, Fig. 5 shows how multiple lithography masks can be overlapped to create more levels using lesser number of litho masks. Such multi-level structures in the micro and mesoscale have far reaching applications in the fields of microfluidics, cooling technologies, biology, filtration, and energy as mentioned briefly in the introduction. Furthermore, our novel process solves several practical characterization and standardization challenges that mar the use of grayscale lithography to make multi-level hierarchical structures and thus arguably is more suited for commercial use. Difficult fabrication process is the primary reason behind multi-level, 3D structures not observed in commercial use. Having a standard recipe that can be easily translated from one lab to another will open a range of possibilities in research and development of such hybrid structures for the working devices and increase their performance by many folds.

Data Availability

All data generated or analyzed during this study are included in this published article and its Supplementary Information files.

Acknowledgement

This research was supported by funding from the Department of Energy’s Advanced Research Projects Agency-Energy’s (ARPA-E) OPEN 2018 funding opportunity. Several parts of the work were carried out in SNF (Stanford Nanofabrication Facility) and SNSF (Stanford Nano-Shared Facility). This work was authored in part by the Alliance for Sustainable Energy, LLC, the manager and operator of the National Renewable Energy Laboratory for the U.S. Department of Energy (DOE) under Contract No. DE-AC36-08GO28308. The views expressed in the article do not necessarily represent the views of the DOE or the U.S. Government. The U.S. Government retains and the publisher, by accepting the article for publication, acknowledges that the U.S. Government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this work, or allow others to do so, for U.S. Government purposes.

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A Novel Hardmask-to-Substrate Pattern Transfer Method for Creating 3D, Multi-level, Hierarchical, High aspect-ratio Structures for Applications in Microfluidics and Cooling Technologies

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