An accurate delay and power model is an inevitable component for a circuit simulator and logic synthesizer as it aids to evaluate the performance of the circuit. It is essential for the defining model to be simple, compact and accurate in order to characterize its design parameters. Hence, the number of attributes defined in the delay and power model should be less and not compromise on accuracy. The model parameters have to also independently match and connect to the device parameters for proper measurement. Using these as imperatives, this research attempts to define the creation of GDI library using a MUX based signal connectivity model and define the creation of the delay and power model for the proposed GDI library. This research utilizes a model developed for un-skewed and skewed gates in -single and multi-stage networks. It calculates the delay calculation for simple RC networks and multi-path combinational circuits. The power model is described using two components; the node activity factor and the power factor which is related to internal node capacitances, wiring and gate capacitances of the driving and receiving GDI nodes. The probability signal transition characteristics of all GDI cells are also termly described. The experimentation findings from this research, which meets the specifications of the sub-micron library supported for the SilTerra 130nm 6-metal layer fabricated for CMOS n-well process reveals that the proposed GDI library is indeed better and superior by the parameters of the delay-transistor and power utilization in relation to the PTL and CMOS technology. An overall 55 – 65% improvement is achieved for primitives when simulation is carried out in mentor graphics for the 130nm CMOS process. The proposed delay model also evidently proves that the logical effort of GDI cells is less in comparison to the CMOS technology. The node activity factor α0 →1 of the proposed GDI cells ranges from 0.1-0.2 whereas in CMOS it is 0.1-0.3.