Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

The leakage current is prime concern in the modern portable battery operated device. Therefore, various techniques using MOSFET and FinFET devices are presented and their performance is evaluated and compared. To further reduce the leakage current for improved battery backup in portable devices, new devices namely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. The subthreshold leakage power saving is observed in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25 °C) and high temperature (110 °C) with low and high input ranges. For high temperature & high input ranges, the simulation results show power saving from 89.65—97.86% and from 91.85—99.76% when compared with single chiral standard and LECTOR based domino circuits, respectively.


Introduction
Due to the scaling limit, conventional Complementary Metal Oxide Semiconductor (CMOS) and Fin-Field Effect transistors (FinFET) technology needs to be replaced with highly efficient Carbon Nano Tubes FETs (CNTFETs). The CNT-FET based domino logic circuits can show drastic improvement in power consumption due to ballistic transport phenomenon of charge carriers in CNTFET. This section first presents various characteristics of CNTs followed by the discussion on subthreshold leakage (SL) current in CNTFETs.

CNTs and its Characteristics
The CNTs are of two types based on their structures namely Single Walled CNT (SWCNT) and Multi Walled CNT (MWCNT). The SWCNT is constructed from one atom thick graphene sheet rolled in cylindrical tube. When graphene sheet is rolled across three different axes SWCNT can be classified as zigzag (n,0), armchair (n, n) and chiral (n, m) as shown in Fig. 1. Equation of three different axes known as chiral vector ( �� ⃗ C ) [1][2][3] is defined by Eq. (1) where n and m are integers, � ⃗ a 1 and � ⃗ a 2 are unit vectors. For dual chirality, different threshold voltages are achieved by varying CNT diameters. The diameter of CNT reduces when threshold voltage of CNTFET increases. The diameter [1][2][3] of a carbon nanotube is given by Eq. (2).
where a = 0.246 nm and n & m are chiral vector integers.

Subthreshold Leakage (SL) Current Characteristics
Figure 2(a) and (b) shows subthreshold current flow in n-type and p-type CNTFET transistors, respectively. In n-type CNTFET, when gate terminal is set to '0', the transistor moves in OFF state and ideally no current flows from source to drain. However, a very small current flows between them due to short channel effects (SCEs). This current is known as SL current. On the other hand, in p-type CNTFET, when gate terminal is set to high to move transistor in OFF state, the SL current flows from source to drain. The V-I characteristics of n-CNTFET and p-CNTFET is shown in Fig. 3(a) and Fig. 3(b), respectively. As shown in Fig. 3(a), in an n-CNTFET with high values of n (chiral vector integer), when source voltage increases subthreshold current increases rapidly but after a point, the slope of subthreshold current reduces rapidly with the change in source voltage. When chiral vector integer n reduces or in other words diameter of CNT reduces, subthreshold current also decreases. Further, reduction in chiral vector integer does not make remarkable difference in subthreshold current. As shown in Fig. 3(a), for n = 13 to n = 7 the magnitude of subthreshold current is almost same and fall on the same line.
As shown in Fig. 3(b), the subthreshold current increases gradually with source voltage in p-CNTFET. But in case of chiral vector integer n = 19 when source voltage increases beyond 0.8 V sudden breakdown occurs and large amount of subthreshold current flows. When CNT diameter reduces subthreshold current decreases by very small amount and cannot be distinguished, hence subthreshold current lines overlapped. Therefore, it is concluded that n = 13 or 11 are best suited values for SL reduction.
The paper is organized as follows. Section 2 provides literature review wherase Sect. 3 describes the proposed techniques. Results and discussion are given in Sect. 4. Finally, Sect. 5 concludes the paper.

Literature Review
The leakage current is prime concern for the design engineers and therefore significant attention is captured by the researchers across the globe. However, various reduction techniques are presented in the literature; the leakage is still high and motivated us to further work. This sections summarizes different work done to reduce leakage current. A lector stacking technique for gate oxide and SL current reduction is presented in [4] where p-and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down network of domino circuit. In this circuit, each LCT gate is controlled by source terminal signal of other transistor. In this technique, either n-type or p-type transistor operates near its cut-off region for any combination of inputs which leads to higher resistance between supply and ground thus reducing leakage current. Moreover, in inverter circuit a footed-diode transistor is inserted between n-type transistor and ground which offers more resistive path between supply and ground to suppress leakage current at the inverter. Kao et al. [5] show different dual threshold voltage technique which reduces total leakage power. In [5], a domino circuit simulated on three circuit variants: first all transistors with low threshold voltage, second all the transistors with high threshold voltage and third dual threshold voltage with three different modes evaluation, precharge and standby. The results found that low threshold voltage design is faster than high threshold voltage. Gupta et al. [6] enhance their previous work with dual threshold voltage technique and removed footed-diode transistor from inverter and analyzed in four different states CHIL (Clock high and inputs are low), CHIH (clock high and inputs are high), CLIL (clock low and inputs are low) and CLIH (clock low and inputs are high). It is shown that CHIH state is effective to suppress the leakage at low temperature and CHIL is ineffective. At high temperature CHIH is preferred for high fan-in and CLIL is preferred for low fan-in. Zhou et al. [7] show that for CMOS circuit, multi-threshold CMOS technology is an effective method to reduce subthreshold leakage power and satisfies requirements for design of low power and high performance designs. Garg et al. [8] proposes Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic gates with reduced leakage power and better noise performance. Asyaei [9] presented a new leakage tolerant domino circuit that provides higher noise immunity with lower power consumption and without significant delay increment for wide fan-in gates. Further in [10], a new charging scheme is presented that reduces power consumption of dynamic circuit where dynamic node discharges frequently and suitable for large fan-in gates. All these works are contributed for CMOS technology, further many circuits proposed in FinFET technology node. Moradi et al. [11] proposed several logic circuits using FinFET device which is useful for reducing total leakage power. Magraiya et al. [12,13] also presented circuits for reduction of SL power in FinFET domino circuits with the help of ONOFIC & ONOFIC pull-up approach and achieved SL reduction.
Further, some works are going on CNTFET devices are related to device level modification. According to Avshish Kumar et al. [14], single wall CNTFETs have clear advantage over MOSFETs particularly performance is improved related to on current with respect to dielectric constant and gate insulator thickness. Hence, thinner gate oxide and larger CNT improves the performance of CNTFETs. Further, Junctionless ballistic CNTFETs (JL-CNTFET) [15] is presented by Khalil Tamersit which mitigates ultra-scaling effects and enhances performance. Electrostatic doped Schottky barrier CNTFET (EDSBCNTFET) [16] is proposed by Amandeep Singh et al. for low power memory design by leakage power reduction and better stability. Another application of CNT-FET for designed a high speed and low power unbalanced ternary multiplier is in [17]. Further, a ternary SRAM cells is presented in [18] for high speed and less variation in static noise margin application. Then, another ternary SRAM cell design using 17 CNTFET transistors for energy efficient and read disturb free application is presented in [19]. It is observed from the above research work that the existing leakage reduction techniques with CMOS & FinFET devices are still not minimizing the leakage current efficiently. Further there is very less analysis done on the leakage current of circuits with CNTFETs. Therefore, this paper presents new dual chiral CNTFET based domino circuits and provides a critical analysis to minimize leakage current.

Proposed CNTFET Domino Circuits
To address the aforementioned leakage current problem in the recent devices, new dual chiral CNTFET based two different standard and LECTOR domino OR circuits are proposed. To differentiate high threshold transistors from low threshold transistors thickness of tube is reduced as shown in Fig. 4(b) and Fig. 6(b).

Standard Domino CNTFET OR Gate
A generalized circuit diagram for 2-inputs standard footerless domino OR gate as shown in Fig. 4(a) has same threshold voltage or single chiral tubes whereas circuit in Fig. 4(b) shows proposed dual chiral footerless domino CNTFET circuit. In dual chiral, carbon nanotube diameters of clock transistor CN1, keeper transistor CN2 and inverter transistor CN4 are varied by changing the chiral vector. Due to this, carbon nanotube diameter reduces and drain current flow in the transistor also reduces.
The working of a dual chiral CNTFET domino circuit is same as standard domino circuit: when clock is low (clk = L), the high threshold precharge transistor CN1 is ON which charges the dynamic node; this is called precharge phase. During this precharge phase, output node goes low and high threshold CN2 transistor turns ON, maintaining the dynamic node in high state. Output of domino logic is independent of the inputs applied in the evaluation transistors, whereas only the leakage current is depends on the input vectors applied. On the other hand, when the clk = H, transistor CN1 is OFF and CN2 depends on the output of the domino circuit; this is called evaluation phase. Charging of dynamic node will depend on the input vectors applied and according to output node condition which will be low or high. Flow of subthreshold current is shown in Fig. 5 using dashed arrow for low and high inputs. The next subsection presents the LECTOR based dual chiral CNTFET domino circuits to minimize the leakage.

LECTOR Domino CNTFET OR Gate
In this section, the LECTOR based 2-input domino OR CNTFET both for single and dual chiral vector are shown in Fig. 6(a) and (b), respectively. Earlier Gupta et al. [6] have presented the same logic for domino logic in CMOS technology for reduction of subthreshold and gate oxide leakage currents. But in case of CNTFET, the SL is the dominant parameter of the total leakage current, hence the focus of this work is to investigate and reproduce the same logic in case of CNTFET. In Fig. 6 [4]. The proposed dual chiral LEC-TOR domino gate operates similarly to proposed dual chiral standard footerless CNTFET domino gate. In the proposed circuit, when clock is low (clk = L), the dynamic node is charged through the high threshold transistor CN1 and low threshold transistor CN4. This charging is  independent of the input state of previous clock. Suppose the inputs are low before the clk = L, node N2 will be at low potential and low threshold transistor CN4 offers a very low resistance path for charging of the dynamic node. If inputs are high before clk = L, then node N2 potential is not sufficient to turn completely OFF the low potential transistor CN4 (operating near cut-off region). The resistance of CN4 will be less than its OFF resistance which allows charging of the dynamic node. This case is known as precharging phase and output is independent of inputs of the evaluation network, whereas only the leakage current is dependent. Now, when clk = H or circuit is in standby mode known as evaluation phase. In this phase, output depends on the inputs. If all the inputs are low, the dynamic node will not be discharged by the evaluation network and the output of the inverter will be low and it turns ON the high threshold transistor CN2, the voltage at node N1 will turn ON the high threshold transistor CN5. But the voltage induced at node N2 will not enough to cut-off the transistor CN4, which will operate near the cut-off region, offering a high resistance path between V dd and ground, thus reducing SL current. When all or any one the input is high, the dynamic node will be discharged through the evaluation network. The transistor CN2 will turn OFF the voltage at node N1 and will operate the transistor CN6 near its cut-off region (offering high resistance). The potential at node N2 will turn ON the transistor CN4. Therefore, the introduction of low threshold LCTs increases the resistance between V dd and ground in addition with propagation delay of the domino circuit. Flow of subthreshold current in dual chiral LECTOR based OR CNTFET for low and high inputs are shown in Fig. 7(a) and Fig. 7(b) respectively. These circuits reduce the leakage current significantly and can be effectively employed for low power designs. The next section presents the efficacy of the proposed work with simulation results.

Results and Discussion
To evaluate the performance of the proposed technique, zigzag (n,0) CNTFET based domino OR gates are designed for 2, 4, 8 and 16 inputs using single threshold voltage (single

Power Consumption and Delay Analysis
The active power consumption and delay of the CNTFET domino circuits at 25 °C is shown in Table 1 and Table 2, respectively. The result shows that the APC in the CNT-FET domino circuit is increased with number of inputs. For chiral vector integer n = 7, minimum APC is achieved when compared to other combinations of different chiral vectors. This is due to the fact that low chiral indices offer higher threshold voltages. Similarly, the delay is increased when chiral vector integer is varied from n = 19 to n = 7. Hence, we can see a trade-off between power and delay when the chiral indices vector of the CNTFET is varied. Power delay product (PDP) of the standard and LEC-TOR based domino logic for single and dual V t is shown in Table 3. It can be observed that the PDP is increased with the number of inputs and with the decreased chiral index vector for both standard and LECTOR based domino logic.

Subthreshold Leakage (SL) Power Consumption at Low Temperature (25 °C)
The SL power saving in proposed dual chiral standard footerless and LECTOR domino OR gates over the single chiral domino gates for both low and high inputs are shown in Table 4. The graphical representations of the same for low and high inputs are shown in Fig. 8 and Fig. 9 respectively. From Table 4, it is found that at low temperature for low inputs, dual chiral standard footerless CNTFET domino OR gates for chiral vector integer n = 19 & 15, SL power  Fig. 8(a). Also from Table 4 Fig. 8(b).
Similarly, for high input at low temperature, dual chiral standard footerless CNTFET domino OR gates for chiral vector integer n = 19 & 15, SL power saving is 90.66%; for n = 19 & 13 SL power saving is 95.23%; while, for n = 19 & 11, SL power saving is 95.10%; On the other hand, for n = 19 & 9 and n = 19 & 7, SL power saving is in both two cases is same 95.09%. From the results it is found for chiral integer vector n = 19 & 13 maximum SL power saving is achieved, as shown in Fig. 9(a).
Also from Table 4  the results it is found that for chiral integer vector n = 19 & 11 maximum SL power saving is achieved, as shown in Fig. 9(b).

SL Power Consumption at High Temperature (110 °C)
SL power saving in proposed dual chiral standard footerless and LECTOR domino OR gates in comparison with single chiral domino gates for both low and high inputs are shown in Table 5. The graphical representations of the same for low and high inputs are shown in Fig. 10 and Fig. 11 respectively. From Table 5 Fig. 10(a).
Also from Table 5  From the results it is found that for chiral integer vector n = 19 & 9 provides maximum SL power savings, as shown in Fig. 11(b).