Power Efficient Model of PWM Generator for Green Computing and Communication on High Performance FPGAs

: PWM generator is one of the core modules of a communication model. Its main function is to control the amplitude of signal and used for reducing average power of the pulses and signals. The PWM generator can also be used in promoting the green computing and green communication other than data and wireless communication if it is made power and energy efficient. In this work we are using different Stub Series Terminated Logic (SSTL) IO with three distinguished FPGAs of different Nano meter (nm) gate size that are 28 nm SPARTAN-7, 20 nm KINTEX-7 Ultra scale, and 16 nm ZYNQ Ultra scale+. The model has been synthesized and implemented on VIVADO ISE tool. From the power analysis it is observed that 16 nm ZYNQ Ultra scale+ requires the highest amount of power for operation with SSTL18_I IO and 28 nm SPARTAN-7 uses least amount of power for the operation with SSTL135 IO, while the 20 nm KINTEX-7 Ultra scale lies in mid of both of these devices.


Introduction
Pulses and signals are the building blocks of a communication module system. The telecommunication system uses PWM (Pulse Width Modulation) signal for its operation. These PWM signals are hence generated with the help of the PWM generator. In the communication system the signal is regarded as PWM signal when its width is changed accordingly with respect to the modulated signal [1]. The generation of PWM signal is represented in Fig. 1 and Fig. 2.  Fig. 1, the PWM waves are generated with the help of three building blocks such as modulator, comparator, and sawtooth generator and four types of signals that are message, carrier, PAM, and ramp [2]. At the first instance the message and carrier waves are modulated with the help of modulator. And in second phase the output of modulator i.e. PAM signal and sawtooth generator i.e. ramp is fed to the comparator. The resultant of the comparator is the PWM signal. The PWM generator reduces the average power of the communication module [3]. PWM uses a rectangular wave signal whose width is varied and the resultant is the reduced average power of the signal [4]. Let's consider the pulse as x (t), having time period of T, duty cycle D, low value y min and high value y max as shown in  Therefore the average reduced power of the waveform is sated as: T<t<T and y max is 0<t<D.T, hence the above equation can be realized as:  (Look up  Tables), 46 FF, 4 IO, and 1 BUFG; whereas there are 48000 LUTs, 96000 FF, 400 IO, and 32 BUFGs  are accessible on the device for the usage [38][39]. The utilization percentage of all the resources is as 0.04 % LUTs, 0.05 % FF, 1 % IO, and 3.13 % BUFG. The resources utilized after post implementation are shown in table 1 and Fig. 8  There are numerous methods in order to make the PWM communication power and energy efficient for the development of the green communication. These methods are like dynamic voltage variation at the output and input of the PWM generator, scaling of the capacitance at the output, variation in the frequency of the signal, clock gating techniques, clock mapping, changes in thermal properties, and input output impedance matching with IO standards [44]. In this work the communication model is being made power-efficient by matching the impedance with the help of IO standard. These IO standards are applied at the input and output end of the transmission line, to match the impedance of the input port to the output port [45]. After using the IO standards the communication model will be look like as shown in Fig. 11. There are various IO standards used to make the model power-efficient which is such as LVCMOS (Low Voltage Complementary Metal Oxide), POD (Pseudo Open Drain), SSTL (Stub Series Terminated Logic), HSTL (High-Speed Transceiver Logic), HSUL (High-Speed Unterminated Logic), LVTTL (Low Voltage TTL), and Mobile DDR [46][47]. In this work the IO standard used in making the communication power-efficient is SSTL IO standard [48].

Resources utilization
Utilization Utilization % Fig. 11 IO standard based communication model 4.1 SSTL IO Standard SSTL is the acronym for Stub Series Terminated Logic IO standard. This is used in FPGA for reducing the power consumption and hence makes the device power-efficient [49]. SSTL IO standard works on DDR and DRAM based ICs and memory modules [50]. This IO standard provides high speed to the device. In this work we have used four major SSTL family IO standards which are as follows: a. SSTL135-This family group provides 1.35 V voltage at the input end [51]. b. SSTL15-This family allows 1.5 V voltage for the operation [51]. c. SSTL18_I and SSTL18_II-These two IO standards operate at 1.8 V voltage. SSTL18_I is of class I and works for unidirectional signal whereas SSTL18_II is of class II works for parallel transmission [51]. The internal architecture of SSTL IO standard is depicted in Fig. 12. In Fig. 12 it is seen that the IO standard is applied at the input and output port of the transmission lines. In this section we will cover about the Total Power (TP) used by the device in implementing the efficient PWM generator foe green computing and communication. The total power consumed is the total on-chips power, which is also regarded as thermal power. Therefore TP can be equated as the summation of device Dynamic and Static Power.
DP is the device that power which is calculated when all the inputs of the device are in active state. In FPGA it is the summation of IO, Signal (S/g), and Logic (L/g). SP is calculated when there is no response in the circuitry of the device. Power in FPGA it is the Leakage Power (LP).
A. SSTL135 This IO standard give the input voltage of 1.35 V. when the power is calculated for this then the TP is calculated as summation of DP which is 0.527 W and SP 0.101W. The TP consumed with SSTL 135 is 0.629 W. Here the DP is the total of IO, S/g, and L/g power. The power consumption for SSTL135 is given in table 4 and represented in Fig. 13. … (7) from … (6) C. SSTL18_I SSTL18_I is of the class I group in SSTL18 family, which operates at input voltage of 1.8 V. The T.P consumed with this is 0.637 W. The DP consumed is 0.529 W and the SP consumed is 0.107 W.
From … From … The power consumption for SSTL15 is given in table 6 and represented in Fig. 15.  It is detected from the power analysis of the entire 4 SSTL IO standard that as the input voltages raises the TP consumption for the device also upturns. Therefore there is an increase of 1.74 % of TP when the TP consumption is compared between SSTL135 and SSTL18_II. These 2 IOs consumes the least and the extreme power in the family. The TP consumed for SPARTAN-7 with SSTL is depicted in Fig. 17.

Power Analysis for KINTEX-7 Ultra scale
For KINTEX-7 Ultra scale the power is calculated for SSTL135, SSTL15, SSTL18_I, and SSTL18_II IO standard. In this device the TP consumption is equivalent for SSTL18_I and SSTL18_II IO standard.

A. SSTL135
When the TP is calculated with SSTL135 it is observed that there is 51% of the TP consumed by the device when it is in active state i.e. the device DP which is 0.531 W, whereas 49% of the TP is consumed when there is no active signals i.e. the SP which is 0.509 W. Hence the TP consumed is 1.04 W.
The TP consumed with SSTL135 for KINTEX-7 Ultra scale is described in table 8 and Fig. 18. The TP consumed with SSTL15 for KINTEX-7 Ultra scale is described in table 9 and Fig. 19. From the power analysis it can be detected that there is just a sight change in power among all the IOs of SSTL. SSTL135 consumes the lowest power while the SSTL18_I and SSTL18_II have the maximum power consumption. There is a raise of just 0.19 % in the TP consumption between SSTL135 and SSTL18_I and SSTL18_II. The TP consumption for KINTEX-7 Ultra scale device with SSTL IOs is described in table 11 and Fig. 21. Table 11. TP for KINTEX-7 Ultra scale Fig. 21 TP for KINTEX-7 Ultra scale 5.3 Power Analysis for ZYNQ Ultra scale+ SoC When power is calculated for ZYNQ Ultra scale+ SoC it is found that the TP consumption is quivalent for 2 SSTL IO such as SSTL135 and SSTL15. For the SSTL18_I and SSTL18_II the power consumption is distinguished.
A. SSTL135 and SSTL15 Both of these IO standards give the input voltage of 1.35 V and 1.5 V respectively. When the power is calculated for this then the TP is calculated as summation of DP which is 0.879 W and SP 0.224 W. Hence the TP consumed with SSTL135 and SSTL is 1.103 W. Here the DP is 80 % of the TP consumed while the SP is 20 of the TP. The power consumption for SSTL135 is given in table 12 and represented in Fig. 22.
From … (7) From … (6) From the section 6 it can be concluded that SPARTAN-7 device is suggestively most power-efficient and ZYNQ Ultra scale+ utilizes the highest amount of power consumption. And KINTEX-7 Ultra scale device lies in the mid of both these devices. There is a reduction of 43.07 % TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also it can be observed from section 5.1, 5.2, and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is on active state than static state. Since PWM generator is an integral part of data and wireless communication, therefore it should requires less power for proficient transmission and well-organized green computing and communication.

Future Scope
In this work we are using just approx. 3 % of the total available resources on the FPGA board. And almost 97 % resources are vacant. Hence there is a great chance of implementing the other communication protocols on this FPGA to make an efficient and well-organized communicating device on a single chip. Also later this design can also be converted into small ASIC designs to integrate with latest processor and mobile devices.
Declaration: I hereby declare that all the sections mentioned in the manuscript are relevant. There is no any such non relevant section in the manuscript.