High resolution time-to-digital conversion circuit for HgCdTe APD detector at 77K

: HgCdTe avalanche photodiode (APD) is a frontier research on infrared focal plane technology, High-precision time stamp readout circuit is the basis of the APD focal plane at 77 K, which directly affects APD infrared focal plane performance. Time-to-digital conversion circuit (TDC) is one of the methods to achieve high-precision time stamping. Based on the analysis of MOSFET at low temperature, our design a vernier TDC circuit, which uses a synchronous counter to quantize an integer multiple of the period to achieve a coarse count of 6 bits; The on-chip PLL multiplied high-frequency clock has high-precision and high PVT characteristics, using it to quantify the part that is less than one clock cycle to achieve a fine-count of 6 bits output. The circuit adopts standard CMOS process tape out, our circuit works at a master-frequency of 120 MHz. At 77 K, the circuit test can distinguish the time resolution of 236.280 ps. The DNL is within -0.54~0.71 LSB, and INL is within -1.32~1.21 LSB.

Gain Normalized Dark Current Density (GNDCD) use to characterize the dark current changes of APD devices when avalanche multiplication occurs, as shown in Figure 3, The device state is stable below 6V, and GNDCD changes smoothly. Starting from 8V, due to the increase of tunneling current, the dark current also increases rapidly. The excess noise factor F also shows the same trend. It is about 1.2 under a small bias, and the calculated F is much higher than the normal value when the increase of the tunneling current at 8V. Through the noise test and analysis of the detector, it provides a basis for reducing the influence of noise on the circuit.

Analysis of readout circuit structure
The structure design of the focal plane readout circuit is shown in Figure 4. It is mainly composed of pre-amplification, sample-and-hold, time-to-digital conversion circuit (TDC), phase locked loop (PLL) and control circuit. Its working principle is that when the laser pulse is emitted, the synchronous trigger circuit TDC starts to work, when the detector detects the return laser pulse, the circuit quickly integrates so that the voltage reaches the TDC comparator threshold and flips, generating a stop signal, and the TDC carries the time The analog signal of the information is converted into a digital signal, thereby quantifying time and realizing three-dimensional ranging. Its accuracy will determine the minimum time resolution.  The sequence of the working principle for the vernier type TDC is shown in Figure 5(b). The time T1 between the start signal and the end signal consists of three parts: (1) the time interval T3 between the start signal START and the next rising edge of the counter clock, (2) the clock period T2, and (3) the time interval T4 between the end signal STOP and the next rising edge of the clock.Thus, time T1 can be written as: Where m indicates the number of T2. The time interval accuracy determines the resolution of the time-to-digital conversion circuit.
The structure of the fine counting vernier delay circuit is shown in Figure 6 (Guo et al. 2012;Li 2015;Huang 2004). It consists of two delay chains (multiple identical delay units connected in series), one is for transmitting the START signal with a delay time of t1, and the other is for transmitting the STOP signal with a delay time of t2 (t1>t2). The time interval between the two delay chains is: Each stage is sampled by DFF. Before the STOP signal catches up with the START signal, the output is 0; when the N stage just catches up or exceeds, the output is 1 and flip to stop counting. Therefore, the time can be written as N*T LSB . Among them, the D flip-flop uses the true single-phase clock flip-flop TSPC structure (Takamoto 1993;Li 2012;Duan et al. 2019 The resolution of the time-to-digital conversion circuit is mainly determined by the accuracy of the comparator and the accuracy of the unit circuit in the vernier delay chain. Therefore, at 77K, the design of the comparator and the delay unit in the vernier delay chain are very important.

Low temperature MOSFET model analysis
Since the detector (HgCdTe APD) works at 77 K, it is extremely important to study the characteristics of MOSFET devices at low temperatures. As the temperature decreases, the semiconductor ionization ability becomes weaker, and the hole or electron concentration decreases, which affects the surface potential and causes the MOSFET parameters to change: Threshold voltage increases and source-drain capacitance decreases, etc. This affects the operating characteristics of the readout circuit at low temperatures. Therefore, the establishment of a low-temperature circuit simulation model can better characterize the circuit performance.
By extracting device parameters, test MOSFET devices at 300K and 77K, the results are shown in table 1. The main parameters of NMOS and PMOS have changed significantly at low temperatures. For example, the threshold voltage Vth0 becomes larger by 0.2V at low temperature; the mobility μ0 becomes about three times and the unit source-drain parasitic resistance Rdsw becomes about 1.5 times; the saturation speed vsat increases about 3 times for PMOS. Simultaneously analyze the on-resistance and junction temperature characteristics of the MOSFET, The result is shown in Figure 7. Under the saturated conduction condition of the MOSFET, Rds tends to increase with increasing temperature, realizing MOSFET switching speed faster.

Fig.7 Relationship between MOS tube on-resistance and junction temperature
Figure8 shows the I-V curve measured at 300 K and 77 K for NMOS devices with aspect ratio W/L=20μm/0.55μm. Under the same gate-source voltage Vgs, the operating current in the saturation region of the NMOS device at 77K is significantly higher than that at room temperature, It provides a basis for modeling at low temperature.

Delay unit circuit design
Since the propagation of the delay unit composed of the traditional two-stage inverter is easily affected by PVT, the relationship between them can be written as: where, W and L eff are the gate width and equivalent channel length of the transistor respectively, and P dev is the degree of influence the device parameters on the circuit. Therefore, measures to reduce the propagation delay of the inverter: reduce CL, increase W/L of the MOS tube, that is, reduce Reqn and Reqp and increase VDD. It is easy to get that in order to make the circuit more stable, the value of W can be increased appropriately when the channel length is unchanged. Therefore, in our designing, the aspect ratio (i.e., W/L) of the NMOS and PMOS tube are set to 2:1 and 4:1, respectively.
The delay unit circuit adopts a voltage-controlled structure, as shown in Figure 9. By adjusting the voltage Vtrl of the bias tube, different delays can be obtained. the two NMOS tubes are connected to the power supply voltage to ensure that it can be used in at all process angles. The desired delay time within the corresponding range is obtained by adjusting the bias voltage Vtrl. At the same time, a symmetrical structure is adopted in the delay unit to reduce the influence caused by the parasitic effect of the layout. It can be seen from the Figure 10 that the delay unit can easily achieve smaller time resolution at low temperatures .

Comparator design
As shown in Figure 11, the comparator adopts high-speed comparator structure, which can better combine the advantages of an open-loop comparator and a regenerative comparator. It hence has the advantages of high precision and low offset. The preamplifier amplifies the input differential signal and improves the resolution of the comparator. Its own isolation effect makes the comparator have smaller kickback noise and input offset voltage. The latch (hysteresis) structure is the core, which can effectively increase the speed of the comparator and determine the resolution accuracy. The purpose of the self-biased differential amplifier is to drive the load. The simulation show that the self-biasing working state is between 1 to 3 V. so , in our design, we add an NMOS tube is added to the latch part of the design to raise the minimum voltage of the latch, and make the self-biasing circuit works in a normal state.

Fig.11 Comparator schematic diagram
As we all know that the accuracy of the comparator is directly affected by the input offset voltage.thus in our design, the offset voltage is mainly composed of two parts, i.e.,the input voltage of the pre-amplifier and the latch, namely: Here, A V is the gain of the pre-amplifier, so the offset voltage of the pre-amplifier greatly affects the offset voltage of the entire comparator.
Where A VTN and A VTP are the threshold voltage offset factor of the process model, A βN and A βP are the offset of the process factor. It can be seen from the formula that with increasing the tube size the effect of the imbalance can be reduced.
Usually increasing the gain of the amplifier can also reduce the offset noise. Since the gain bandwidth product is a constant, and in order to ensure that the bandwidth of the comparator is above 100 MHz, the gain of the pre-amplifier stage in the design cannot be too large, so the gain is designed to be 6.02 dB in the circuit.
In the simulation, the comparator reference voltage is 2 V, and a ramp voltage is applied to the other end. The ramp voltage is from 1 V to 3 V has a time interval of 1.06 ms.The most used methods in the simulation are Monte Carlo and corner simulations. Figure 12 shows the worst case in the corner simulation when the comparator is selected under CMOS technology at 77 K, and the different states of tt, ff, fs, sf, ss, etc..It can be seen that the equivalent input offset voltage is 0.45 mV. The maximum offset voltage at less than 1 LSB is 0.244 mV. Table 2 shows the parameter simulation results of the hybrid comparator.

Unit circuit simulation results
The output structure of the TDC vernier delay chain is 0 and 1, and the resolution depends on the time interval which is less than one clock cycle between the start/stop signal and its adjacent main clock rising edge. Under the master CLK of 120 MHz, the simulation parameters are set, and the start signal start changes to high level at 1.15 s. By comparing with the rising edge of the next clock cycle, the time interval is 6.6 ns, and the applied bias voltages of the two delay chains are 1 V and 4 V respectively. Based on the previous analysis of the resolution of the delay unit and the comparator, the theoretically calculated accuracy that can be achieved is: = + = 1.06 * 0.224 * 10 −3 2 ⁄ 128 + 40 = 132.75 Where, R is the resolution accuracy of the comparator, U is the total number of the delay units, and Dt is the accuracy of the delay units.
At 77 K, we use the CSMC 0.5m 2P3M process to do simulation, the simulation results are shown in Table 3. It shows that the value near the flip point, and the 50th flip is achieved in the counter. Which means the accuracy of 132 ps can be achieved in our simulation. Comparing the theoretical value with the simulated value, the theoretical value of 132.75 ps is between the simulated value of 132 ps and 6.6ns/49=134.69 ps. Thus, between 49 and 50, the simulation results are in good agreement with the theoretical calculation results.

Experimental results
After the circuit is taped out, the test chip is packaged in QFP64, the test chip is placed on a custom-designed printed circuit board (PCB), The PCB is assembled in a laboratory Dewar which can operate with liquid nitrogen(N2), As shown in Figure 13.

Fig.13 Tested chip in the Dewar
The block diagram of the test system is shown in Figure 14. It is composed of a high- The coarse count is composed of a 6-bit shift register, and the results are consistent with repeated times at room temperature and 77 K, as shown in Figure 16. The results of the precision counting test are shown in Figure 17. We find that, within 6.6 ns, it takes an average of 22.187 cycles to catch up at room temperature, the resolution converted to TDC is 297.472 ps, and its RMS value is 47.235 ps; however, it takes 27.933 cycles to catch up at low temperature, the conversion time is able to achieve an resolution of 236.280 ps, and its RMS value is 26.709 ps. Fig.17 Fine counting value at room temperature and low temperature test It can also be seen from the Figure 12 that a deviation of the catch-up period appears in the repeated experiment, it leads to the non-linearity of the integral. For the high-frequency digital part, the parasitic effect has a great influence on the circuit, it can cause an increasing of the delay time of the delay unit; In the actual measurement, the error caused by the jitters of the internal clock multiplication CP-PLL directly affects the total time value which less than one cycle and the offset error of the comparator also affects the accuracy.
With using origin pro to fitting our test data, we further obtain the degrees of the differential and integral non-linearity, see Figure 18 below. The values of the degrees are -0.54~0.71 LSB and -1.32~1.21 LSB, respectively. Thus, finally we can get that |DNL| that |INL| of TDC is less than 1LSB and 2LSB, respectively. At 77 K and 300K ,The simulation test summary of the whole circuit parameters is shown in Table 4 below, and compare with Raytheon.

Conclusion
In this work, we analyzed the performance of the time-to-digital conversion circuit of the mercury cadmium telluride APD detector at 77 K. The parameters that affect the resolution are mainly determined by the accuracy of the delay unit of the vernier delay chain and the high-speed comparator. The test results of our circuit simulation indicates that changing the difference of the delay chain via controlling its bias voltage as well as using a high-speed comparator with a latch structure can improve the accuracy of the circuit. At 77 K, the resolution of 236.28ps is obtained, for TDC, and the degree of the integral and differential non-linearity are -0.54~0.71 LSB and -1.32~1.21 LSB, respectively( |DNL|<1LSB, |INL|<2LSB).