Hardware-efficient and accurately frequency offset compensation based on feedback structure and polar coordinates processing

Compared with off-line digital signal processing (DSP) verification, achieving the expected performance and hardware efficiency in application specific integrated circuit (ASIC) is more critical for DSP to reduce power consumption and cost. The performance of traditional frequency offset compensation algorithms based on feedforward structure is strongly dependent on the accuracy of frequency offset estimation. Therefore, frequency offset calculation and loop filtering implemented in ASIC or field programmable gate array (FPGA) usually choose high word-width fixed-point or floating-point operations, which increase the consumption of logical resources and reduce the clock frequency that hardware logic can achieve. This work proposes a frequency offset compensation scheme based on polar coordinate processing and feedback structure, and a pre-decision-based angle differential estimator is used to estimate the residual frequency offset. In the proposed feedback structure, the frequency offset estimator is realized by a simple accumulator, and the input of the accumulator is the residual frequency offset or its scaling, which will reduce the requirement for the accuracy of the residual frequency offset estimator. The offline verification results show that the performance of the proposed algorithm is close to that of the traditional algorithm, but the proposed algorithm has lower logic resource consumption and higher clock frequency in hardware implementation based on FPGA. The performance of the proposed method is evaluated in real-time through 10-Gbps data rate polarization-multiplexed quadrature phase shift keying modulation after 20-km standard single-mode fiber transmission. Compared with offline processing in MATLAB®, no hardware implementation penalty is observed.


Introduction
With the increasing demand for passive optical networks (PONs) for long reach and high rates, direct detection technology is difficult to meet the needs of new scenarios. Coherent detection has been widely used in fiber-optic networks and free-space communications due to its high sensitivity and tolerance to transmission impairments (Kikuchi 2006;Kitayama et al. 2014). One of the most important technologies in coherent communication is the digital signal processing algorithm, which is usually implemented in FPGA or ASIC (Laperle et al. 2014) to overcome various impairments and significantly improve sensitivity. The complexity and power consumption of DSP algorithms have gradually become the main bottleneck of the real-time hardware system.
In long-reach backbone network transmission, additional large chromatic dispersion compensation and complex multiple-input multiple-output (MIMO) algorithms will be used, which would increase the complexity of the DSP algorithm. In short-reach transmission, the complexity of coherent technology is also reduced due to the small dispersion and nonlinear effect. In short-reach high-speed coherent optical communication, the DSP algorithm used in the backbone network needs to reduce the complexity, so it needs to be designed according to different algorithms to optimize the complexity. Several efforts have been made to reduce the complexity of coherent receiver DSP algorithms. For example, a polarization demultiplexing algorithm with zero multiplier consumption is proposed (Liu et al. 2020), which reduces the complexity of the DSP algorithm on the optical network unit (ONU). In order to meet the low-complexity design requirements of coherent PONs, the combination of frequency domain equalization and few-tap MIMO was proposed (Liu et al. 2021). For the short-distance high-speed coherent PONs system, a high-efficiency adaptive equalization scheme based on coherent technology is proposed (Ju et al. 2019), which further reduces the complexity of the DSP algorithm at the receiver. Since the frequency offset between the local oscillator (LO) and the optical carrier can cause phase noise which affects the transmission performance, the frequency offset algorithm is essential on the ONU side. To further reduce the complexity and power consumption of the DSP algorithm at the receiver, we need to optimize the carrier recovery algorithm.
Carrier recovery includes frequency offset estimation algorithm and phase recovery algorithm. According to whether the frequency offset estimation value is feedback to the input signal, the FOE in the coherent optical communication system can be divided into a feedforward structure and a feedback structure. Since the loop bandwidth of the feedforward structure can theoretically reach infinity, the FOE of the feedforward structure is more widely used. So far, various FOE schemes of the feedforward structure have been proposed (Leven et al. 2007;Lei et al. 2008;Cao et al. 2010). Among them, differential phase-based FOE (Diff-FOE) (Fatadin et al. 2010;Huang et al. 2013;Ferreira et al. 2016a) and fast fourier transform-based FOE (FFT-FOE) (Tang et al. 2020;Li et al. 2022) are two widely used algorithms. Both of these two methods require the M-th operation to remove the phase modulation, but the power operation is the most computationally demanding in the algorithm. Although the PADE algorithm applies a multiplier-free design (Lei et al. 2008), there is still a large burden in hardware implementation. To solve these problems, a feedback scheme is proposed (Ferreira et al. 2016b), which simplifies the complexity of the algorithm by forcibly reusing the M-th in the phase estimation algorithm. The experiment shows that there is no obvious difference between the performance of the feedforward structure and the feedback structure. The FOE of the feed-forward structure usually needs to add a delay that is the same as the FOE in the signal branch to achieve delay matching, which will cause a lot of random access memory (RAM) logic resource consumption. For the feedback structure, there has always been a misunderstanding in previous articles that the loop bandwidth will limit the performance of the feedback structure to track frequency offset. But for high-speed systems, the frequency offset is a slowly changing process, and in real-time systems, the frequency offset change rate is only on the order of 1 kHz. In a hardware implementation, although the loop bandwidth of the feedback structure is smaller than that of the feedforward structure, the bandwidth of the feedback structure is still much larger than the rate of frequency offset change. For example, in the system with a clock rate of 312.5 MHz in this work, assuming that there is a delay of 20 clock cycles, the loop bandwidth is 15.625 MHz, which is still much larger than the frequency offset change rate. Another important detail is that the performance of the frequency offset compensation algorithm of the traditional feedforward structure depends on the accuracy of the FOE. Therefore, frequency offset computing unit and loop filter implemented in ASIC or FPGA usually choose fixed-point operation or floating-point operation with high word width. This increases the consumption of logic resources and reduces the maximum clock frequency that hardware logic can achieved.
In this paper, a frequency offset compensation algorithm based on feedback structure and polar coordinate processing is proposed. The proposed FOE estimates the residual frequency offset through PADE-FOE (Lei et al. 2008) and uses the residual frequency offset in the feedback loop. In the proposed feedback structure, the frequency offset estimator is realized by a simple accumulator, and the input of the accumulator is the residual frequency offset value or its scaling value, which reduces the requirement for the accuracy of the residual frequency offset estimator. The effectiveness of the proposed feedback structure is verified both by offline MATLAB ® and real-time FPGA. The offline verification results show that the performance of the proposed algorithm is close to that of the traditional algorithm after floating-point arithmetic processing based on MATLAB ® . But the proposed feedback structure consumes fewer logic resources than the traditional structure and has higher maximum clock rate. Using FPGA to perform real-time digital signal processing on a 10-Gbps data rate PM-QPSK transmission, it is found that the proposed FOE can accurately track the frequency offset around [− 700 MHz, + 700 MHz]. It can still be operated stably even at the frequency offset change ratio of 285 GHz/s. However, the feedforward structure based on 32-bit fixed-point operation cannot achieve accurate tracking. Compared to offline MATLAB ® processing, the receiver sensitivity penalty is zero.
2 Proposed architecture Figure 1 shows the proposed feedback structure frequency offset estimation and compensation algorithm. It consists of two parts: (a) residual frequency offset estimator, (b) proportional integral controller. The dotted line in Fig. 1 is the residual frequency offset estimator that uses the modified PADE algorithm.
The phase of received symbol can be expressed as = d + error , where d is the QPSK data modulation, which can take a value in ∕4, 3 ∕4, −3 ∕4, − ∕4 , and error is the phase error. The phase error can be further expressed as error = 0 + kΔ T + n , where 0 is the error induced by laser phase noises and it can be assumed to be constant for several consecutive symbols, kΔ T is the error induced by frequency offset Δ and it changes by Δ T for every symbol period T, n is the phase fluctuation caused by amplified spontaneous emission (ASE) noises. As shown in Fig. 1, the residual frequency offset estimator mainly includes three parts: (1) "Error Detection" detects symbol phase errors. The decision value of the current symbol is estimated according to the residual frequency offset estimation value Δ̂T and the phase error value ̂e rror of the previous symbol.
(2) "Angle Differential" calculates the difference between the total phase errors of two adjacent symbols. Subtract the estimation error of the previous symbol from the estimation error ̂e rror of the current symbol to obtain an inexact estimate Δ̂cT expressed as In this part, the absolute value judgment operation in the original algorithm is removed, and the feedback controller in the feedback loop is used to remove the phase ambiguity, which will reduce the hardware implementation complexity. (3) "Noise Suppression", this operation uses the loop filter to suppress noise. The loop filter here uses an IIR filter because it has advantages in both performance and hardware implementation. In terms of performance, this loop filter has an inherent feedback process that improves stability and accuracy. For hardware implementation, the loop filter does not need to store instantaneous estimates, thereby reducing hardware complexity. The transfer equation for the IIR loop filter is The loop filter coefficient can be set according to the noise of the system to adjust the correlation between the estimated values of the frequency offset of the preceding and following symbols.
After passing through the loop filter, the algorithm gives the residual frequency offset estimation Δ̂T , which is reserved for the next symbol pre-decision on the one hand. The other hand enters the feedback loop in Fig. 1 as the input to the frequency offset accumulator. After the initial frequency offset estimation, a feedback loop is used to achieve tracking of frequency offset drift. The (n + 1)-th symbol is pre-compensated using the estimated frequency offset of the n-th symbol. As shown in Fig. 2 and Eq. (1.3), Δ̂T is the current residual frequency offset, which is added to the accumulated frequency offset ̂T (1.1) Δ̂cT =̂e rror,k −̂e rror,k−1 .
(1.2) Δ̂T = (1 − )Δ̂T + Δ̂cT, 0 < < 1. to obtain the (n + 1)-th symbol estimate. The frequency offset accumulator integrates the frequency offset error Δ̂T to produce an accurate frequency offset estimate ̂T which can be expressed as where is the scaling factor of the residual frequency offset value, which is usually 1∕2 n , and the computational complexity can be reduced by scaling the residual frequency offset value. The estimation range of the improved PADE algorithm is (− B/8, B/8), where B is the symbol baud rate. When the initial frequency offset is not in this range, the feedback control module will correct it. The essence of ̂T is the phase rotation caused by frequency offset, and the angle of the symbol offset is calculated and compensated by the angle calculator. Polar coordinate system is used for processing, which allows a multiplierfree implementation. The coordinate transformation is based on the multiplier-free coordinate rotation digital computer (CORDIC) algorithm. CORDIC algorithm can significantly reduce the hardware complexity required for vector rotation operation. The algorithm can compute vector rotations simply by summing and shifting operations (Volder 1959). The feedback FOE structure is suitable for any modulation format. The residual frequency offset estimation algorithm needs to be modified for different modulation. Although FFT-FOE algorithm has good performance, FFT operation in FFT-FOE consumes too much logic resources and is not suitable for FPGA implementation. In terms of algorithm performance, PADE is better than Diff-FOE. Because of the above advantages of PADE, this work chooses the hardware implementation of PADE algorithm.

Experimental setup and results
The effectiveness of the proposed algorithm implemented in current commercial FPGA is investigated online in a 2.5-GBaud PM-QPSK modulation over 20-km SSMF transmission. The detailed experimental setup is shown in Fig. 3. An external cavity laser (ECL) with a wavelength of 1550.32 nm (linewidth < 100 kHz) is used as the light source at the transmitting end. The intel Arria10 FPGA repeatedly transmits a 64-Kbit PM-QPSK electrical (1.3) T =̂T + Δ̂T (0 < < 1), Fig. 2 Frequency offset accumulation process diagram signal, which can be thought of as an X-polarization state and a Y-polarization state. The PM-QPSK electrical signal amplified by the microwave amplifier is fed into the PM-IQ modulator, which is biased at its zero point with the assistance of an automatic bias controller (ABC). The launch power of 10 dBm is obtained after erbium doped fiber amplifier (EDFA) before 20-km SSMF transmission.
At the receiver, an integrated coherent receiver (ICR) detects the polarization multiplexed phase modulated signal by beating the signal with a local oscillator. The unit has two optical inputs (LO and optical signal) and eight electrical outputs from four balanced receivers. The signal is coherently detected using the ICR and a local oscillator tuned to the emission wavelength. The electrical waveform after the ICR is collected by the analog to digital (AD) acquisition card, and the sampling rate and resolution are 5 GSa/s and 8-bits, respectively. The digitized signal is processed by real-time DSP in an intel Arria 10 FPGA. The receiver DSP algorithm includes IQ imbalance compensation, clock recovery algorithm based on Gardner power timing error detector, MIMO equalization, frequency offset estimation and compensation algorithm using the architecture shown in Fig. 1, and carrier phase recovery algorithm using traditional Viterbi & Viterbi algorithm. Although the performance of the joint FOE algorithm of X and Y Pol. is better than that of the separate FOE algorithm, considering the high complexity of joint FOE algorithm, separate FOE is adopted at the present stage. The FPGA clock frequency is set to be 312.5 MHz. SignalTap II in the Quartus software is used to obtain the real-time received bits to calculate the bit error rate (BER). The logic resources consumed by FOE algorithm is 7.9 K. Figure 4a shows the statistical characteristics of the measured frequency offset by using the proposed algorithm with the received power and statistical time of -10 dBm and 120 s. It can be seen from the figure that the variation range of frequency offset reaches 350 MHz, and the ratio of equivalent frequency offset to baud rate reaches 14%. The long-time test found that the variation range of frequency offset in room temperature environment is up to 600 MHz, and the variation range of large frequency offset has far exceeded the 1/8 baud rate range of traditional frequency offset estimation. Therefore, the 1/8 baud rate frequency offset correction module shown in Fig. 1 is necessary. As shown in Fig. 4b, the frequency offset of X and Y Pol. is measured by recording the offset estimation register in FPGA within 30 ms. The frequency offset estimation and compensation algorithms of X and Y Pol. in FPGA are realized separately. It can be seen from the figure that the frequency offset estimation curves of X and Y Pol. are almost overlapped. In order to see the frequency offset estimation more clearly, the frequency offset measurement of 3 ms is shown in Fig. 4c. It can be seen from the figure that the frequency offset of X and Y polarization states changes very smoothly. The maximum frequency offset change ratio is 285 GHz/s. Nonetheless, the proposed feedback structure still works effectively. Fourier transform is used to further analyze the variation law of frequency offset, as shown in Fig. 4d two obvious peaks at 180 Hz and 900 Hz, which are mainly caused by mechanical vibrations that cause tiny deformations in electronic components such as laser cavities (Kuschnerov et al. 2010). The frequency offset is slowly varying at the rate of KHz. This is also the reason why the feedback structure can ideally track the change of frequency offset. In order to evaluate the accuracy of the proposed feedback structure frequency offset estimation algorithm, we propose an actual frequency offset test method, which is obtained by summing the feedback frequency offset estimation and residual frequency offset estimation. The residual frequency offset is obtained by calculating the slope of the phase rotation angle estimated by Viterbi-Viterbi (V-V) algorithm. Figure 5a shows the relationship between the estimated frequency offset value based on the feedback structure and the actual value, which is measured at the received power of − 45.5 dBm corresponding to BER of 1e-3. The actual frequency offset curve is smoother. Figure 5b shows the variation curve of V-V estimated phase with time obtained from three measurements. The residual frequency offset can be calculated by calculating the slope of the fitting curve. Figure 5c shows the residual frequency offset statistical count in 60 s. The mean and variation of residual frequency offset are 0.19 MHz and 2.23 MHz, respectively. It can be demonstrated that the proposed FOE has high estimation accuracy, and the residual frequency offset is much smaller than the requirement of the V-V algorithm. From the above results, the frequency offset estimation and compensation algorithm based on feedback structure proposed in this In order to further evaluate the performance of feedback structure frequency offset compensation algorithm and feedforward structure frequency offset compensation algorithm, we design and implement the two structure algorithms in FPGA at the same time. Figure 6a shows the variation of frequency offset estimation with time for X and Y polarization signals by the two algorithms. Figure 6b shows a partial enlarged detail of (a). The above tests are also carried out when the receiver power is − 45.5 dBm. It can be seen that when the frequency offset is less than 160 MHz, the frequency offset estimated by the feedforward and feedback structure algorithms is basically the same. However, when the frequency offset is greater than 160 MHz, the frequency offset estimation of the feedforward structure has a large deviation, thus it is impossible to estimate and track the large frequency offset change. On the contrary, the algorithm based on feedback structure can well estimate and track the frequency offset change, even in the case of large frequency offset change range and high frequency offset change rate. From the analysis of the experimental results, maximum frequency offset change rate that can be tracked based on the feedback structure is 285 MHz/s. The frequency offset capture and tracking ranges of feedforward algorithm are [− B/8, B/8] (corresponding to 312.5 MHz for 2.5-GBaud signal). For feedback algorithm, capture range is [− B/8, B/8], however the tracking ranges will expand. The performance of tracking range and frequency offset compensation accuracy for the proposed algorithm and the classical feedforward algorithm is evaluated by co-simulation of MATLAB ® and VPI. The simulation conditions are set according to the experimental conditions, and the frequency offset between the transmitter and the receiver is set to be zero. After the frequency offset algorithm is successfully captured, the center frequency of the laser at the receiving end is slowly changed, and finally the frequency offset is set at the frequency value that needs to be evaluated. After the tracking is stable, the normalized mean square error (MSE) value of the residual frequency offset is calculated. The normalized MSE is defined as where Δ is the actual residual frequency offset (Yang et al. 2018 Fig. 7b. Compared with Diff-FOE, the normalized MSE of feedfoward-PADE is reduced by more than an order of magnitude. The performance of the feedback-PADE proposed in this paper is slightly lower than that of the feedforward-PADE due to the existence of feedback delay. Figure 8a shows the analysis of the impact of frequency offset on system performance verified by MATLAB ® and VPI collaborative simulation. The simulation conditions are built completely according to the experimental conditions. It can be seen from the figure that when the sensitivity penalty of the receiver is 0.5 dB, the allowable frequency offset variation range is about [− 700 MHz, + 700 MHz]. The four curves of BER changing  Fig. 8b are the implementation of FPGA and MATLAB ® under B2B conditions and the implementation of FPGA and MATLAB ® after 20-km SSMF transmission. The MATLAB ® implementation scheme is set as follows: the MIMO signal captured by SignalTap II is sent to the computer for processing, and the computer completes the recovery of frequency offset and phase offset and calculates BER. It can be seen from the figure that these four curves almost overlapped, indicating that the performance of frequency offset estimation realized by FPGA is almost the same as that of MATLAB ® . No receiver penalty is obtained after 20-km SSMF transmission.

Conclusion
In this paper, feedback frequency offset estimation algorithm based on polar coordinate processing is reported and experimentally verified. Frequency offset estimator is implemented by a simple accumulator, and the input of the accumulator is the residual frequency offset value or its scaling value, which is calculated by PADE-based FOE. Compared with feedforward scheme, feedback structure has lower logic resource consumption, higher maximum clock rate in ASICs or FPGAs realization, and can track a wider range of dynamic frequency offset. The accuracy and reliability of the proposed feedback FOE algorithm are verified in a real-time 10-Gbps data rate PM-QPSK system after 20-km SSMF transmission. It is found that the maximum FOE range of the proposed algorithm is [− 700 MHz, + 700 MHz] at receiver sensitivity cost of 0.5 dB, but the feedforward structure based on 32-bit fixed-point operations cannot achieve accurate tracking. As long as the residual frequency offset estimator is modified for different modulation formats, the proposed feedback FOE algorithm is suitable for any modulation format.
Funding This study is supported by National Natural Science Foundation of China (No.61701271), Natural Science Foundation of Shandong Province (ZR2020QF004), and Key Laboratory of Communication Network Information Transmission and Distribution Technology (SCX21641X009, HHX22641X003, FFX22642X010).