The effectiveness of the proposed algorithm implemented in current commercial FPGA is investigated online in a 2.5GBaud PM-QPSK modulation over 20km SSMF transmission. The detailed experimental setup is shown in Fig. 3. An External Cavity Laser (ECL) with a wavelength of 1550.32 nm (linewidth < 100 kHz) was used as the light source at the transmitting end. The Intel Arria10 FPGA repeatedly transmits a 64Kbit PM-QPSK electrical signal, which can be thought of as an X-polarization state and a Y-polarization state. The PM-QPSK electrical signal amplified by the microwave amplifier is fed into the PM-IQ modulator, which is biased at its zero point with the assistance of an automatic bias controller (ABC). The launch power of 10dBm is obtained after erbium doped fiber amplifier (EDFA) before 20km SSMF transmission.

At the receiver, an integrated coherent receiver (ICR) detects the polarization multiplexed phase modulated signal by beating the signal with a local oscillator. The unit has two optical inputs (LO and optical signal) and eight electrical outputs from four balanced receivers. The signal is coherently detected using the ICR and a local oscillator tuned to the emission wavelength. The electrical waveform after the ICR is collected by the AD acquisition card, and the sampling rate and resolution are 5 GSa/s and 8 bits, respectively. The digitized signal is processed by real-time DSP in an Intel Arria10 FPGA. The receiver DSP algorithm includes IQ imbalance compensation, clock recovery algorithm based on Gardner power timing error detector, MIMO equalization, frequency offset estimation and compensation algorithm using the architecture shown in Fig. 1, and carrier phase recovery algorithm using traditional Viterbi & Viterbi algorithm. The FPGA clock frequency is set to be 312.5 MHz. Finally, SignalTapII in the Quartus software is used to obtain the real-time received bits to calculate the bit error rate (BER).

Figure 4 (a) shows the statistical characteristics of the measured frequency offset by using the proposed algorithm with the received power and statistical time of -10 dBm and 120 seconds. It can be seen from the figure that the variation range of frequency offset reaches 350MHz, and the ratio of equivalent frequency offset to baud rate reaches 14%. The long-time test found that the variation range of frequency offset in room temperature environment is up to 600 MHz, and the variation range of large frequency offset has far exceeded the 1/8 baud rate range of traditional frequency offset estimation. Therefore, the 1/8 baud rate frequency offset correction module shown in Fig. 1 is necessary.

As shown in Fig. 4(b), the frequency offset of X and Y Pol. is measured by recording the offset estimation register in FPGA within 30 milliseconds. The frequency offset estimation and compensation algorithms of X and Y Pol. in FPGA are realized respectively. It can be seen from the figure that the frequency offset estimation curves of X and Y Pol. are almost overlapped. In order to see the frequency offset estimation more clearly, the frequency offset measurement of 3 milliseconds is shown in Fig. 4(c). It can be seen from the figure that the frequency offset of X and Y polarization states changes very smoothly. The maximum frequency offset change ratio is 285GHz/s. Nonetheless, the proposed feedback structure still works effectively.

Fourier transform is used to further analyze the variation raw of frequency offset, as shown in Fig. 4 (d). There are two obvious peaks at 180hz and 900hz, which are mainly caused by mechanical vibrations that cause tiny deformations in electronic components such as laser cavities (Kuschnerov et al. 2010). The frequency offset is slowly varying compared to the FPGA clock frequency, only on the order of kHz. This is also the reason why the feedback structure can ideally track the change of frequency offset.

In order to evaluate the accuracy of the proposed feedback structure frequency offset estimation algorithm, we propose an actual frequency offset test method, which is obtained by summing the feedback frequency offset estimation and residual frequency offset estimation. The residual frequency offset is obtained by calculating the slope of the phase rotation angle estimated by Viterbi-Viterbi (V-V) algorithm. Figure 5(a) shows the relationship between the estimated frequency offset value based on the feedback structure and the actual value, which is measured at the received power of -45.5dBm corresponding to BER of 1e-3. The actual frequency offset curve is smoother. Figure 5(b) shows the variation curve of V-V estimated phase with time obtained from three measurements. The residual frequency offset can be calculated by calculating the slope of the fitting curve. Figure 5(c) shows the residual frequency offset statistical count with in 60 seconds. The mean and variation of residual frequency offset are 0.19 MHz and 2.23 MHz, respectively. It can be demonstrated that the proposed FOE has high estimation accuracy, and the residual frequency offset is much smaller than the requirement of the V-V algorithm. From the above results, the frequency offset estimation and compensation algorithm based on feedback structure proposed in this paper can well realize frequency estimation and tracking in the scene of large range and high frequency offset change rate.

In order to further evaluate the performance of feedback structure frequency offset compensation algorithm and feedforward structure frequency offset compensation algorithm, we design and implement the two structure algorithms in FPGA at the same time. Figure 6(a) shows the variation of frequency offset estimation with time for X and Y polarization signals by the two algorithms. Figure 6(b) shows a partial enlarged detail of (a). The above tests are also carried out when the receiver power is -45.5dBm. It can be seen that when the frequency offset is less than 160MHz, the frequency offset estimated by the feedforward and feedback structure algorithms is basically the same. However, when the frequency offset is greater than 160MHz, the frequency offset estimation of the feedforward structure has a large deviation, thus it is impossible to estimate and track the large frequency offset change. On the contrary, the algorithm based on feedback structure can well estimate and track the frequency offset change, even in the case of large frequency offset change range and high frequency offset change rate.

Figure 7(a) shows the analysis of the impact of frequency offset on system performance verified by MATLAB® and VPI collaborative simulation. The simulation conditions are built completely according to the experimental conditions. It can be seen from the figure that when the sensitivity penalty of the receiver is 0.5dB, the allowable frequency offset variation range is about [-700, 700] Mhz. The four curves of BER changing with receiver sensitivity shown in Fig. 7(b) are the implementation of FPGA and MATLAB® under B2B conditions and the implementation of FPGA and MATLAB® after 20km SSMF transmission. The MATLAB® implementation scheme is set as follows: the MIMO signal captured by SignalTap II is sent to the computer for processing, and the computer completes the recovery of frequency offset and phase offset and calculates BER. It can be seen from the figure that these four curves almost overlapped, indicating that the performance of frequency offset estimation realized by FPGA is almost the same as that of MATLAB®. No receiver penalty is obtained after 20-km SSMF transmission.