Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then, the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multi-stacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix. In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. The verification results show that the deviation of resonant frequency is about 6%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\%$$\end{document} and the conversation of the simulation time is about 99.9%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\%$$\end{document} compared with the HFSS model. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN.


Introduction
In recent years, with the rapid development of electronic terminals, electronic systems have developed toward higher speed, higher bandwidth, lower power consumption, and so on. Three-dimensional integrated circuits (3D ICs) are widely used for some unique advantages, such as shorter interconnection and heterogeneous integration [1][2][3]. But the problems such as signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI) become more and more serious in the higher frequency systems [4]. Simultaneous switching noise (SSN) often leads to unwanted noise in power distribution networks (PDNs), and then, the induced power supply fluctuation will cause problems with signal integrity in the system. A major challenge faced by 3D ICs is how to deliver clean power to the active circuits, especially on the topmost chip [5]. Fundamentally, PDN systems have a low value of the impedance in the frequency range of interest to effectively reduce noise. The low-frequency impedance is principally determined by off-chip components in 3D ICs, while the high-frequency impedance is determined by the multi-stacked on-chip structure concerned in this paper [6][7][8]. Through-silicon-vias (TSVs) penetrating the stacked chips act as key interconnect channels to connect stacked chips and thus realize the circuit conduction as shown in Fig. 1. These chips may have different functions to implement a heterogeneous system. The power and ground TSVs, respectively, connect on-chip PDNs that consist of the multilayer power and ground grid metal into a whole as the important electrical pathways to supply the power source for active circuits.
A compact and accurate impedance modeling can help optimize power distribution networks during the early stages of design. The primary objective is to develop an accurate and quick model to predict the PDN impedance. On-chip PDN conditions such as the effective inductance and capacitance at the active circuit affected by the size of the PDN and the number and position of TSVs are very important to precisely evaluate the impedance of 3D stacked on-chip PDNs. As the frequency is closing to a higher value (GHz), even a small TSV inductance can produce several numbers of high impedance peaks induced by the parallel resonances of the TSV and on-chip PDN inductances and capacitances [9]. It will induce a larger noise near the frequency point of the peak impedance. In 3D PDNs, a large number of TSVs are placed in the Si substrate. Multiple and randomly located ground TSVs may be shared by multiple power TSVs in the TSV array. The coupling between P/G TSVs which is affected by the number and distribution of TSVs cannot be ignored because it seriously influences on the power supply noise [10]. In the previous analysis, a uniform distribution of power/ground TSVS (P/G TSVs) was assumed frequently. Although a uniform distribution is preferable to suppress the worst voltage drop in 3D PDNs, it may not be a practical design choice due to the area constraint. In some designs, TSVs are only assigned in the whitespace around circuit modules [11,12]. Too many TSVs in the whitespace will increase the size of the die and may cancel out their benefits. So minimizing the number of TSVs is an important goal for the optimization of PDNs during the design flow. It brings difficulties to obtain and analyze 3D PDN impedance because there exists complicated electromagnetic coupling among TSVs. Knowing the effect of the number and assignment of P/G TSVs on the impedance in advance is helpful to minimize the number of TSVs at the beginning of the design.
A considerable CPU run time is required to analyze the complex multi-stacked on-chip PDN through finite element simulation software such as ANSYS HFSS. Many published studies have reported the impedance models of PDN systems rather than finite element simulation. For the plate-shaped PDN, the analytical methods are used to calculate the impedance such as the resonant cavity method [13,14], the imaging method [15], the transfer matrix method [16,17], and boundary element method [18]. With the development of IC technology, mesh-type and grid-type PDNs are usually designed since the plate-shaped PDN is easy to peel off during the fabrication process. The segmentation method is the basic method to analyze complex PDN structures. Some researchers have built the equivalent circuit models for the 3D PDNs using the lumped circuit models of on-chip PDNs and TSVs to analyze the impedance of the PDNs by SPICE simulations [19][20][21][22]. Others propose a hybrid approach combining the full-wave EM simulation and the circuit model to obtain accurate impedance of the PDN [23,24]. Most of these studies focus on the influence of the regular TSV array on the PDN impedance, but few studies focus on the influence of the irregular TSV array with complex couplings. In Ref. [20], the proposed model of the regular P/G TSV array has a limitation in the assumption of uniform current magnitude distributions across all power and ground TSVs in the uniform distributed TSVs during the extraction of the partial TSV inductances. It leads to the inaccurate partial TSV inductances in a real multiply stacked PDN which has an uneven power distribution. In Refs. [25,26], it uses a segmentation method to model the PDNs with multiply pairs of P/G TSVs. It considers the effects of P/G TSV pairs to estimate the impedance of the 3D stacked PDN. It is no longer applied if TSV pairs are close to each other because there is greater coupling between them. And it is unsuitable for the arbitrarily distributed TSVs which multiple grounded TSVs are shared by multiple power TSVs. There are two TSV design schemes, namely the irregular TSV placement and the regular TSV placement for the design of 3D ICs [27]. For the irregular TSV placement, the matrix-based calculation using a segmentation method can accelerate the calculation speed for the PDN impedance estimation and solve the complexity problem of building a SPICE circuit due to the lots of coupling. In this paper, a matrix calculation method is proposed to solve the PDN impedance of multistacked chips based on TMM rather than the simulations of the HFSS and SPICE. The P/G TSVs in the TSV array can be regular distributed or arbitrarily distributed. The coupling between the TSVs and the distributional effect of the onchip PDN is considered. The test ports of the model can be TSV connection ports or ports of any interested nodes on the on-chip PDN of every tier. The multi-stacked onchip PDN impedance is calculated quickly and accurately by the proposed method. It shows the advantages of large savings in computer run time and flexibility and versatility in applications.
The paper is organized as follows. In Sect. 2, a typical multi-stacked on-chip PDN structure based on TSVs is given and a detailed derivation of the impedance matrix is presented. In Sect. 3, the impedance obtained by the proposed method for different TSV distributions is compared. The accuracy of the proposed method is verified with the results obtained from HFSS. Compared with the results of HFFS and other methods, it concludes that the proposed method is accurate and effective. The influence of several arbitrarily distributed TSVs on the multi-stacked on-chip PDN impedance is also compared and analyzed. Finally, there is a conclusion drawn in Sect. 4.

Modeling and analysis of the multi-stacked on-chip PDN impedance
A locally simplified multi-stacked on-chip PDN in stacked 3D ICs is shown in Fig. 2, where active layers are face-toback (F2B) stacked. The grid-type PDN is usually used for the on-chip PDN because it is efficient when it comes to design with a limited area and it is not easy to peel off. The grid-type on-chip PDN is composed of orthogonal metal wires in two interconnection layers, where power wires and ground wires are routed alternately in the same interconnection layer with an identical pitch and connected to corresponding wires in the next interconnection layer by a large of micro-vias. The P/G TSV array in silicon substrate connects adjacent on-chip PDNs to achieve power delivery. In this paper, bumps are simplified as an extension of the TSV metal. The impedance matrix of the multi-stacked on-chip PDN can be derived by using separated P/G TSV array and on-chip PDN models through TMM.
For an on-chip PDN model, a quasi-static solver can be applied if the dimension of a network is much less than onetenth of the wavelength of interest (0.1 ). The grid-type onchip PDN can be divided into a lot of periodic unit cells with a lumped element model for each cell. As shown in Fig. 3, the P/G grid is divided into (N − 1) × (M − 1) unit cells modeled with a distributed network of RLCG elements. The equivalent circuit of each grid unit cell consists of the resistance ( R u ), inductance ( L u ), conductance ( G u ), and capacitance ( C u ) which can be accurately calculated as (1), where  The unit cell with its equivalent circuit model L p and L w are the pitch and width of the metal line of the mesh grid. Parameters with subscripts of CMS and Micro represent parameters per unit length in the coplanar multistrip type transmission line and the conductor-backed coplanar multistrip type transmission line, respectively. More details of the calculating procedure are presented in [28].
According to the relationship between the nodal voltage and the nodal current, the admittance matrix of the P/G grid ( Y P∕Ggrid ) in N × M nodes can be expressed as: where Y ii is the N × N self-admittance matrix of unit cells in the ith column and Y ij is the N × N mutual-admittance matrix of unit cells between the ith column and the jth column. Z S and Y P are the impedance and admittance of a unit cell, respectively. is the angular frequency.
As the size of the P/G grid increases, the number of the unit cells is increasing rapidly and the size of the admittance matrix of the P/G grid is bigger. The matrix calculation will become more complex and time-consuming. In the impedance calculation of a multi-port network, the input impedance of one port is obtained under the condition that the input currents of other uninterested ports are zero. To simplify the matrix and speed up the calculation, the matrix transformations are as follows. The relationship between voltages and currents in nodes of the grid metal is rewritten as: where I a and V a are the current and voltage vector in the interested nodes, I b and V b are the current and voltage vector in the neglected nodes. For simplifying the admittance matrix of the P/G grid, the neglected nodes can be seen as open circuits and these nodal currents are limited to zero as (4). Then, these nodes are deleted from the grid nodes, only remaining the interested nodes.
So the simplified admittance matric ( Y sim ) in only interested nodes can be derived as: For a multi-stacked on-chip PDN, the P/G TSVs connecting adjacent on-chip PDNs can be randomly distributed. The nodes with power TSVs connecting are regarded as the nodes of interest to reduce the admittance matrix. The transmission matrix for a multi-port network can be derived in terms of the concerned nodal voltages and nodal currents and can be represented to relate the voltages and currents as: So the transmission matrix of a single on-chip PDN in the vertical direction ( T PDN ) can be written in a simpler form as: It is not ignored that the electromagnetic coupling exists among the P/G TSV array as the frequency increases. To simplify the analysis of the coupling, the TSV array is considered as the multi-conductor interconnection and established the T-shaped network topology of the equivalent circuit model. Without a doubt, the equivalent circuit model becomes extremely complicated as the number of TSVs increases. This paper replaces the simulation of the complex equivalent circuit with using the matrix computation .
All the values of lumped elements in the model of TSVs as depicted in Fig. 4 are given in the closed-form formulas as [29]. A ground TSV is arbitrarily set as the reference marked with 0. The values of the self-inductance ( L ii ) and mutual inductance ( L ij ) of other TSV metals can be calculated as: where 0 is the permeability of the vacuum, P ij is the distance between the TSV marked with i and the TSV marked with j, h metal is the length of the TSV metal, and r TSV is the radius of the TSV. Considering N TSVs in which there are m power TSVs and n ground TSVs, all ground TSVs which are shorted represent the current return path. Based on the definition of the loop inductance with the size of m × m , it is rewritten as [30] : where V p and I p are the m × 1 voltage and current vectors of m power TSVs, respectively, V g is the n × 1 voltage vector of n ground TSVs. Then, the effective loop inductance ( L eq ) of the TSV array is yielded. When regarding each outer edge of the TSV as an equipotential surface, the equivalent inductance of Si substrate ( L Si_eq ) in a homogeneous medium can be calculated as derived in (8) and (9). Next, simplify calculate the effective capacitance ( C Si_eq ) and conductance ( G Si_eq ) matrix of the silicon substrate as [31] : The internal impedance ( Z in ) for a TSV metal can be expressed as: where I 0 and I 1 are the modified Bessel functions of order zero and one, respectively. The effective internal impedance matrix ( Z in_eq ) of the TSV array can be obtained in the similar way to (9). The linear capacitance of a TSV can be expressed as: Next, Z in is given by 1∕(j C OX ) to calculate the effective linear capacitance matrix ( C OX_eq ) as also similar way to (9). The effective linear capacitance matrix of the TSV array is extracted from Z in_eq = j C OX_eq −1 . The impedance and admittance of the P/G TSV array can be expressed as: The transmission matrix of the TSV array ( T TSV ) can be derived as: Finally, the separated on-chip PDNs and TSV arrays are assembled into a whole. According to the cascade of the multi-port network as shown in Fig. 5, the transmission matrix of the multi-stacked on-chip PDN combining multiple on-chip PDNs and TSV arrays ( T total_n ) can be expressed as: where T PDN_n is the transmission matrix of the on-chip PDN of tier n, T TSV_n,n−1 is the transmission matrix of the TSV array between tier n and tier n − 1 . The impedance matrix Fig. 4 The partial equivalent circuit model of a TSV array of the multi-stacked on-chip PDN ( Z total_n ) can be derived from T total_n as: The impedance matrix describes the voltage-current correlation over the connection ports of the PDN at different frequencies. The coupling effect between TSVs through matrix calculation is considered in the arbitrary distributed P/G TSVs. For the impedance of the ports of any interested nodes on the on-chip PDN of every tier, it can be derived from the Z-matrix transformation of the black box model as shown in Fig. 6. segment is expressed as a single on-chip PDN where interested ports (p) are. segment is expressed as the remaining part of the multi-stacked on-chip PDN. The interconnection between them is replaced by the interconnected ports denoted c-ports on the segment and d-ports on the segment. p and q ports are the concerned ports of the (16) and segments. The Z-matrices of , , and segments are, respectively, partitioned into submatrices corresponding to the interested and connected ports as: Z and Z can be replaced, respectively, by different Z total_n due to different segments. According to the continuity of the voltage and current on ports c and d, Z can be calculated as:

Validation and analysis of the proposed method
To verify the accuracy of the proposed method of the impedance estimation in the TSV-based multi-stacked on-chip PDN structure, a double-stacked grid-type on-chip PDN is constructed and its parameter description is listed in table 1. It has a horizontal size of 1mm × 1mm. Fig. 5 The configuration of a multi-stacked on-chip PDN transmission modeling Fig. 6 The illustration of a black box model  The ordinary cylindrical TSVs filled with copper are applied in the TSV array. Designers need to arrange these TSVs properly to meet signal integrity, power integrity, and heat dissipation requirement. Fig. 7 shows two different TSV assignments. For a regular TSV distribution, P/G TSVs are uniformly distributed on the nodes with an identical pitch. For an arbitrary TSV distribution, P/G TSVs are only assigned in the whitespace around the circuit modules. Therefore, P/G TSVs can be arranged in any position of the substrate that is dependent on the distribution of the circuit modules. Multiple and randomly located ground TSVs can be shared by multiple power TSVs. Without good planning and optimization, the over-design P/G network may create congestion problems for the later signal routing resources that are over-used. In the constructed structures, the regular TSV distributions are shown in Fig. 8, which includes the different number of TSV pairs and the uniform TSV distributions with the different scales of the TSV array. The proposed model is used to calculate the impedance of which the result is compared with the full-wave method and previous models. Due to the difficulty in the fabrication of complete multi-stacked on-chip PDNs, a frequency-domain simulation to extract Z-parameters is conducted ranging from 0.1GHz to 40 GHz with a 3D electromagnetic (EM) solver, ANSYS HFSS to verify the accuracy of the proposed method. Lumped ports for the analysis of the PDN input impedance are located on the topmost on-chip PDN.
As shown in Fig. 9, the PDN impedance curves have similar characteristics which mainly have three resonant frequencies ( f 1 , f 2 , and f 3 ) below 20GHz. These frequencies are caused by the series and parallel resonances of the equivalent capacitance of the P/G grid ( C P∕Ggrid ), the equivalent inductance of the P/G grid ( L P∕Ggrid ), and the equivalent inductance of the TSV array ( L TSV ). As the number of TSVs increases, f 2 moves to a higher frequency and it is eliminated if the number of TSVs is large enough. In this situation, f 3 is Fig. 7 The configurations of two different TSV assignments. a A regular distribution: TSVs are placed on each node b An arbitrary distribution: TSVs are only placed in the whitespace .9% compared with the HFSS model. The proposed model leads to a larger saving in CPU run time than using HFSS simulation. It only takes a tiny computing time compared with the full-wave method. Therefore, it is concluded that the proposed model is accurate and efficient to estimate the impedance of the multi-stacked on-chip PDN with the regular TSVs connecting. Comparatively, the benefit of the proposed method is that it can deal with the complicated TSV array including not only the regularly distributed TSVs but also the arbitrarily distributed TSVs in 3D PDNs. The arbitrarily distributions of TSVs are constructed as shown in Fig. 10. The whitespace around the circuit models is, respectively, across, peripheral, and combined distribution in the substrate, and TSVs are only assigned in the whitespace. To enable power TSVs to be connected directly to the power wires without the need for the extra redistribution layer, power TSVs are placed designedly at the location of the intersection of the two-layer of the power metal wires so that it can reduce the wiring area. Ground TSVs are placed designedly at the location of the intersection of the two-layer of the ground metal wires. The impedances of three test ports marked with port 1, 2, and 3 are calculated and qualitatively analyzed. The results are shown in Fig. 11. In the range of the lower frequency, the impedance shows capacitive which is determined by the C P∕Ggrid and the equivalent capacitance of the TSV array ( C TSV ). As the number of TSVs increases, the total capacitance is increasing so that impedance is decreasing. As the frequency goes up, the impedance shows inductive which is determined by the L P∕Ggrid   The comparison of three kinds of arbitrary distributions of P/G TSVs for the PDN impedance since the L TSV decreases to a very small value that can be neglected if the number of TSVs is large enough.
The impedance of the PDN should stay at a low level to ensure power integrity. Aspects that the influence of the impedance for the multi-stacked on-chip PDN and methods to decrease the impedance are studied. Fig. 12 shows several kinds of low density and arbitrary P/G TSVs connecting between tier n and n-1. The impacts of the number of TSVs on the impedance of the multi-stacked on-chip PDN are explored. Fig. 13 compares four input impedances at the center of the toper tier for the double-stacked on-chip PDNs with four kinds of arbitrary TSV array connecting as shown in Fig. 12. Four PDN impedance curves have similar characteristics. Careful observation reveals that the difference in the input impedance of the lower frequency range is slight. The reason is that the impedance of the lower frequency range is caused by the total capacitance which consists of C TSV and two times C P∕Ggrid . As the number of TSVs increases, the capacitance of TSVs is gradually larger and the total capacitance is only larger slightly, but the effective inductance of the power TSVs is smaller. The resonance frequency f 1 goes to the higher frequency range with an increased ground TSV number compared to case a with b and c, which can affect the relative distance between the frequency of the impedance peak and the clock frequency, but the impact is getting smaller with more ground TSVs compared case b with c as it is shown that the impedance curves tend to be approximately the same. Therefore, it needs to add more power TSVs as shown in case d if higher f 1 and f 2 are wanted, and f 2 will be eliminated because of the enough TSVs.
To determine the effects of the number of stacked tiers on the impedance, it varies from two to four. Fig. 14 shows the comparison of three input impedances at the center of the topmost tier for the multi-stacked on-chip PDNs with the TSV array connecting as shown in case c in Fig. 12. The P/G grid and TSV capacitances increase with the number of stacked tiers increasing so that the impedance below the series resonant frequency ( f 1 ) is decreased. f 1 moves to a lower frequency range, but the lowest parallel resonance  Fig. 13 The comparison of the input impedance at the center of the toper tier for the double-stacked on-chip PNDs with four kinds of TSV arrays connecting, respectively, as shown in Fig. 12 Fig. 14 The comparison of the input PDN impedance at the center of the topmost layer depended on the different numbers of the tiers frequency ( f 2 ) of them moves to the lower frequency range with the higher PDN impedance peak. As a result, it needs to pay more attention to designing the future heterogeneous 3D IC because a higher-stacked on-chip PDN is more difficult to keep minimizing the low PDN impedance.
To determine the effect of the size of the stacked onchip PDN on the impedance, the scales of the sizes of fourstacked on-chip PDNs are varied from 0.7 to 2.2. The uniform density distribution of TSVs is adopted. Fig. 15 shows the comparison of three input impedances at the center of the topmost tier for the four-stacked on-chip PDNs with the TSV array connecting as shown in case d in Fig. 12. When the scale of the stacked on-chip PDN is increased, the impedance below series resonant frequency ( f 1 ) is decreased because the P/G grid and TSV capacitances increase. f 1 moves to the lower frequency range. The parallel resonance becomes less and less obvious in the high-frequency range.

Conclusion
The proposed model can reflect the various arrangements of the P/G TSVs for estimating the multi-stacked on-chip PDN impedance in 3D ICs. The separated power/ground grid units of the on-chip PDN are modeled as the transmission line using the frequency-dependent RLGC parameters, and the TSV array is modeled using the theory of multiconductor transmission lines. The coupling between the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN is considered. Then, the impedance of the multi-stacked on-chip PDN is derived by the transmission matrix method through the cascade. It replaces the simulation of the complex SPICE circuit in which there exists lots of coupling with the matrix calculation method. It is computationally efficient and leads to a large saving in CPU run time. For the complicated structure, it is also accurate and scalable to analyze the impedance in the predesign stage and help designers achieve a 3D PDN quickly and reliably.