Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique

The threat application and data hacking systems rule today’s digital world. Hence, securing digital information is the most needed to keep personal detail confidential. Several advanced crypto techniques were implemented in the past, resulting in the finest securing outcome. However, those models required additional features and maintenance based on the utilized applications. Considering these difficulties, Data-encryption-standard has been implemented, and the security functions were enriched by performing the Bernoulli mathematical model. So, the presented technique is named a novel Bernoulli Data-encryption-standard (B-DES). Here, the Bernoulli function has been performed after the XOR process, and then during the decryption process, the function of the novel B-DES has been reversed. Moreover, the designed encryption approach is checked with different attacks like brute force attack, Known plain-text Analysis, Chosen-Plaintext Analysis, Man-in-the-Middle Attack, and Ciphertext analysis. Here, the gained power usage by the designed scheme is 193 mW, compared to other models; it has diminished the power usage by 7%. Moreover, the earned memory utilization is 0.6 kB; compared to other models, it has reduced memory utilization by 3%. The delay rate recorded by the designed model is 3.43 ns; compared to other models, it has minimized the delay score by 3%.


Introduction
Secure communication has become an important topic in today's digital area for secure banking and other privacy-based applications [1]. For secure communication, a series of steps must be taken to ensure that data sent through an insecure channel cannot be viewed by anybody other than the intended recipient [2]. Thus, using cryptography is essential to develop such a system [3]. Both encryption-decryption are the key components of cryptography, a security measure used to keep sensitive information out of the hands of unauthorized individuals or groups [4]. Once the data has been transmitted, it is decrypted and returned to the original form at the receiver's end using a cryptography key [5]. Algorithms comprise different key types that are effectively employed to implement the encryption-decryption process [6]. A single key is worn for the encryption and decryption function in the symmetric crypto procedure [7].
Moreover, in the asymmetric crypto model, double keys were employed to process the crypto functions [8]. Both key types encrypt data using a public and a secret key. The proliferation of content on the web led to the development of cryptography that led to the VLSI execution for the encryption and decryption of data that used various approaches [9]. Encrypted data is delivered to a distant host-encoded at the source host through an encryption key [10]. Then encrypted data is sent to its recipient, where it is decoded to retrieve the original data [11]. So, the attacker would not get the encrypted key to decrypt the message or info [12]. The concept of keys was effectively noticed by examining numerous encryption techniques [13]. As a result of the investigation, it has been determined that a more secure framework can be established by lengthening the key [14]. Also, the wider key size requires more electricity to operate and generate more heat [15].
Essentially, the crypto concept is a trade-off between security and operating expenses. Significant efforts are needed to construct more robust encryption [16]. A highly effective block cipher should be characterized by two chef parameters: rapid response and complexity reduction [17]. Security is becoming increasingly crucial in network-connected technologies. There is a greater incentive to compromise network-connected ingredients than closed systems owing to circumstances such as a larger threat landscape via local and remote access and the possibility for major attacks to utilize compromised nodes containing large datasets [18]. Cryptography is one of the critical components against adversaries. Moreover, it is employed to ensure the confidentiality and integrity score of the data and give entities participating in communication anonymity and authentication [19]. Moreover, in these modern smart facilities, the mathematical operations enriched the crypto operations, Such as addition, multiplication integration, and so on [20]. In many cases, applying the mathematical constraints in the crypto concepts has been tended for an irreversible process. So in advance, the binary arithmetic model has been proceeding with the principle of mathematical equations. Hence, this process can help to mitigate the computation time and resource utilization. In addition, a one-time pad function has been incorporated into the crypto mechanism to enrich digital communications. Moreover, it has minimized data theft and key stealing. However, it has recorded more time to execute the process [21]. Moreover, the Lion Swarm optimization model has been implemented for the crypto mechanism to improve the data communication process. Finally, the designed model is validated in the wireless sensor network [22]. In addition, securing large data is more important, so the crypto mechanism is implemented in the cloud computing framework. In addition, convolutional networks have been executed to predict the user's behavior [23]. But, it has recorded more time complexity. Besides, the homomorphic cryptosystem is checked for the electronic digital application for securing digital information [24]. It has afforded a better privacy range for digital information. However, it is high in economic cost. Furthermore, transferring massive data requires more resources through a digital application. Hence, the cloud system was introduced to share the high volume data [25]. Here, the communication is optimized by the optimization modules. However, additional features are required to optimize the function. On the other hand, trible elliptic curve models were implemented for the distributed platform to maximize the crypto technology. Here, the elliptic curve cryptosystem is implemented to address the issues of the conventional cryptosystem [26]. But, this model has required more resources to design the cryptographic process. Several powerful crypto techniques have enriched digital applications by improving security functions. But some harmful attacks, like the Mirai botnet, DoS, etc., have destroyed the digital application's confidential range.
Hence, the main objective of this work is to improve crypto security by incorporating the mathematical model. Finally, the security range of the designed model is measured by validating its confidential score against different security attacks. So, the present research article has aimed to design a novel, efficient data encryption-standard (DES) based on incorporating multiplication concepts. Here, the novelty of the work after the XOR operation and the Bernoulli functions were performed. The usage of the Bernoulli concept in the DES was verified by validating the execution parameters. In addition, several attacks were launched in the final process to verify the robustness of the encryption functions.
The key contribution of this current work is described as follows, • Initially, DES has been modeled mathematically in the MATLAB environment with key exchanging parameter. • Consequently, the Bernoulli multiplication theorem is a frame for the polynomials. • Moreover, the designed multiplication model is given to one of the S-box functions of the DES. • Then the confidentiality and time complexity have been noted in both cases that are before and after applying the multiplication function, which is tested in the Matlab FPGA function. • The designed Bernoulli-DES is verified with other models in terms of security range, encryption time, execution duration, delay, power, and energy.
The planned research work is described as follows, Sect. 2 details the recent associated work about the crypto models in the FPGA environment, Sect. 3 explains the normal DES system and issues Sect. 4 offers a novel solution for the mentioned issues, and the outcome of the novel technique is revealed in the Sect. 5. The research arguments were ended in the Sect. 6.

Related Work
Some of the recent works related to FPGA are described below: Internet-of-Things (IoT) has incorporated several resource-strained devices in the network. To avoid resource constraints, reliable cryptography-based algorithms have been employed. Arthur Teodoro et al. [27] have presented Artificial Neuralarchitecture as a Tree Parity scheme (TPS) for performing key exchange through mutual learning networks. In the embedded systems area, FPGA has attained more space; therefore, TPS implementation in FPGA was analyzed and tested to optimize performance parameters. Moreover, the presented TPS implementation takes less time for synchronization performance. However, increasing the parameter N value affects the performance of synchronization.
Chen et al. [28] presented a polynomial ring-based processor with high performance for an algorithm called CRYSTALS-Kyber. Control logic was reused by inverse and forward Theoretic-based-Transform using the effective configurable butterfly-based unit to mitigate the finite state-machine area. The implementation of a low-cost FPGA-based platform validates the performance of the presented method. The presented CRYSTALS-Kyber has higher memory throughput and efficiency. Moreover, this model can affect by channel attacks.
Zoni et al. [19] presented a scalable and efficient structure for implementing bit-flipping functions targeting highly lightweight codes for post-quantum-based cryptography. Moreover, the lightweight cryptosystem has nine configurations employed for the implementation process. The result indicated that the optimized structure allows large encoded implementation on small FPGAs. However, certain implementations reduce the average speed performance.
The varied composite field-based arithmetic unit implementation utilized in the McEliece cryptosystem was presented by Canto et al. [29] for countermeasures. It utilizes tailored and overhead-aware signatures. The FPGA implementations with a Graphical processing model were performed to indicate the proposed schemes' feasibility. The result indicated that the presented approach covers high errors at viable overheads and low costs. However, this method takes more time the process.
Takougang et al. [30] have presented an autonomous 5G system stability analysis, including quasi-periodic and periodic attractors, coexisting attractors, stability phenomenon, hop bifurcation, one-scroll and double-scroll chaotic attractor, reverse-period doubling, and offset boosting. Using FPGA, the presented 5G system model is implemented. The result indicated that attractors' coexistence generated by FPGA implementation had attained better qualitative agreement. However, the execution time is high.
The hardware-aware algorithm was implemented in the cryptography technique by Wang et al. [31] to improve the security parameters up to the hardware level. Hence, the designed crypto model is tested in the real-time application. Moreover, it has recorded a high confidential score for real-time applications. However, running the system has required more resources, leading to recording the high time complexity and economic cost.
Syafalni et al. [32] have designed holomorphic accelerator modules and a cryptographic system. Hence, this model is used to verify the user authentication process after storing the digital records in the cloud environment. Moreover, the designed accelerator is checked in the FPGA platform, and performance parameters such as delay, memory usage, encryption time, and error score have been measured. It has recorded outstanding results. But this model is complex in design because of multiple features.
To compute the memory usage, Reis et al. [33] have implemented the computing memory paradigm and the storage boundaries to set the maximum storage level of the cloud storage. After designing the cloud storage, the encryption model is implemented in that particular cloud memory to secure the stored events. Finally, the designed model is tested by optimizing the CPU and increasing the performance of the FPGA. However, it has recorded high latency.
Saračevic et al. [34] have designed the DES for the IoT application to secure digital data. Hence, the designed DES model is tested in different IoT applications. During this test validation, the performance of the DES was recorded. It provided better data security for the stored IoT data in many cases. However, if the data is unstructured, the DES model has generated weak keys, leading to data loss and hacking.
Hence, securing cloud data is more important. However, the literature studies have proved that the advanced models have met several issues like high resource utilization, high time complexity, and design complexity. Considering these issues, the present study has planned to implement a mathematical scheme in the DES to enhance security functions. Compared to all cryptographic models, the DES system is easy to implement with a less complexity score. Hence, the DES models were considered for this present research study. Moreover, the disadvantage of the DES is weak key generation; here, this weak key generation was neglected by introducing the mathematical model. Hence, the present study and the novel technique are the most required tasks for maintaining the privacy range for the digital cloud environment.

Problem Statement
The DES cryptosystem is utilized in many digital applications real world. But, the growth of hacking and malicious vulnerability technologies has maximized the trouble in encrypting the data using the DES model. So, it lacked security functions against harmful, malicious events. Hence, many arithmetic models are implemented together with DES to maximize the strength of the secret data. However, those system has raised the complexity range and time consumption. The usual DES system is represented in Fig. 1. Besides, several multiplication models were also implemented in the DES round, but the outcome of those models was not appropriate. So, the present work has planned to implement a polynomial multiplication model in the DES round to enhance DES security. In the normal DES model, the cipher text was gained by doing the XOR operations. But it is not secure in all cases; the probabilistic-based malicious events can break the XOR and get the cipher text. Then the corrupted data was sent to the receiver side. These issues have motivated to implement the multiplication model in the DES environment.

Proposed B-Des Methodology For Improving Security Range
The key aim of this current work is to enrich the security of DES against harmful, malicious events. Here, the function of the DES [34] has been improved by applying the Bernoulli multiplication [35] constraints in the DES procedure. Hence, the planned modified DES is known as Bernoulli-DES (B-DES). Finally, the effectiveness of the designed multiplication-based DES is tested against brute force attacks. Subsequently, the key parameters were analyzed and compared with another conventional model. Moreover, the proposed architecture is described in Fig. 2.
Finally, the designed model is checked against brute force attack. Hence, the original data hasn't been attained while applying the brute force attack in the encrypted data. It has verified the robustness of the designed cryptosystem. Also, the after incorporating the multiplication process, it has reduced the encryption time to the normal DES. Here, the 64-bit size data has been given as the input of the Bernoulli DES, in that the key size bit counts are 56 and error parity check bits are 8. To make the plain text into the cipher text, 16 rounds of operations have been done. After the Initial permutation (IP), the 64 bits are separated as 32 + 32; here, the 32 bits are processed in LS, and the other 32 bits are processed in RS. Moreover, the S-box in the B-DES has taken 6 bits as input and produced 4 bits block as output. The designed DES model is described in Fig. 3.
In addition, the F-function represents the Feistel process; the purpose of using the F-function is to decrypt the cipher text without any additional resources. Hence, it has minimized the computational cost of the encryption standard. Usually, to gain the chipper text, XOR functions were used, but it is vulnerable to malicious events. Hence, in this proposed DES, the Bernoulli equation was considered. Hence, the Bernoulli equation using Eq. (1), Here, m represents the count of the plain text bits and the i n has determined the XOR-ed output and a is the Bernoulli digits. Here, the Bernoulli digits were taken as same as the XOR-ed output. Moreover, the B m is the Bernoulli variable, its value is 1, and the constant variable is denoted as n. Then the binary addition has been performed, then to decrypt the data, the concatenated digits of the Bernoulli are again XOR-ed from the XOR-ed cipher data. Because, the reverse process of XOR is XOR function. Finally, the process has been reversed to attain the original text. The B-DES Simulink model is illustrated in Fig. 4.
The Simulink design of the novel B-DES approach is described in Fig. 4. Here, the double-data-rate (DDR) is the memory module of the novel B-DES. In addition, an efficient malicious event was launched in the final layer of the B-DES to check the successful score of the Moreover, the parameters of the novel B-DES is validated in the dual phases, that is, before and after applying the malicious features. Hence, the malicious feature that has been considered to validate the designed cryptosystem is the brute force model. Finally, the energy constraints and power usage have been measured by validating the particular formula gained from the device utilization. Hence, the process of the B-DES is described in algorithm 1.

Results and Discussion
The planned model is checked in the MATLAB environment, and the robustness verification has been performed in the FPGA platform. The computational cost is the most advanced of the novel B-DES than the conventional DES. While using the multiplication model in the DES environment has reduced the computation duration up to 0.4%. Moreover, the specification of the execution parameter is tabulated in Table 1.
The FPGA waveform has been visualized in Fig. 5. Also, the processor used to value the designed cryptosystem is SOC_rfcapture. In addition, the utilized CPU clock rate to perform the crypto function is 1000 MHz. The recorded latency score for the process read and write is five clocks.

Fig. 5 FPGA waveform of B-DES
The signal waveform of the input and output data is described in Fig. 6. Here, the input and output data wave has verified a similar amplitude. Hence, it was proved that no attack threats happened in the communication medium. Moreover, the designed scheme is verified with the FPGA module in the MATLAB environment. Here, the blue line indicates the input data, and the rose color line determines the output data.
Here, three waveforms have been described in Fig. 6. Here, the signal frequency of plain, cipher, and de-cipher text are compared. Considering the plain text signal, there is a major signal variation in the cipher text signal; this verified that the designed

Case Study
This case study has been elaborated to check the function of the developed novel B-DES encryption model. Moreover, the image data is taken as the input of the designed novel B-DES model. Hence, the taken input image, encrypted image, and decrypted image are determined in Fig. 8.
After importing the image data, the histogram of the images was calculated, which is described in Fig. 9. The histogram has been measured for the original and the encrypted image. Moreover, the histogram values have differed based on the image's present features. For example, if the '0' is set as the feature, then the histogram values differ for the Fig. 8 Input, encrypt and decrypt image Fig. 9 Image histogram data zero's bits. In the initial phase, after the image training, the binary bits were extracted then for the encryption, that extracted binary bits were taken into account.
The correlation of the images was determined based on the present features; in the B-DES, the value one is taken as the Bernoulli polynomial value; then, for the concatenation process, the same XOR-ed output is again added. The results of this process are considered cipher text. Then for the decryption process, the concatenated Bernoulli data is subtracted from the cipher text then the XOR process is reversed to gain the plain bits.
The recorded encryption duration of the image is 84.7 ms. Moreover, the designed B-DES model is suitable for normal and visual graphics data. The correlation of the input image is described in Fig. 10.
A high UACI/NPCR value is commonly interpreted as great resistance based on the malicious events variations. Moreover, it is unclear how high UACI/NPCR must be for the image cipher to have a high range of security. Moreover, to gain the highest UACI/NPCR, here Bernoulli concepts have been introduced in the DES model. In addition, the gained NPCR of the designed B-DES is 99.67%, and UACI 18.1%.

Comparison Assessment
A comparative analysis has been performed to measure the designed model's improvement score. The parameters considered for this comparative analysis are delay, energy usage, power, and energy consumption. In addition, a few existing approaches were considered for this comparative assessment: AES, PRESENT, DES, SIT, KATAN, and ELCM [36].

Delay Assessment
Delay is an important parameter for digital applications, especially for FPGA models. Hence, the metrics delay has been measured. This delay is the required time to send the data from the source to the destination. The scheme AES has observed the delay score as 11.98 ns, the model PRESENT has recorded a 10.34 ns delay, the conventional DES has recorded the delay range as 21.1 ns, the SIT approach has earned a delay score of 7.6 ns delay, the KATAN scheme has gained the delay measure as 8.5 ns, and the method ELCM has obtained the delay score as 5.4 ns. Considering all these methods, the proposed B-DES has recorded the mitigated delay score as 3.43 ns; these statistics are detailed in Fig. 11.

Memory Usage
The required resources and space estimation are the FPGA applications' chief parameters. Based on the CPU requirements, the execution process has differed. If the required memory spaces are too low, it results in less execution time and computation costs, like energy and resource usage. If the model needed more memory to execute the process, it would have resulted in a high execution time.
The RAM size has been calculated after performing the crypto process to measure memory usage. The model ELCM has recorded the RAM usage as 0.9 kB, the KATAN scheme has recorded 1.3 kB, the approach SIT has used 1.1 kB, the DES crypto scheme has utilized 4.6 kB memory RAM, the PRESENT model has utilized 1.3 kB RAM, and

Power Consumption
Evaluating energy usage is the crucial metric to estimate the robustness of the designed crypto model. If the model takes more resources, it takes more energy to execute the process. Also, if the data is too complex, the time taken for the encryption process becomes high, resulting in a wide range of energy consumption. Here, the consumed energy has been validated in terms of pica seconds/bit. Hence, the recorded energy consumption is 10 pica s/bits. The assessment of comparison is tabulated in Table 2.
Estimating power utilization is the chief parameter for hardware-based applications. Here, the metrics power has been validated in terms of mW. The comparison of the power utilization is graphically detailed in Fig. 13.
The obtained power consumption by the AES is 290 mW, the PRESENT model has recorded the power utilization score as 240 mW, the approach DES has recorded the power utilization score as 267 mW, the power utilization recorded by the model Sit is 221 mW, the method KATAN has measured the power usage as 234 mW, and the model ELCM has measured the power consumption score as 202 mW. Considering all these validations, the proposed B-DES has recorded the power usage score as 193 mW.

Robustness Analysis
In addition, different attacks have been considered to measure the security range of the designed cryptography, and the function of the proposed novel B-DES has been noted. Hence, the obtained security attacks for the testing process are Brute force Attack (BFA) [37], Known plain-text Analysis (KPA) [38], Chosen-Plaintext Analysis (CPA) [39], Man in Middle Attack (MITM) [40], and Ciphertext analysis (CA) [41]. The result gained by launching different security attacks is described in Table 3 and Fig. 14. After launching the attack, there is a slight variation, like 2-3%, which does not affect the security of the communication channel. Moreover, the attained low confidential score 97%, it has justified the security robustness of the proposed model.
In all comparison validation, the presented model has recorded the finest outcomes than the other compared model. The usual cryptosystem is not secure in all cases due to the vulnerability and harmfulness of malicious events. So, the multiplication model has been implemented along with the crypto model to enrich the security parameters. This process has led to gaining the finest performance score for all metrics.

Discussion
From the comparison assessment, the proposed B-DES has determined the finest results; the recorded total execution period is 0.213 s. The conventional DES has recorded 0.6565 s for executive functions. While considering the other conventional DES, this encryption period is very less, which has proved the proficiency of the designed novel B-DES model. In addition, the designed B-DES model is supported for digital privacy applications in all fields to secure people's data in the cloud. In the future, incorporating the optimization module will be helped to reduce the energy utilization of the FPGA module. The overall performance of the B-DES and DES is described in Table 4. The DES framework has also designed the weak bits that have tended to cause brute force. This can degrade the entire security parameters and has reduced the confidentiality rate. Hence, the Bernoulli multiplication function was introduced in the DES architectures to avoid weak bit generation and to reduce privacy issues. Hence, the proposed B-DES has gained the finest outcome than other models. From all metrics, the desired output has been attained; this shows the stability of the designed B-DES crypto model in securing digital transformation. In the future, designing the optimization model with B-DES will improve energy-optimized results.

Conclusion
The present research work has designed a novel B-DES for the digital application to secure the data against brute force attacks. Finally, the designed model performance is validated in the MATLAB felid programmable gate array. Furthermore, the comparative analysis of the designed B-DES with other associated models has verified the improvement score of the designed model by earning less power and memory usage. Hence, the proposed model is suitable for securing data from unauthorized users for digital applications. In addition, compared to the Conventional DES model, the B-DES has recorded a 0.4% less execution time. So, the designed multiplication model is required in the DES system to maintain a high confidential rate between the users. Also, the designed cryptosystem is suitable for all digital privacy applications by incorporating specific application process parameters. However, designing the multiplication model in the crypto process is more complex and requires more time for multiplication. In the future, implementing the Boolean expression in the crypto model will provide a better privacy range with less design complexity score.