A Novel Approach for Design and Investigation of Dual Material Stack Gate Oxide TFET using Oxide Strip Layer Mechanism


 In this paper, for the first time, we use a distinctive approach based on oxide strip layer in dual material stack gate oxide-tunnel field-effect transistor (DMSGO-OSL-TFET) to improve the DC, analog/RF, and linearity performance. For this, a stack gate oxide with workfunction is considered to enhance the ONstate current (ION ) and reduce the ambipolar current (Iamb). For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms compared to other structures. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K oxide strip layer is considered on the drain side to suppress the (Iamb) whereas, a low-K oxide strip layer is used at the source junction to maximize the ION . Moreover, length of gate segments, oxide strip layer height, and thickness are optimized to achieve a better ION , switching ratio, subthreshold swing (SS) and reduce the (Iamb) which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-oxide strip layer-TFET (DMCG-OSL-TFET) shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity performance parameters such as gm3, VIP3, IIP3, IMD3 making the proposed device useful for low power switching, analog/RF and linearity applications.


Introduction
MOSFETs are widely used for low power switching, analog/RF design, and wireless communication systems. To further improve the performance and increase the packing density, the dimensions of MOSFETs are aggressively down scaling [1]- [2]. Eventually, this leads to some major issues such as high I OF F , high power dissipation, SCEs, and SS restriction of 60 mV/decade [3]- [4]. These challenges make conventional MOSFETs unfavourable for the future low power switching and analog/RF applications. To address the above problems, an alternative device structure based on quantum tunneling-FET (TFET) is considered to be one of the possible replacements of MOSFETs in low-power switching circuits due to lower (I OF F ), voltage scaling, steeper SS below 60 mV/decade and immunity to SCEs [5]- [7]. These features make TFETs more favorable for low-power energy-efficient circuits. However, the main issue of this device is inferior I ON and ambipolar behavior [8]. TFET can be used in digital complementary logic circuits and high-frequency applications if the ambipolar current is suppressed. Ambipolar current implies the flow of current for both positive and negative V GS [9]. This happens as the tunneling junction is transfered from source to drain side by applying V GS < 0 (in case of n-type TFET). Because of ambipolar current, SS degradation and the efficiency of the device for the complimentary digital logic circuits and high-frequency applications is limited [10]- [11].
The ON-current of the TFETs is inferior due to inadequate tunneling rate (BTBT) at the tunneling junction. In TFET, higher lateral electric field across the source junction is required to lower the tunneling barrier width. As per the Wentzel-Kramers-Brillouin method, the BTBT probability depends exponentially on the width of the tunneling barrier, effective bandgap, effective mass of charge carrier, and the energy band overlap [24].
In recent literature, researchers have made numerous efforts and proposed different methods to suppress the ambipolar current, improve the DC, analog/RF and linearity performance. Raad et al. [12] proposed a TFET based on hetero dielectric and workfunction engineering (HGD-DW TFET) and reported an I ON /I OF F ratio of (9.8×10 11 ), g m of 0.290 mS, f T as (∼ 59.6 GH Z ). Kondekar et al. [13] proposed TFET based on electrically doping (ED-TFET) to enhance the analog and radio frequency performance and reported an I ON /I OF F ratio of (∼ 10 12 ), g m as 1.02 mS, f T of (190 GH Z ). Nigam et al. [14] proposed a charge plasma based TFET (DMCG-CPTFET) and obtained an I ON /I OF F ratio of (∼ 6 ×10 12 ), I amb as 1×10 −17 (A/µm), f T of (∼ 28 GH Z ). Ashita et al. [15] investigated a inverted-C TFET (ICTFET) with SCOPs which provides both lateral and vertical tunneling to boost the ON current. The authors have reported I ON /I OF F ratio of (4.5×10 9 ), SS of (48 mV/decade), f T of (1.19 GH Z ). Chandan et al. [16] proposed a metal strip based TFET (MS-ED-TFET) to overcome low switching ratio, SS and analog/RF performance and acheived an I ON /I OF F of (8.92×10 8 ), SS of (8.07 mV/decade), g m of 0.007 mS, f T as (0.17 GH Z ). Shaikh et al. [17] presented a quadruple-gate TFET with drain engineering (DE-QG-TFET) and acheived an I ON /I OF F ratio of (1.79 ×10 12 ), f T of (∼ 34 GH Z ), g m of 0.261 mS, GBP of (3.9 GH Z ). kumar et al. [18] proposed a stack-gate approach TFET with dual material (DMDODG-TFET) to and reported an I ON /I OF F ratio of (5 ×10 11 ), SS of ( 18.5 mV/decade), f T of (∼ 8.8 GH Z ), g m of 0.09 mS. Joshi et al. [19] investigated an extended source TFET (ESDG-TFET) and reported an I ON /I OF F of (2.57×10 12 ), SS of (12.24 mV/decade), g m of 0.238 mS, f T of (37.7 GH Z ) To address the ON-current, ambipolarity issues, enhance the analog/RF and linearity parameters, in this work, a novel device structure named dual-material stack gate oxide-oxide strip layer TFET (DMSGO-OSL-TFET) is proposed. The (φ 3 < φ 2 ) workfunction and high-K oxide strip layer at the drain junction leads to an increased tunneling barrier width and reduced lateral electrical field, as a result, ambipolar current reduces when negative V GS is applied. Similarly, (φ 1 < φ 2 ) work function and the low-K oxide strip layer at the source-channel junction reduces the tunneling width (λ) and increases the lateral electric field, which results in an improvement in tunneling current. This paper is organised as follows: The structural and Simulation details of the device is discussed in section 2. Structural optimization details are presented in Section 3. DC, analog/RF and linearity performance is discussed in section 4. Lastly, the conclusions of this work is summarised in Section 5.
2 Device structure, parameters and simulation models  Table 1 presents the device parameters and dimensions used in the simulation. The length of the stack gate is considered 50 nm with SiO 2 layer thickness of (0.8 nm) and Hf O 2 oxide layer thickness of (1.2 nm) [18]. Further, the entire gate is split into three segments labelled as tunnel gate (M 1 ), control gate (M 2 ) and auxiliary gate (M 3 ) with lengths (L 1 , L 2 , L 3 ) and work functions (φ 1 , φ 2 , φ 3 ) respectively. In the case of single-material stack gate oxide-oxide strip layer-TFET (SMSGO-OSL-TFET) the gate work functions (φ 1 = φ 2  [20]. In DMSGO-TFET without oxide strip layer I ON /I OF F is noted as 2.25×10 11 . A low-K oxide strip layer is considered at the tunneling junction to increase the I ON . Whereas, a high-K oxide strip layer at the drain junction to lower the I OF F . Due to this, I ON /I OF F is noted as 2.83 ×10 12 in the proposed device using TCAD device simulator. The nonlocal BTBT model is considered which uses the Wentzel-Kramers-Brillouin method to measure tunneling probability across the junction. Shockley-Read-Hall model is enabled to consider minority carrier recombination effects for numerical solutions. Bandgap narrowing (BGN) model is used due to heavily doped concentrations in source and drain regions, FLDMOB mobility model is used to consider the velocity saturation effects because of lateral electric field. The simulation study carried out in this work uses a nonlocal BTBT model that is calibrated with the data reported in [8], which was previously calibrated, with the experimental data obtained from the fabricated device [21]. Fig. 2 shows the comparison of results reported in [8] and the simulated results of the proposed device using TCAD. The propoed device can be fabricated using the similar method reported in [26].

Workfunction optimization Results
To align the band structure at the junctions and to modulate the carriers through the channel, the entire and changing (φ 2 ), better switching ratio and minimum ambipolar current is observed for the combination (φ 1 = φ 3 < φ 2 ) as illustrated in Fig. 3(a) and table 2. , it can be seen that tunneling width increases with an increase in (φ 2 ). This results in band overlap decrease on the source side, which results in a decrease of tunneling current. Whereas the band overlap has been noted at the drain junction for (φ 2 > 4.4eV) and tunneling is observed in the OFF state, also (φ 2 ) workfunction variation in the ON-state does not shows a significant change of the tunneling current until the workfunction (φ 2 = 4.4 eV). Also, a band overlap decrease is seen for (φ 2 > 4.4 eV), which results in a decrease in ON current (I ON ) as shown in Fig. 3(a).

Oxide strip optimization results
To further improve I ON and minimize the ambipolar current, optimized oxide strip layers are inserted at the source and drain junctions. Fig. 4(a) shows the comparative I DS -V GS variation for different oxide strip materials in DMSGO-OSL-TFET. It was noted that the combination of low-K oxide strip (air) at the tunneling junction and high-K oxide strip (Hf O 2 ) at the drainchannel interface shows higher I ON and minimum ambipolar current because of tunneling width and band alignment at the junction. Fig. 4(b) shows I DS -V GS variation in DMSGO-OSL-TFET with oxide strip heights at the tunneling junction by fixing the oxide strip on the drain side. It has been noted that a strip of 4 nm height at the tunneling junction shows better I ON because of higher electric field and decrease in tunneling width. Similarly, as shown in Fig. 4(c), fixing the height of low-K oxide strip and varying the high-K oxide strip, it was observed that at the drain channel junction, the oxide strip of 4 nm height shows minimum ambipolar current with a higher ratio of I ON /I OF F . Fig. 4(d) shows the comparative I DS -V GS characteristics in DMSGO-OSL-TFET for different oxide strip thickness. It was noted that oxide strip thickness of 2 nm at the tunneling junction shows better tunneling current I ON and minimum ambipolar current due to the band alignment.

Gate length optimization
In this section, the gate segments of the proposed device is optimized. In this regard, Tables III-V shows the variations in I ON , I OF F , I amb , I ON /I OF F for various combinations of L 1 , L 2 and L 3 . The optimization of L 3 at constant L 1 = 10 nm is shown in Table III. Further, the optimization of L 1 at constant L 3 = 15 nm is shown in Table IV. Table V shows the L 1 and L 3 variations at L 1 = L 3 . From this analysis, it has been noted that L 3 = 15 nm performs better in terms of I ON , I OF F , I amb . However, L 1 = L 3 = 10 nm shows  better results in terms of I ON /I OF F and is considered for further analysis.
For an optimized oxide strip layer shown in Fig.  1 based on (φ 1 , φ 2 , φ 3 ) combinations, various structures for the device are formed, as presented in Table  6. Further, a comparative analysis among these devices is done in terms of their carrier concentration, band diagrams, tunneling rate, surface potential, electric field variation, and I DS -V GS characteristics. For SMSGO-TFET, all the three workfunctions (φ 1 , φ 2 , φ 3 ) of the gate material has been considered equal (4.4 eV). Fig.  5(a) shows the comparative carrier concentration variation with distance. Higher electron concentration is observed in the case of DMSGO-OSL-TFET, due to this a decrease in tunneling width and an increase in tunneling rate is observed as shown in Fig. 5(b) and Fig. 5(c). Further, an increase in surface potential is observed in DMSGO-OSL-TFET, shown in Fig. 5(d). Due to the oxide strip layer at the tunneling junction, maximum electric field is observed at this junction as shown in Fig. 5(e). Thus, maximum tunneling occurs in this region, as the BTBT rate (G BT BT ) at the tunneling junction depends on the electric field (ε) leads to an increase in BTBT rate as per the expression [22].
Where A, B are constants which are related to the electron's effective mass and the tunnelling probabil-     ity, ε is the electric field and σ is the transition constant. Further, the probability of tunneling of the carrier (T W KB ) at the tunneling barrier is analyzed by the approximation of Wentzel-Kramer-Brillouin (WKB) [23].
Where m * is the effective mass of an electron, q represents the electron charge, h represents Plank's constant, E g is the effective bandgap, λ is the width of tunneling barrier, and ∆φ represents the energy overlap where the tunneling occurs. Therefore, as shown in Fig. 5(f), a significant increase in tunneling current is observed. Fig. 5 and Table 7 show that DMSGO-OSL-TFET performs better than other device structures.

DC characteristics
In this section, comparative DC characteristics of DMCG-TFET, DMCG-OSL-TFET, DMSGO-TFET and DMSGO-OSL-TFET has been analyzed. Because of the oxide strip layer, reduced V T , an improved ON-state current, reduced ambipolar current, and a higher switching ratio (2.83×10 12 ) was observed in DMSGO-OSL-TFET compared with DMCG-OSL-TFET due to decreased tunneling distance and improved lateral electric field across the tunneling junction. The electric field variation with distance is shown in fig. 6(a), a higher electric field at the tunneling junction is noted in DMSGO-OSL-TFET, which decreases the tunneling barrier width as shown in Fig. 6(b). This results in a significant increase in drain current, as illustrated in Fig. 6(c). Fig. 6 and Table 8 shows that DMSGO-OSL-TFET performs better than the other structures. Fig. 6(d) shows the comparative output characteristics plot at V GS = 1 V. From the figure, it can be noted that the tunneling current I DS rises and then saturates because of velocity saturation as V DS increases from 0 to 0.8 V. The tunneling current does not change substantially from V DS = 0.8 V onwards, so the current remains constant. Furthermore, due to the better coupling, increase in an electric field and decrease in tunneling barrier width, higher I ON is noted for DMSGO-OSL-TFET relative to DMCG-OSL-TFET with SiO 2 gate oxide.

Analog/RF Performance improvement
This section analyses the analog/RF parameters g m , g DS , R o , C gs , C gd , f T , TGF, Fmax, TFP, GBP and transit time. The transconductance (g m ) reflects the gain of the device, a larger g m makes the device useful for analog applications. Moreover, (g m ) plays an important role in attaining higher values of f T and GBP. Fig. 7(a) shows the comparative variation of g m with V GS at V DS = 1 V. The g m of DMSGO-OSL-TFET is noted to be maximum, because of an increase in tunneling current due to the low tunneling gate workfunction (φ 1 ), and the presence of low-k oxide strip at the source junction shows more band bending and large electric field at the source junction in comparison to the other structures. Further, it has been noted that because of an improvement in drain current, g m increases with V GS at first, then declines at a higher value of V GS due to degradation of mobility. Fig. 7(b) illustrates the comparative output conductance (g DS ) variation with the drain voltage (V DS ). Higher output conductance is preferred as it provides higher intrinsic gain. From the simulation results, higher output conductance has been noted in DMSGO-OSL-TFET due to the higher δI DS shown by DMSGO-OSL-TFET for the equal change in δV DS . Fig. 7(c) shows the comparative R O variation with V DS for constant V GS . It can be noted that lower R O is observed for DMSGO-OSL-TFET as g DS is higher. The variation of C gs and C gd obtained from small-signal ac analysis at 1MHz frequency is presented in Fig. 7(d) and Fig. 7(e). In DMCG-OSL-TFET, the minimum value of C gs is noted and in DMSGO-OSL-TFET, a significant increase of C gd is noted above V GS = 0.85 V. Fig. 7(f) shows the comparative variation of f T with V GS . It has been noted that, initially, f T increases with V GS due to an increase in g m , then decreases with V GS after reaching the peak value due to an increase in C gd and decrease in g m due to mobility degradation. From the simulation results, a higher f T Fig. 7 Comparative performance of (a) gm

DMSGO-TFET and DMSGO-OSL-TFET
is obtained for DMSGO-OSL-TFET which shows that the proposed device structure is more favourable for radio frequency applications. The f T of the device is described as per the expression [24].
The GBP is one of the crucial parameter for assessment of the radio frequency performance of the device, for a specified dc voltage gain of 10, it is calculated using the expression [24].
The GBP variation with V GS is shown in Fig. 8(a). It can be seen that GBP initially increases as the gate voltage increases, but it decreases for higher gate voltages due to mobility degradation. In DMSGO-OSL- TFET, due to g m and C gd at lower gate voltages, a high increase in GBP is observed. The TGF parameter indicates how efficiently the current reaches a certain transconductance value. Fig. 8(b) shows the TGF variation with V GS . In DMSGO-OSL-TFET, higher TGF is observed at lower V GS and with increase in V GS it decreases as the variation in I DS is small. The TGF is obtained as follows Fig. 8(c) shows the variation of TFP with V GS . It can be noted that DMSGO-OSL-TFET has higher TFP due to high g m and f T . The TFP is obtained as follows The variation in transit time (τ ) with V GS is illustrated in Fig. 8(d). It is the time taken by the carriers to move from the source side to the drain [20]. A decrease in the transit time is observed, with an increase in V GS due to an increase in f T . Also, the minimum The maximum operating frequency (f max ) is another crucial parameter for an radio frequency performance analysis. It is calculated by using the equation Here, R gd represents the gate resistance. Fig. 8(e) shows the f max variation with V GS at V DS = 1.0 V. It has been  noted that DMSGO-OSL-TFET shows higher value of f max therefore used to improve analog/RF performance.

Linearity Performance improvement
In this section, we investigate comparative linearity and distortion parameters, such as g m2 , g m3 , VIP2, VIP3, IIP3, and IMD3 which has been explained in [25]. These are defined as follows: Fig. 9(a) and Fig. 9(b) shows comparative plots for g m2 and g m3 variation with V GS . The third-order harmonic defines the lower bound of distortion. Fig. 9(b) shows the comparative variation of g m3 with V GS . The peak value of g m3 can be seen at lower V GS in DMSGO-OSL-TFET in comparison with other devices. Fig. 9(c) shows the comparative variation of VIP2 with V GS at V DS = 1.0 V. A higher VIP2 needed for minimal distortion operation. Further, it can be noted that the VIP2 of DMSGO-OSL-TFET is higher than the other structures due to stack gate, dual gate and oxide strip. The higher VIP3 value indicates a more linear device. Fig.  9(d) shows the comparative VIP3 variation with V GS at V DS = 1.0 V. It has been observed that VIP3 of DMSGO-OSL-TFET is higher than the other structures. IMD3 originates from the non-linearity characteristics of I DS -V GS and seems to be a distorting signal in wireless systems. Devices with lower IMD3 values can have the ability to withstand higher signal distortion. Fig. 9(e) shows the comparative IMD3 variation with V GS at V DS = 1.0 V. Further, IMD3 of DMCG-TFET is noted to be the smallest, indicating that the DMCG-TFET intermodulation distortion performance is the best of the above devices. The higher IIP3 value shows the device is more linear. Fig. 9(f) shows the comparative IIP3 variation with V GS at V DS = 1.0 V, it has observed that the VIP3 of DMSGO-OSL-TFET is much higher than that of other devices.

Conlusion
The DMSGO-OSL-TFET with oxide strip layers at the drain and source junctions is proposed. The structural parameters like gate lengths (L 1 , L 2 , L 3 ), work functions (φ 1 , φ 2 , φ 3 ), oxide strip height and thickness are optimized to achieve better switching ratio and reduce the ambipolar current. The performance of the proposed device is analyzed using TCAD device simulator. Finally, a comparative performance analysis of the proposed device is done with other device structures and noted the combination of low-K and high-K oxide strip layers at the source and drain junctions and workfunction combination (φ 1 = φ 3 < φ 2 ) on the stack gate oxide in the proposed device shows significant improvements in I ON /I OF F , SS, g m , f T , R O , transit time (τ ), GBP, TGF, TFP, F max , VIP2, VIP3, IMD3 and IIP3 given in table 8. The performance of the proposed device is compared with the recent literature shown in table 9 which shows that the proposed device useful for low power switching, high frequency and linearity applications.
Author contributions: 1. Kaushal Nigam -Concept and methodology 2. Dharmender -Resource, simulation Availability of Data and Material The data and material concerned to the manuscript may be made available on request.

Declarations
The manuscript follows all the ethical standards, including plagiarism. Consent for Publication Yes. Consent to Participate Yes. Conflict of Interests No conflicts of interest.