A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied with respect to different LER parameters, aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.


Introduction
In nano-scale CMOS analog circuits, mismatch between the drain currents of two identical transistors placed adjacent to each other is attributed to few major causes like random discrete dopant effect (RDD), line edge/line width roughness (LER/LWR), metal gate granularity etc [1]. The line edge roughness (LER) phenomenon arises due to i) subwavelength lithography and/or ii) intrinsic non-uniformity of the photoresist used in the process technology [2]. LER leads to variation in critical dimension of the feature size. The amplitude of roughness (σ LER ) remains almost same and does not scale down with technology. Therefore, as the device dimensions, especially the channel length and width

Literature Survey and Motivation
In literature, the LER phenomenon has been studied primarily from two perspectives, i) its process level mitigation and ii) its impact on device performance. Several alternative patterning methods like extreme ultra violet lithography (EUVL), electron beam lithography (EBL), mask-less lithography, nanoimprint lithography etc. are being considered for enhanced resolution of the device dimension [4]. On the other hand, modeling and simulation of roughness and its impact on MOSFET, DGFET, FinFET etc. device performances have also been widely studied and reported. The variability impact of LER on sub 32 nm FinFET technologies is investigated from both device and circuit level perspectives using computer-aided design simulations in [5]. In [6] impact of LER along with other variability sources are reported for a Tunnel FET. A 3-D quasi-atomistic simulation methodology for LER in nonplanar devices, like FinFETs and gate-all-around (GAA) FETs, is proposed in [7]. The work reported in [8], describes the LER induced V T variability for 14 nm underlap FinFET using 3-D numerical simulations. For a better understanding of the performance variability induced by LER, modeling of the performance variability becomes indispensable. A tapered fin percolation model (TFPM) for evaluation of V T variability due to fin edge roughness (FER) of a FinFET is formulated in [9]. The model is based on a number of stochastically generated tapered fin structure with a minimum, maximum and average fin width. It can accurately capture the impact of associated physical parameters on V T variability. The model is extended for the formulation of drain current variability due to FER for a FinFET in [10]. On-current, off-current and sub-threshold slope variability due to FER are reported as well. Another model for V T variability formulated for a double gate MOSFET is reported in [11]. Unlike the previous one this model is physics-based and premises on the solution of 2D Poisson's equation. Here LER induced fluctuation occurs in the silicon body thickness. However neither of the above works give any compact model of V T or I D variability.
The major motivation behind undertaking the present research work is the lack of a suitable physics based compact drain current local variability model which incorporates the effect of line edge roughness on statistical fluctuation of the channel length.

Outline and Contribution of our Work
An EδDC transistor is a device structure proposed by us which is reported to be a low-power, low-cost transistor, suitable for SoC applications with controlled process variability effects due to random discrete dopant effects [12][13][14][15][16][17]. In the present work, we derive a physics based local drain current variability model of an epitaxial delta doped channel MOS (EδDC) transistor, caused due to random fluctuation of channel length, attributed to the LER/LWR phenomenon. The theoretical formulation of the model is based on the principle of propagation of variance. Assuming small fluctuation, first order Taylor's series is considered. The process varying parameters are i) channel length, ii) threshold voltage (V T ), and iii) effective mobility. V T variability is induced due to channel length fluctuation and effective mobility varies due to fluctuating velocity saturation effect. The model predicted results are verified through calibrated technology computer aided design (TCAD) simulation platform. The model is verified for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied aiming reduction of drain current variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.
The local drain current variability is high when the transistor operates in the weak inversion mode (WI), compared to when operates in the strong inversion (SI) mode. In WI mode, local drain current variability depends on two factors, i) on channel length variability itself and ii) correlated V T variability. In SI mode, correlated effective mobility fluctuation component is also present apart from the components present in WI mode. As velocity saturation effect is more pronounced at high drain bias it contributes to the increased drain current variability at high drain bias apart from V T variability component.
The major salient features of our variability compact model are: (i) The formulation of the model is based upon the principle of propagation of variance, which is a formal theory of mathematical statistics. Our model encapsulates the device architecture through the use of appropriate compact model of the device architecture. By re-definitions of few device parameters, the model may thus easily be extended to other device structures such as SOI structures, which we have shown in this work. (ii) The present model of local drain current variability being a compact model gives an insight on the minimization approaches of variability through device design and optimization. (iii) The model does not involve purely empirical parameters.

Organization of the Work
The model of the σ I D is derived in Section II, where we recall σ V T formulation from previous work in brief. The verification the model with calibrated TCAD simulation results and the approaches for reduction of σ I D is discussed in Section 3. The extension of the model for SOI transistors and its validation with reported data are also mentioned in Section 4. Finally Section 5 concludes the paper.

Background Information
The cross-section and channel doping profile of the nchannel EδDC transistor are as shown in Fig. 1 and Fig. 2. The significance of the various symbols used to represent the channel doping profile are as used in [18].
The threshold voltage for a short channel transistor, in the presence of the applied drain bias is written as [19], where V T l is the long channel threshold voltage, V bi is the built-in potential across the S/D junctions, ψ s = 2Φ F is the surface potential at strong inversion and l t is the characteristic length. Using the principle of propagation of variance, random V T variability due to channel length fluctuation is given by [18], where threshold voltage sensitivity w.r.t. channel length is obtained using (1) as follows.
Due to the presence of LER/LWR, the average channel length of a transistor, becomes a random variable. σ L represents the variability of average channel of a transistor. Line edge roughness, and hence, σ L induced by LER is defined by correlation length Λ and the rms roughness amplitude σ LER , as follows [20][21][22]. Here we assume uncorrelated edge variation, which gives channel length variability as follows [6,23],

Formulation of Drain Current Variability
The drain current I D of a MOS transistor is related to several process parameters, which is mathematically represented by whereP represents the vector of process parameters. Also we assume that the deviation/fluctuation in a certain parameter, symbolized as δP i is much smaller than the value of the parameter P i itself. Therefore, we employ first order Taylor's series expansion to write The distribution of drain current samples for large number may be approximated to be a normal distribution, characterized by sample mean and standard deviation. The dispersion characteristics being more important in characterizing the variability aspect, we work with this parameter in our present work. From (6) the variance for three input parameters is written as Here the factor ρ characterizes the correlation between the input parameters. For perfect correlation, which occurs when the parameters are analytically related, the value of the correlation coefficient may be assumed to be unity.
The choice of each of the process parameter P i is based upon physics of the transistor. The sensitivity of the drain current with respect to these process parameters may be evaluated either through simulation method or through analytical method. In our work, we prefer the later and select appropriate compact model to describe the relationship between the drain current and the chosen process parameters.

Drain Current Fluctuation through Charge based Model
EKV drain current model, which smoothly describes the device operation in all the modes of operation is used to analyze drain current variability induced by LER/LWR [24,25]. The average value of drain current is given as, is called the specific current, and i f and i r are normalized forward and reverse currents with the normalization factor as I S . n, C ox , μ eff and φ t are the slope of gate-to-body voltage versus surface potential graph, the gate oxide capacitance per unit area, the effective mobility and the thermal voltage respectively. i f/r is as follows.
Here V P is the pinch-off voltage, approximately written as, Here, source being the reference terminal, V S = 0. Normalized fluctuation of drain current due to L fluctuation and correlated V T and μ eff fluctuations thus becomes, The forward and reverse current derivatives w.r.t. V T referred in (11) are evaluated as follows.
where, ∂V P ∂V T = − 1 n . In (11) both μ eff and V T fluctuation roots from channel length fluctuation. Hence they are correlated.
If we now investigate (11), we see that the second term is independent of the bias region. The third term consisting of interpolation function, takes the corresponding limiting forms in different bias regions. The first term, i.e., mobility fluctuation needs a close inspection w.r.t. the nature of inversion region.

Drain Current Variability in Weak Inversion (WI) Mode
Velocity saturation effect being insignificantly small, can be neglected here. Hence, μ eff = μ s , where, μ s is the surface mobility. In WI mode, surface mobility is solely dependent on Coulomb scattering of the carriers. i) The ionized impurity atoms present in the channel and ii) the remote fixed charges existing inside the high-k dielectric (Remote Coulomb Scattering or RCS effect) act as the scattering centers. For low normal electric field, the inversion carriers experience surface mobility as follows [26] 1 Here, RCS effect is embedded in μ 00 and it is termed as the zero field mobility. Coulomb scattering with the impurity atoms is represented by the term α d .Q imp , α d being the Coulomb scattering parameter. However, channel length of the transistor does not have any impact on the scattering phenomena. Hence surface mobility fluctuation term on R.H.S. of (11) vanishes.
Thus normalized variance of drain current in weak inversion mode is thus given by (16).
The last term in (16) is the correlation coefficient. The current sensitivities are calculated using (12) and (13).

Drain Current Variability in Strong Inversion (SI) Mode
In strong inversion (SI) mode, The effective mobility is [25] μ eff = μ s here μ s represents the surface carrier mobility and v sat represents the saturation velocity of the inversion carriers.
To evaluate fluctuation of μ eff , in SI mode, we refer to (17), which on partial differentiation w.r.t. L, gives, In this mode of operation, surface roughness scattering and lattice vibration dominates surface mobility [27]. An efficient surface mobility model which includes the mobility degradation effect is as follows.
Here θ 1 and θ 2 are the parameters to account for the mobility degradation effect [28,29]. μ 0 represents low field mobility of the inversion carriers, which includes both the Coulomb scattering effects as mentioned in the previous section. In presence of the series source/drain (S/D) resistance mobility degradation parameter θ 1 is modified as [28] Here, θ * 1 is the coefficient of mobility degradation in absence of source/drain resistance and R SD is the source/drain series resistance. The values of the mobility degradation coefficients are extracted from extensive TCAD simulation.
The normalized drain current variability due to channel length fluctuation in SI mode is thus given by (21).
The last three terms in (21) represent the corresponding correlation coefficients. The current sensitivities are calculated using (12) and (13). Effective mobility variability is derived using (18) as,

Device Simulation
The n-channel EδDC MOS transistor parameters are selected for high performance applications according to the International Technology Roadmap for Semiconductors 2010 version. The models for different physical effects are included in the simulation as discussed in [13,17]. The channel length varaibility due to LER is simulated using monte carlo simulation for 200 samples. The channel length of 200 EδDC transistors are normally distributed around its nominal value (here 16 nm) with a spread of σ L . The value of σ L is calculated for a particular set of Λ and σ LER values using (4).

Variation of Local Drain Current Variability with Bias
As the transistor moves from weak inversion (WI) mode to strong inversion (SI) mode, the variability gradually decreases, as can be seen from Fig. 3. This is due to the fact that the deterministic drain current (I D ) is less by several orders in WI mode compared to SI mode. This leads to the nature of variation of normalized drain current variability even for similar fluctuation σ I D over the entire gate bias range. As evident from (16) In the weak inversion mode (WI), the local drain current variability depends upon three factors: the channel length variability, the threshold voltage variability and the correlation factor. Since the channel length variability term is bias independent, the drain bias dependence comes from the remaining two components. Moreover, we observe that higher drain current variability is more pronounced in WI mode compared to strong inversion (SI) mode. Though σ V T is independent of the bias mode (weak or strong), the higher drain current variability for high drain bias at WI mode, compared to SI mode results from exponential drain bias dependence of inversion charge at drain end in WI mode compared to its linear drain bias dependence in SI mode [25].
However, as we can see from (21), in SI mode, correlated effective mobility fluctuation component is also present apart from the components present in WI mode. As velocity saturation effect is more pronounced at high V DS , it contributes to the increased drain current variability at high drain bias apart from V T variability component. An important point for EδDC transistor may be noted here. We reported in our earlier works [13,17], that the threshold voltage variability at high drain bias is not much significant. The excellent agreement between TCAD simulation and analytical results confirms perfect capture of bias dependence of the model.

Local Drain current Variability for different LER profile parameters
In Fig. 4a, the variation of normalized local drain current variability due to random variation of channel length is reported for low drain bias and for a range of σ LER values. For this observation Λ is kept fixed at 5 nm. With increasing σ LER , channel length variability increases linearly following (4). Increased channel length variability induces increased V T variability and hence normalized drain current variability due to channel length variability enhances. A similar variation is reported in Fig. 4b for high value of drain-to-source voltage. As discussed in a previous subsection, we see here that nature of the graphs remaining similar to those at low V DS , variability values are higher for high V DS , which is a consequence of higher σ V T for high V DS .
The nature of graphs given in Fig. 4a and Fig. 4b are not only physically justified, but also this physics is perfectly incorporated in the model. This is evident from the very close agreement of the simulation and the model predicted results. Figure 5a represents the variation of normalized local drain current variability due to random variation of channel length for low drain bias and for a range of Λ values. For this observation σ LER is kept fixed at 1 nm. With increasing Λ, channel length variability increases following (4). Increased channel length variability induces increased V T variability and drain current variability. However, this enhancement is significant in WI mode of operation. A similar variation is reported in Fig. 5b for high value of V DS . Here also σ I D values are higher for high V DS as correlated σ V T increases with increasing drain bias. Here the scalability of model is verified with LER correlation length Λ.

Reduction of Drain Current Local Variability through Channel Engineering
σ I D due to variability of channel length induced by LER can be controlled in an EδDC transistor using channel engineering technique. This technique involves the study of variability performance with variation in the profile parameters using analytical model. Here we make all the observations for high drain bias and for a fixed LER profile (Λ=5 nm & σ LER =3 nm), hence for a fixed channel length variability. If we have a close look at (16) and (21), profile parameter dependence of the normalized drain current variability is only associated with the V T variability component. In the following discussion we would refer to our observation obtained in [18].

Variation with x 1
In Fig. 6a, we observe the variation of σ I D /I D with gate bias for several epitaxial layer thickness x 1 . As we are Fig. 4 Variation of normalized drain current variability with applied gate bias for various edge roughness amplitude at L = 16nm at a Low V DS and b V DS Fig. 5 Variation of normalized drain current variability with applied gate bias for various correlation lengths at L = 16nm at a Low V DS and b High V DS studying this section for fixed channel length variability, correlated V T variability differs with change of profile parameter values. With increasing thickness of the low doped layer x 1 , depletion depth, W dm increases. Increased W dm , worsens short channel effect (SCE) [15]. In case of poor SCE, V T will be more sensitive to variation in channel length, leading to higher ∂V T ∂L . Hence, σ V T increases with increasing x 1 . Consequently the contribution of V T variability associated component of normalized drain current varibility increases and hence σ I D /I D goes up. It is observed that as x 1 increases from 5 nm to 15 nm, σ I D /I D becomes three times larger for V GS =0.1 V. However this increment lowers as the transistor approaches SI mode of operation. Figure 6b shows the variation of σ I D /I D with gate bias for several epitaxial layer doping N s . With increase of epitaxial layer doping, the short channel effect is controlled, hence the maximum depletion depth and consequently σ V T is restricted. Lowering of σ V T in-turn lowers σ I D /I D with increasing N s . The maximum improvement of σ I D /I D is by 8.5% which occurs for V GS = 0.1V . The improvement gradually diminishes with increase of gate bias and becomes insignificant as the transistor enters in SI mode. Figure 6c shows the variation of σ I D /Ī D with gate bias for several screening layer doping N p . Increase in N p restricts the spread of depletion region beneath the channel. Controlled channel depletion makes SCE better. Hence V T variability and drain current variability with random variation of channel length is reduced with increasing N p . However, minimum value of channel depletion is limited by x 1 , SCE and hence variability due to random variation of channel length cannot be reduced indefinitely. Consequently, we see in Fig. 6c, σ I D /I D does not reduce significantly, for N p ≥ 5 × 10 19 cm −3 .

Variation with N p
In the above observations we find that the impact of all the three profile parameters on drain current variability becomes insignificant as we enter in SI mode. This is because, in SI mode correlated effective mobility fluctuation plays a key role which is independent of channel profile.

Correlation between normalized drain current variability and threshold voltage variability
It is seen from the drain current variability model, as well as discussed in 3.5.1-3.5.3, that variation of drain current variability with profile parameters, directly follows from variation of σ V T with profile parameters. In order to illustrate this correlation we select the normalized drain current variability value at a particular gate bias (say, V GS =0 V) and compare it with σ V T for similar channel profile and LER profile parameters.
It can be seen in Fig. 7, that the nature of variation of σ I off /I off with x 1 exactly follows the same for σ V T with x 1 . Similar correlations for N s and N p variations, can be observed from Fig. 8 and Fig. 9. Though the above graphs are for different correlation lengths, Λ, similar observations are obtained for different roughness amplitudes σ LER as well. The corresponding figures are Fig. 10 to Fig. 12.

Trade-off between i) channel profile parameters and ii) LER profile parameters for minimization of drain current variation
We have already discussed that adjustment of channel profile parameters of an EδDC transistor can be used to minimize the normalized drain current variability caused due to LER. However, how the channel profile parameters should be tuned to minimize the impact of LER profile parameters, needs a detailed study. For this study we observe the variation of normalized drain current variability for particular bias (say V GS = 0), i.e., normalized off current variability.
First we observe the variation of correlation length Λ for different channel profile parameter variation. In Fig. 7a, we see that σ I off /I off increases with increase in both x 1 and Λ. Hence, we can say, in order to keep σ I off /I off minimum, x 1 has to be kept as low as possible in order to compensate the effect of increase in Λ. In Fig. 8a, we see that σ I off /I off increases with increase in Λ, however, it decreases with increasing N s . Thus, we can say, we can keep σ I off /I off under control even if Λ increases, by increasing N s . However, from Fig. 9a, we can say that increase in N p keeps σ I off /I off under control when Λ increases. But beyond N p = 10 20 /cm 3 no significant variability improvement can be observed.
Next we take up the study for roughness amplitude (σ LER ) variation. A similar nature of variation of σ I off /I off can be observed as we found in the preceding section for Λ variation. In Fig. 10a, we see that σ I off /I off increases with increase in both x 1 and σ LER . Thus, in order to keep σ I off /I off minimum, lowering x 1 can compensate the impact of increased Λ. In Fig. 11a, we see that σ I off /I off increases with increase in σ LER and decreases with increasing N s . Hence to keep σ I off /I off minimum, in case σ LER increases, N s can be suitably increased. It can be observed from Fig. 12a, the nature of variation of σ I off /I off with N p is similar to that for N s variation. However, variability does not improve significantly beyond N p = 10 20 /cm 3 .

Application of the model for FD-SOI Transistor
The model derived in the present work, can be extended for UTB-FD-SOI MOSFET, with the definition of depletion depth as described in [31]. The results obtained from the extended model for SOI structure are compared with the reported results [32] of atomistic simulation results for V T variability and local ON current variability due to LER. The comparison is made for all three reported structures with different gate-oxide and body thickness. LER parameters are 3σ LER =2 nm and Λ=25 nm. The model parameters are suitably selected to match the corresponding nominal performances. The validity of the extended model is depicted in Fig. 13, where appreciable accuracy is observed for both V T and I ON variability. Hence the extended model is verified for the SOI structures. Fig. 13 Verification of the model predicted local ON-current variability result due to LER with atomistic simulation results for a UTB-FD-SOI MOSFET [32]

Conclusion
An unified model of drain current local variability due to channel length fluctuation caused by LER phenomenon is reported. The channel length variation leads to correlated variation of threshold voltage and effective mobility of the charge carriers. The drain current variability is significant in weak inversion mode compared to strong inversion mode. The variability is higher for higher drain bias (due to the presence of DIBL) irrespective of mode of operation. In the strong inversion mode, the correlated fluctuation due to effective mobility of the carriers plays an important role. Validation of the model is established by the close agreement between the model predicted results and those obtained from calibrated TCAD results. Further, extensive channel engineering approach prescribes the way for designing an optimal channel profile for the EδDC transistor with minimum V T and I D local variability due to channel length fluctuation. Correlation between σ V T and drain current variability is graphically shown and justified. Minimization of drain current variability for LER profile parameters by tuning channel profile parameters, is studied in detail.
Fine tuning of the correlation components may be included in the model by introducing a general correlation parameter, value of which may be determined from a set of measured data. We have shown the extension of our model to SOI structure. With appropriate use of compact model of nominal drain current and redefinition of some parameters, the model may be extended to tri-gate devices also. model formulation, processing and simulation of the simulated data were done by the corresponding author. Problem formulation, model development and its physical analysis was performed by the second author. The first draft of the manuscript was written by the corresponding author and was critically checked and modified by the second author. Both the authors read and approved the final manuscript.
Funding The second author thanks Department of Electronics and Information Technology, Govt. of India for financially supporting the work under the SMDP-C2SD project at the University of Calcutta.

Consent for Publication
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