Fault Detection in Multi-input Analog Circuits using Regression Modelling

doi:10.21203/rs.3.rs-1742684/v1

The aim of this paper is to detect parametric faults in multi-input analog circuits by solving for the coefficients of a polynomial regression model using traditional linear least squares techniques, with some care applied in the solution. The multi-input circuit output is expressed in terms of more than one input variables using polynomial coefficients. In the proposed approach, the value of each component of the circuit under test (CUT) is varied within its tolerance limit using Monte-Carlo simulation to calculate its fault free polynomial coefficient bounds. The CUT is then declared fault free or faulty based on the result of the comparison of its estimated polynomial coefficients with the fault free coefficients. To the best of our knowledge, parametric fault detection in multi-input analog circuits using polynomial regression modelling is attempted for the first time in the literature. The effectiveness of the proposed method is demonstrated via two case studies, namely, a lead lag circuit and the PI compensator of a peak-current-mode-controlled buck-type switching converter.

Analog circuit

Parametric faults

Analog fault detection

Polynomial regression

Monte-Carlo simulation

Due to the wide range of applications of electronic circuits in the recent years, testing of electronic circuits, especially analog circuits is a foremost problem to ensure fault free systems, as there is no simple analog fault model comparable to the digital stuck-at fault model. The accepted analog fault models [1] are catastrophic faults and parametric faults. Many literatures presents several techniques for detecting the faults in analog circuits. D. Binu et al. [2] thoroughly surveyed several high-tech techniques for fault detection and diagnosis in electronic circuits. Z. Guo and J. Savir [3] detected parametric faults in the CUT by exploiting an auto regression model to predict the coefficients of the CUT’s transfer function, followed by comparison against their precomputed bounds. Z. Guo et al. [4] also presented a similar approach to detect parametric faults in passive components of the CUT from its transfer function by imposing minimum and maximum values on the coefficients. The frequency response based fault detection was proposed by Kavithamani A et al. [5] considering the fact that the frequency response of a circuit such as bandwidth, high cutoff frequency, low cutoff frequency etc. changes in the presence of faults. Signal Flow Graph (SFG) based approach was proposed by R. Ramadoss et al. [1] for detection of parametric fault detection of linear analog circuit where SFGs are inverted, and reverse simulated with good and faulty outputs to obtain test waveforms and component tolerances. Sindia and Agrawal [6, 7] proposed a method of testing for parametric faults in non-linear analog circuits based on a polynomial representation of fault-free function of the CUT, using Taylor series expansion. The response of the CUT is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC. The test then classifies the CUT as fault-free or faulty based upon a comparison of the estimated polynomial coefficients with those of the fault-free circuit. X. Li et al. [8] presented a novel method that employs the cross-entropy between the good circuit and the bad circuit to detect component faults in analog circuits based on the autoregressive (AR) model.

In almost all literature reported so far till date, the fault detection algorithm for detection of parametric faults has been developed for single-input single-output analog circuits e.g., Sallenkey band pass filter [5, 8], low pass filter [3, 4, 7, 8], leapfrog filter [1, 3, 5] or Elliptic filter circuit [6, 7] where, the Op-amp is configured for single ended operation and the non-inverting input is grounded. In this paper, an utmost effort paid off in parametric fault detection in analog circuits where Op-amp is configured for double ended operation. Moreover, most of the practical analog circuits have limited accessible terminals for excitation and measurement of responses; hence detection of internal parametric faults is difficult. So, we adopt a strategy where we fit a polynomial regression model [9, 10] for the output function (V_out) of the circuit as a polynomial of degree n in terms of m independent input variables (voltages) Vin₁, Vin₂ …. Vinm. Classical linear least squares techniques are used to estimate coefficients of a polynomial regression model. In order to simplify the analysis, we further assume that all test measurements taken are noise-free. We also assume that the circuit does not become unstable in the presence of faults and faults occur in passive components only.

The paper is organized as follows: Section 2 outlines brief theory behind estimation of a linear regression in n-dimensions. Section 3 describes the fault detection procedure for analog circuits. Illustrations for validating the proposed algorithm are detailed in Section 4 and Section 5 concludes the proposed fault detection method.

The function of a circuit can be expressed as a polynomial using a Taylor series expansion [14] in terms of two input voltages Vin₁, Vin₂, about the point V_in1 = 0 and V_in2 = 0 as follows:

\(\begin{gathered} {{\text{V}}_{out}}{\text{=}}f({{\text{V}}_{in1}},{{\text{V}}_{in2}})=f(0,0)+{f_x}(0,0){{\text{V}}_{in1}}+{f_y}(0,0).{{\text{V}}_{in2}}+\frac{1}{{2!}}[{f_{xx}}(0,0).{{\text{V}}_{in1}}^{2} \hfill \\ +2{f_{xy}}(0,0).{{\text{V}}_{in1}}.{{\text{V}}_{in2}}+{f_{yy}}(0,0).{{\text{V}}_{in2}}^{2}]+.....{\text{ }}(1) \hfill \\ \end{gathered}\) where f(x,y) is a real function of x and y.

Ignoring the higher order terms in (1), we can expand V_out up to some n^th power of V_in1, V_in2, which gives us the approximation in (2).

\({{\text{V}}_{out}}{\text{=}}{{\text{a}}_0}+\sum\limits_{{k=1}}^{n} {\sum\limits_{{i=0}}^{k} {{a_{ki}}{{\text{V}}_{in1}}^{{k - i}}{{\text{V}}_{in2}}^{i}} +} \varepsilon {\text{ }}\) (2)
Where a₀, a_ki are real valued coefficients ∀ i = 0 to k and ∀ k = 1 to n. ε is the truncation error.

The coefficients a_ki’s are real functions of circuit parameters, e.g. resistances, capacitances etc. The coefficients a_ki’s in Eq. (2) cannot be exact to that of Eq. (1), as Eq. (2) comprises only a finite number of terms for what is essentially a truncated Taylor series. Eq. (2) is a linear regression model that describes the relationship between circuit output voltage Vout and two input voltages Vin1, Vin2. Judicious selection of the coefficients a₀ and a_ki’s of a polynomial regression model in (2) using traditional linear least squares techniques minimizes truncation error ε. The accuracy of regression model depends on the degree of the polynomial expansion used in practice. The traditional methods in MATLAB to estimate a linear regression model are already discussed in [15]. In this work, MATLAB Polyfitn library [16] is used to solve the coefficients of a polynomial regression model using classical linear least square techniques. Several numerical methods are used to implement Polyfitn library. However, to obtain a more stable solution, reasonably efficient QR factorization with pivoting [17] is introduced to build Polyfitn library. Any analog circuit in general can be represented using this model. The technique applies equally well to linear and nonlinear circuits.

For fault detection, we assume that normal parameter variations (normal drift) in a fault-free circuit are within a fraction α of their nominal value, where α << 1. That is, every parameter p_j is allowed to vary within the hypercube p_j,nom(1 − α) < p_j < p_j;nom(1 + α) ∀ j, where p_j;nom is the nominal value of the circuit parameter p_j. Any change in the value of one or more parameters of an analog circuit result in a change in one or more coefficient values of its polynomial regression model described by Eq. (2). Due to parametric fault, if the value of any parameter p_j falls outside the hypercube, one or more coefficient values of Eq. (2) slip outside the hypercube \({a_{ki,\hbox{min} }}\)< \({a_{ki}}\)< \({a_{ki,\hbox{max} }}\). As a result, we get a different set of coefficients reflecting a detectable fault. Figure 1 outlines the procedure to test the CUT.

3.1 Estimation of Fault-free Polynomial Coefficients

For derivation of polynomial coefficients, the CUT is first simulated in PSpice [18] with nominal value of the circuit components. Using PSpice simulation data for V_in1, V_in2 and V_out, a polynomial regression model of the form given by Eq. (2) is obtained using MATLAB Polyfitn function. The polynomial coefficients, thus obtained are fault-free coefficients.

3.2 Computation of Fault free Coefficient Bounds

To calculate fault free coefficient bound, the CUT is simulated using Monte-Carlo simulation [19] where each of the circuit parameters varies within the specified tolerance range (± 5%) [8] for which the circuit output is considered to be fault-free and the polynomial coefficients are estimated while the rest of the circuit parameters are kept at their nominal values. Thus, for every circuit parameter p_j, we get fault-free bounds (\({a_{ki,\hbox{min} }}\),\({a_{ki,\hbox{max} }}\)) of coefficients\({a_{ki}}\)∀ i, j, k.

3.3 Fault Modeling and Estimation of Faulty Polynomial Coefficients

It is noteworthy that only single parametric faults are considered in this paper. The operational amplifier used in the circuit is assumed to be fault free. The CUT is fault free when the resistors and capacitor values vary within the tolerance limits (± 5%). To test the CUT, single parametric fault is injected by varying one of the circuit parameters outside its tolerance limits followed by PSpice simulation. Polynomial coefficients of the faulty CUT are estimated using MATLAB Polyfitn function.

3.4 Fault Detection

The estimated polynomial coefficients of the faulty CUT are compared with the fault free coefficient bounds. If any of the estimated polynomial coefficients are found to be within its fault free coefficient bounds, the fault is said to be detected. On the contrary, if all of the coefficients are found to fall in the range, no conclusion can be drawn that whether the CUT is faulty or fault free. However, in most of the cases, it is observed that if the CUT passes the polynomial coefficient based fault detection test, the CUT can be declared as fault-free with a higher probability [6].

To present how the methodology can be used to identify faulty component, here two examples are considered. The first circuit considered is a lead lag circuit [11], and the second circuit is the PI compensator of a peak-current-mode-controlled buck-type switching converter [12, 13]. For both circuits, single parametric fault conditions are simulated and the results are obtained.

4.1 Lead Lag Circuit

The circuit shown in Fig. 2 is an op-amp based lead lag circuit with two inputs. At the inverting input a sinusoidal signal of 100 Hz and amplitude of 2 Volts is applied while at the non-inverting input another sinusoidal signal of 10 Hz and amplitude of 4 Volts are applied.

The nominal values of the circuit components of lead-lag circuit shown in Fig. 2 are- R1 = 1kΩ, R2 = 10kΩ, R3 = 10kΩ, C1 = 0.1595µF, C2 = 1.595µF. The circuit is simulated for 30ms in PSpice with nominal component values and the response of the CUT is shown in the Fig. 3.

It is noteworthy that the output of the lead-lag circuit falls in the non-linear region because in some of the input voltages’ range op-amp operates in the saturation region.

4.1.1 Estimation of Fault-free Polynomial Coefficients

Using PSpice simulation data for V_n, V_p and V_out, a 6th degree polynomial regression model for lead-lag circuit is derived in terms of its two inputs V_n, V_p. The 6th degree polynomial regression model is simulated in MATLAB as shown in Fig. 4. It may be noted that the response from the derived polynomial regression model matches well with PSpice simulated response.

The 6th degree polynomial results in 28 polynomial coefficients. Among these, first 13 polynomial coefficients are shown in Table 1.

Table 1

Nominal value of the first 13 polynomial coefficients of 6th degree polynomial regression model of lead-lag circuit
Coefficient	A0	A1	A2	A3	A4	A5	A6
Nominal Value	0	0.0002	-0.0006	0.0002	-0.0010	0.0011	-0.0004
Coefficient	A7	A8	A9	A10	A11	A12
Nominal Value	0.0023	-0.0047	0.0038	-0.0005	0.0042	-0.0124

4.1.2 Computation of Fault free Coefficient Bounds

To calculate fault free bounds of the polynomial coefficients, the lead-lag circuit is simulated using Monte-Carlo simulation as discussed in Section 3.2. Table 2 shows the fault-free bounds of 13 coefficients A0 to A12 corresponding to each circuit component.

Table 2. Fault free coefficient bound value of the polynomial coefficients A₀to A₁₂

4.1.3 Fault Modeling and Estimation of Faulty Polynomial Coefficients

To test the lead-lag circuit, single parametric fault is injected by randomly varying each of the circuit parameters outside its tolerance limits followed by PSpice simulation. Polynomial coefficients of the faulty CUT are estimated as shown in Table 3.

Table 3. Various detected single faults

4.1.4 Fault Detection

As per Table 3, each of the circuit components under single parametric fault results in atleast one or all of the first 13 estimated polynomial coefficients to slip outside the fault-free coefficient bounds. So, all parametric faults modelled in this case study of the lead-lag circuit are said to be detected.

4.2 PI Compensator of a Buck Converter

Figure 5 shows the peak current-mode [20] controlled DC–DC buck converter using pulse width modulation (PWM) control IC UC3843 [21]. The working principle of peak-current mode controlled DC–DC buck converter is studied in [22, 23, 24] in details. One of the key functional blocks of the current mode controller is the PI compensator shown in Fig. 6 and constructed using an error amplifier. This is required for regulation of the output voltage. The output voltage, V_out of the power stage, is divided through resistor divider network R_f1 and R_f2 and then applied to the error amplifier as shown in Fig. 6. The reference voltage V_{REF =} 2.5 V is applied to non-inverting terminal of the error amplifier as a soft-start ramp with rise time 4ms.

The controller is the important part of the converter to maintain the constant output. Therefore, it is very necessary that the controller is designed and tested properly. Our aim is to detect the parametric fault of the controller part of the Buck converter circuit. Figure 6 shows the discrete PI compensator of the Buck converter circuit.

The nominal values of the circuit components of the PWM controller circuit shown in Fig. 6 are: R_f1=9.76 kΩ, R_f2=3.25 kΩ, R₁ = 1kΩ, C_hf=30pF, C_comp=2nF, R_comp1 =10 MΩ, R_comp=80 kΩ. The buck converter circuit is simulated for 1.5 ms in PSpice with nominal component values and the response of the PWM controller circuit is shown in the Fig. 7.

4.2.1 Estimation of Fault-free Polynomial Coefficients

Using PSpice simulation data for V_COMP, V_out and V_REF, a 5th degree polynomial regression model for PI controller circuit is derived in terms of its two inputs V_out and V_REF. The 5th degree polynomial regression model is simulated in MATLAB as shown in Fig. 8. The experimental result shows that the 5th degree polynomial gives the best match with PSpice simulated response of the controller circuit.

The 5th degree polynomial results in 21 polynomial coefficients shown in Table 4.

Table 4

The nominal value of the polynomial coefficients K0 to K21
Coefficient *10^+ 7	K0	K1	K2	K3	K4	K5	K6	K7	K8	K9	K10
Nominal Value	0.0019	-0.035	0.0008	0.2556	-0.0114	0.0001	-0.904	0.0631	-0.0012	0	1.593
*Coefficient 10**^+ 7	K11	K12	K13	K14	K15	K16	K17	K18	K19	K20
Nominal Value	-0.151	0.005	-0.0001	0	-0.9415	0.131	-0.006	0.0002	0.0000	-0.0000

4.2.2 Computation of Fault free Coefficient Bounds

To calculate fault free bounds of the polynomial coefficients, PI controller of the buck converter is simulated using Monte-Carlo simulation as discussed in Section 3.2. Most of the parametric faults in the PI controller circuit are detected using first 13 coefficients. Table 5 shows the fault-free bounds of the first 13 coefficients K0 to K12 corresponding to each circuit component.

Table 5. Fault free coefficient bound K₀ to K₁₄ for the controller circuit

Table 6. Various detected single fault using the coefficient K₀ to K₁₄ of the controller circuit

4.2.3 Fault Modeling and Fault Detection by Estimation of Faulty Polynomial Coefficients

To test the PI controller circuit, single parametric faults are injected randomly followed by PSpice simulation of faulty circuit. Polynomial coefficients of the faulty CUT are estimated as shown in Table 6. All parametric faults except – 5.6% and – 6% variation in R_comp1 and C_comp respectively are detected using first 13 coefficients. These two faults can be detected by considering the rest 8 coefficients, i.e. K13 to K20. Fault free bound of these 8 coefficients is shown in Table 7. Table 8 shows the faulty values of coefficients, i.e. K13 to K20 after injecting parametric faults.

Table 7

Fault free bounds of K13 to K20 for R_comp1 and C_comp
Component	Polynomial Coefficient *10^+ 07
Component	K13	K14	K15	K16		K17	K18	K19		K20
R_comp1 max	-0.0001	0.000	-0.9419		0.1313	-0.0068	0.0002		0.000	-0.000
R_comp1 min	-0.0001	0.000	-0.9414		0.1312	-0.0068	0.0002		0.000	-0.000
C_comp max	-0.0001	0.000	-0.9418		0.1313	-0.0069	0.0002		0.000	-0.000
C_comp min	-0.0001	0.000	-0.9417		0.1312	-0.0068	0.0002		0.000	-0.000

Table 8

Faulty Coefficients K13 to K20 for single parametric faults in R_comp1 and C_comp
Fault Injected	Polynomial Coefficient *10^+ 07								Coefficient out of bound	Fault Status
Fault Injected	K13	K14	K15	K16	K17	K18	K19	K20	Coefficient out of bound	Fault Status
R_comp1 5.6% down	-0.0001	0	-0.9413	0.1312	-0.0068	0.0002	0	-0.00	K15	Detected
C_comp 6% down	-0.0001	0	-0.9415	0.1312	-0.0068	0.0002	0	-0.00	K15	Detected

We have described a polynomial coefficient based test method to detect the existence of parametric faults in multi-input analog circuits, where signals are applied to more than one input. Our test procedure uses an estimation of polynomial coefficients of linear regression modelling followed by a determination of whether or not any of the coefficients is outside the fault-free range imposed by the circuit-parameter drifts. If any of the coefficients is found to be outside its prescribed fault-free range (tolerance box), the CUT is declared faulty. The advantage of this approach is that any component fault can be detected without circuit augmentation. Although, we have successfully demonstrated our test method for detecting single parametric faults only, this method is well applicable for detection of catastrophic faults too. The proposed approach is validated with the help of two case studies where some part of the output voltage V_out falls in the non-linear region. We have chosen 6th degree polynomial for lead-lag circuit and 5th degree polynomial for PI controller circuit of buck converter. High order polynomials often suffer from severe ringing between the data points. Moreover, with the increase in order of the polynomial, the number of coefficient increases and makes the fault detection procedure more complex. So, judicious selection of order of polynomial model is one of the key aspects in our proposed method which can be further explored. It may be noted that some of the parametric faults are sensitive to only fewer number of polynomial coefficients. As a result, those circuit-parameter drifts may not be captured by most of the coefficients which occur in case of PI Compensator of a Buck Converter. The proposed approach can be extended for fault diagnosis by exploiting the sensitivity of polynomial coefficients to circuit parameters.

Data availability statement

All data generated or analysed during this study are included in this article.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Author Contributions Statement

Author Anjali Rai conducted simulation, formal analysis and wrote original draft. Author Rahul Bhattacharya provided necessary resources, validated the results and edited the manuscript. Both the authors reviewed the final manuscript.

Ramadoss, R., & Bushnell, M. L. (1999). Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. Journal of Electronic Testing: Theory and Applications, 14, 189–205
Binu, D., & Kariyappa, B. S. (2017). “A survey on fault diagnosis of analog circuits: Taxonomy and state of the art” International Journal of Electronics and Communications (AEU), Elsevier, vol.73, pp. 68–83, March,
Guo, Z., & Savir, J. (2006). Coefficient Based Test of Parametric Faults in Analog Circuits. IEEE Transactions on Instrument and Measurement, 55, 150–157. DOI: 10.1109/TIM.2005.861490
Savir, J., & Guo, Z. (2002). “On the detectability of parametric faults in analog circuits” in Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 273–276. DOI: 10.1109/ICCD.2002.1106781
Kavithamani, A., Manikandan, V., & Devarajan, N. (2009). “Analog circuit fault diagnosis based on bandwidth and fuzzy classifier”, in Proc. IEEE TENCON DOI: 10.1109/TENCON.2009.5396219
Sindia, S., Singh, V., & Agrawal, V. D., “Polynomial Coefficient Based DC Testing of Non- Linear Analog Circuits”, In Proc. 19th ACM Great Lakes Symposium on VLSI, 2009, pp. 69–74. DOI: 10.1145/1531542.1531562
Sindia, S., & Agrawal, V. D. (2013). “High sensitivity test signatures for unconventional analog circuit test paradigms,” IEEE International Test Conference (ITC), Anaheim, CA, pp. 1–10. DOI: 10.1109/TEST.2013.6651884
Li, X., & Xie, Y. (2013). Analog Circuits Fault Detection Using Cross-Entropy Approach. Journal of Electronic Testing: Theory and Applications, 29, 115–120
Neter, J., Kutner, M. H., Nachtsheim, C. J., & Wasserman, W. (1996).“Applied Linear Statistical Models” IRWIN, The McGraw-Hill Companies, Inc.,
Seber, G. A., & F (1977). Linear Regression Analysis. John Wiley and Sons, Inc.. Wiley Series in Probability and Mathematical Statistics
Xia, L., Bell, I. M., & Wilkinson, A. J. (2008). “A Novel Approach for Automated Model Generation”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS) pp. 504–507. DOI: 10.1109/ISCAS.2008.4541465
Bhattacharya, R., & Biswas, S. (2012). S.Mukhopadhyay. “FPGA based chip emulation system for test development of analog and mixed signal circuits: a case study of Buck converter”. Measurement ; 45(8):1997–2020. doi:10.1016/j.measurement.2012.04.022. Elsevier
Bhattacharya, R. (2017). S.Kumar, and S.Biswas, “Resource Optimization for Emulation of Behavioral Models of Mixed Signal Circuits on FPGA: A case study of DC-DC buck converter”, International Journal of Circuit Theory and Applications, Wiley, [Online], 1st FEB DOI: 10.1002/cta.2323
Kreyzig, E. (2005). Advanced Engineering Mathematics. Wiley
Draper, N., & Smith, H. (1966). Applied regression analysis. New York: John Wiley & Sons
John, D. E., “polyfitn - Polynomial modeling in 1 or n dimensions”, https://in.mathworks.com/matlabcentral/fileexchange/34765-polyfitn
Higham, N. J. (2000). “QR factorization with complete pivoting and accurate computation of the SVD”, Linear Algebra and its Applications, Elsevier, vol. 309, pp.153–174
User’s, & Manual (2012). Cadence ORCAD 16.6, Cadence Design Systems, Inc., San Jose, CA, USA,
Kavithamani, A., Manikandan, V., & Devarajan, N., “Fault detection of analog circuits using network parameters”,Journal of Electronic Testing. Theory and Applications, 2012, Springer28:257–261
Samanta, S., Mukhopadhyay, S., & Sheehan, S. (2011). Discrete-time simulation of a peak current controlled DC/DC buck converter using modal decomposition. IET Power Electronics, 4(6), 642–650
Texas instruments data sheet of UC3843, Texas, & Instruments, Available: http://www.ti.com/product/UC3843
Erickson, R. W. (1999). Fundamentals of Power Electronics. Kluwer Academic Publishers USA
Kassakian, J. G., Schlecht, M. F., & Verghese, G. C. (1991). Principle of Power Electronics. Addison Wesley
Mohan, N., Undeland, T. M., & Robbins, W. P. (2003). Power Electronics: Converters, Applications, and Design (3rd ed.). John Wiley

No competing interests reported.

Fault Detection in Multi-input Analog Circuits using Regression Modelling

Status:

Version 1

Abstract

Figures

1. Introduction

2. Theory Of Multiple Linear Regression

3. Fault Detection Procedure