## 2.1 *Architecture of the proposed circuit*

The topology and the schematic of the current-limiting and short-circuit protection circuit proposed in this paper are shown in Fig. 1 and Fig. 2. This circuit consists of the sense-FET sampling circuit and the gate-source voltage control circuit of the power switch.

The sense-FET sampling circuit consists of current and voltage sampling circuits. The current sampling circuit work as follows, MN1 is a power switch, and MN2 is a current sampling transistor. The current sampling transistor MN2 is connected in parallel with the power MOSFET MN1. The aspect ratio of MN1 and MN2 is 7400:1, so the current flowing through the sampling transistor is quite small, making the voltage drop of the sampling resistor R1 negligible [13], so the source voltages of MN2 and MN1 are approximately equal. According to the linear region current expression of MOSFET:

$$\frac{{I}_{DS2}}{{I}_{DS1}}=\frac{{u}_{n}{c}_{ox}\frac{{W}_{1}}{{L}_{1}}\left({V}_{GS1}-{V}_{TH}\right){V}_{DS1} }{{u}_{n}{c}_{ox}\frac{{W}_{2}}{{L}_{2}}\left({V}_{GS2}-{V}_{TH}\right){V}_{DS2} } = \frac{(W/L{)}_{2}}{(W/L{)}_{1}} \left(1\right)$$

It can be obtained that the ratio of current flowing through MN1 and MN2 is their W/L ratio of 7400:1. Figure 3 shows the transient simulation results of the current. When the power switch MN1 is turned on, the sampling current can linearly follow the output current of MN1. And the sample error of the circuit is 1.89% in the range of 0-2A working current.

The principle of voltage sampling is basically the same as that of current sampling for sense-FET sampling. The difference is that the gate of MN1 is connected to the gate of the voltage sampling transistor MN3 through a two-stage inverter. This is because the gate voltage *V**G* of MN1 will decrease after the current limiting circuit is triggered, so the gate voltage of MN3 needs to be clamped. When MN1 is turned on, the gate voltage of MN3 is fixed, and the current of MN3 is converted into voltage with resistor R2 to complete the sampling of the drain voltage of MN1.

The gate-source voltage control circuit includes the current-limiting protection circuit and the short-circuit protection circuit. The transistor sense-FET1(MN2) samples the current *I**L* of the power switch MN1, and the sampled current is converted into a voltage through R1 and transmitted to the current-limiting protection circuit. When the circuit is heavily loaded, the gate voltage *V**G* of MN1 is reduced, and the then load current *I**L* will be reduced to achieve current-limiting protection. The transistor sense-FET2(MN3) samples the voltage of the power switch MN1 and transmits the sampled voltage to the short-circuit protection circuit through R3. When the output is shorted to the power supply, the voltage *V**SC* changes from low to high, MN4 is turned on, and the circuit is shut down.

## 2.2 *Current-limiting protection*

The current-limiting protection circuit is shown in Fig. 4. The sampling current is converted into the voltage through the resistor R1 and transmitted to a current-limiting protection circuit composed of a temperature-compensated current comparator.

During normal operation, transistors MP2, MP1 and transistor Q1, Q2 form two pairs of current mirrors. When the circuit is heavily loaded, the current of the sampling transistor MN2 increases to the current-limiting threshold, causing the emitter voltage of Q1 increased.

At room temperature, the voltage expression at point A can be calculated by the following formula:

$${V}_{A}={\frac{{(W/L)}_{MN2}}{{(W/L)}_{MN1}}I}_{L}{R}_{1}+{V}_{BE1} \left(2\right)$$

It can be obtained that the base voltage of Q2 and the current *I**Q2* increase, making *I**Q2*>*I**MP2*, then the gate voltage *V**G* of the power switch decreases (the resistor R2 is used to prevent excessive gate voltage from breaking down the device, and there is no voltage drop on it) [17].

The DC simulation and frequency simulation results of the proposed circuit are shown in Fig. 5. It can be seen that the power supply rejection ratio of the circuit is -53dB. When the load is less than 7.5Ω, the current limiting function is triggered, and the current flowing through the power switch is limited to 2A.

Considering the high operating current and temperature of the proposed circuit, temperature compensation should be added to the current comparator. In 0.35µm BCD technology, Poly silicon resistors with a positive temperature coefficient can be adopted to compensate for the negative temperature coefficient of *V**BE*, but the compensation still has a large deviation in the entire temperature range [18–23]. In order to avoid increasing the complexity of the circuit, this design adopts the resistance ratio method, which uses two types of resistances with positive (Poly silicon resistor, *R**P*) and negative (N-well resistor, *R**N*) temperature coefficients (*TC*) to achieve second-order temperature compensation. Figure 6 below shows the simulation results of *I**L* varying with temperature when the circuit only adopts Poly silicon resistor or N-well resistor.

According to the analysis in Ref. [5], the temperature coefficients of *I**L*, *V**G* and *I**CQ1* are equal, and the relative temperature coefficient of *I**L* can be obtained by formula (3):

$$\frac{\partial {I}_{L}}{\partial T}=T{C}_{L}=\frac{1}{{V}_{T}}\frac{\partial {V}_{T}}{\partial T}-\frac{{R}_{N}}{{R}_{N}+{R}_{P}}T{C}_{N}-\frac{{R}_{P}}{{R}_{N}+{R}_{P}}T{C}_{P} \left(3\right)$$

Among them, \({R}_{1}={R}_{N}+{R}_{P}\), \(T{C}_{N}\) and \(T{C}_{P}\) are the temperature coefficients of \({R}_{N}\) and \({R}_{P}\). The temperature simulation result after temperature compensation is shown in Fig. 7, and the temperature coefficient of *I**L* is 277ppm/℃.

## 2.3 *Short-circuit protection*

The short-circuit protection is shown in Fig. 8. When the enable signal \(\stackrel{-}{RST}\) goes from high to low, the RS flip-flop output Q (point C) is high, and the circuit works normally. Transistor MP4, Q4 and resistor R4 form a path from VPWR to GND. Since the base of the Q4 transistor is connected to the collector, the path current and the voltage at point B are fixed. Voltage at point B can be expressed as follows:

$${V}_{B}={V}_{PWR}-{I}_{L}{R}_{L}-{V}_{DS\left(MN3\right)}+{V}_{BE3}={V}_{R2}+{V}_{BE3} \left(4\right)$$

It can be seen that when the short circuit occurs, the voltage drop across R2 increases, Q3 transistor is turned off and *V**SC* goes from low to high. VSC passes through RS flip-flop and inverter INV4, the voltage at point C is low, MN4 is turned off, and all MOS transistor current mirrors are turned off. The voltage at point D is high, MN6 is turned on, and the power switch is turned off.

The DC simulation result of the proposed circuit is shown in Fig. 5. When the load is less than 3Ω, the short-circuit protection is triggered to shut down the entire circuit.