Impacts of Material Parameters on Breakdown Voltage and Location for Power MOSFETs

doi:10.21203/rs.3.rs-1765193/v1

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Impacts of Material Parameters on Breakdown Voltage and Location for Power MOSFETs

https://doi.org/10.21203/rs.3.rs-1765193/v1

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To improve the electrical performance of power devices, materials used in fabrication need to be analyzed and optimized. By numerical simulations, we reveal that the breakdown voltage (BV) and location of a lateral diffused MOS power device simultaneously depend on trench oxide permittivity. For a given device geometry, while trench oxide permittivity with a certain value leads to a maximal BV, a smaller (larger) value causes electrical breakdown in the Si drift channel around the bottom (top) of the trench. This trend stays the same when Si is replaced by SiC. Our study implies that any byproduct reducing the trench permittivity during trench filling should be avoided.

permittivity

breakdown

lateral diffused MOS

Trench process has been widely used in semiconductor fabrication, such shallow trench isolation, tall fin and lateral trench formations. The latter has to be optimized to achieve better electrical performance in terms of a higher BV and a lower specific on-resistance of a lateral diffused MOS (LDMOS) power device [1–3].

Following the trench formation and oxidation remedy at the etched Si surface, the trench is refilled with oxide (normally SiO₂ with an ideal relative permittivity value ε_ox of 3.9) by chemical vapor deposition (CVD) [4–5]. In CVD process, the temperature, pressure and precursors significantly affect the permittivity of the trench oxide. The value can be smaller than ideal ε_ox due to sloppy microstructures and incorporation of hydrogen and carbon atoms [6]. On the other hand, the presence of nitrogen and other metallic elements in the trench oxide will result in a larger value of ε_ox [7]. However, the impact of permittivity of the trench oxide on the LDMOS is rarely discussed [8].

A larger bandgap (E_G) of the host semiconductor for a power device theoretically guarantees a higher BV. However, a semiconductor with a wider E_G normally possesses a lower relative permittivity (ε_s), which may unfortunately enhance the electric field. However, the influence of these two semiconductor parameters on power devices is still unrevealed in detail.

Therefore, we investigate the correlation between material (both semiconductor and oxide) permittivity and electrical breakdown of LDMOS power devices by using a technology computer-aided design (TCAD) simulator. We quantitatively discuss the impacts of a larger E_G and a smaller ε_s on BV as well

The simulated Si LDMOS device is shown in Fig. 1(a), and its electrical characteristics is calculated by solving Poisson and hydrodynamic equations self-consistently with Fermi statistics and an initial temperature set at 300 K [9]. Carrier mobility is modeled with concerns of high field saturation, impurity and surface roughness scattering. Carrier generation and recombination are considered by including Auger, avalanche, doping-dependent and field-enhanced Shockley–Read–Hall (SRH) models. And default parameters of these models for Si are used in simulations.

Both carrier and lattice temperatures can theoretically rise because energy of carriers increases due to electric field acceleration and then relaxes to the lattice via scattering. This phenomenon is likely to lead to different temperatures between the carrier and lattice in a power device. Compared to drift-diffusion formulism, hydrodynamic model is able to take nonequilibrium effects into account [10]. Particularly, avalanche model requires carrier and local lattice temperatures for accurate predictions [11]. As a consequence, besides including hydrodynamic transport model, carrier temperature is also coupled to high field saturation, SRH and avalanche models in the simulations.

A. Simulations with default Si parameters

Fig. 2(a) shows the I_DS-V_DS curves of the LDMOS devices with default Si parameters and different ε_ox. All curves almost fall on top of each other when V_DS < 70 V, and which implies that the on-resistance is hardly affected by different trench oxide ε_ox.

This is attributed to the fact that the current flow is not confined at the trench interfaces. The abrupt increase of the drain current can be clearly observed when the drain voltage reaches a certain value for each LDMOS device. After BV extraction from (a), the correlation between BV and trench oxide ε_ox is presented by the black squares in (b). With the maximal at ε_ox = 3, the BV drops rapidly with increasing and decreasing ε_ox. Compared to the BV at ε_ox = 3, BV value drops by 24.6%, 2.2% and 12.3% at ε_ox = 2, 3.9 and 5, respectively. This result strongly suggests strict fabrication control of the trench oxide deposition.

Fig. 4 displays the electric field (E) and electrostatic potential contour corresponding to the simulations in Fig. 2 at BVs. With ε_ox = 1, V_DS drops along the U-shaped lightly-doped drift region and the maximum E around the trench corner can be observed, where the avalanche breakdown happens. With ε_ox = 3, thanks to the reduced surface field (RESURF) effect [12], more even distribution of V_DS drops between the top and bottom corners of the trench is achieved, accounting for the maximal BV in Figs. 2 and 3. With further increasing ε_ox, the enhanced electrical coupling between the source and drain directly via the top of trench oxide, concentrating V_DS drop, augmenting the E around the top corner of the trench and reducing VB.

B. Simulations with modified Si parameters

With Si default parameters in simulations , the maximal BV takes place at ε_ox = 3 as shown in Figs. 2 and 3. It may be worthy to study if this result can be influenced by changing Si parameters to wide-bandgap material ones. To make the study more transparent, we decouple the impacts of all material parameters on the electrical breakdown of the LDMOS devices. This is done by assuming that the semiconductor of the device is still Si but only one or two parameters are maneuvered artificially in each simulations. While the Si default parameter ε_s is 11.7, we may change it to 9.66 (17.4% reduction), corresponding to ε_s of 4H-SiC [13]. With the same 17.4% modification, Si E_G is increased up to 1.315 eV. Based on these default and modified Si parameters, the BVs of the LDMOS power devices are exhibited in Fig. 3. With a constant E_G = 1.12 eV, the maximal BV is decreased by only 4.1% due to the 17.4% reduction of ε_s. With a constant ε_s = 9.66, however, the maximal BV is enhanced by 11.7% due to the 17.4% increase of E_G. According to these results [14]-[15]-[16], it is concluded that the optimal BVs can be found around ε_ox = 3 ~ 4 and BV is mainly dominated by E_G although a lower ε_s of a wide bandgap material tends to counteract the BV improvement.

By numerical simulations, we reveal that the breakdown voltage (BV) and location of a lateral diffused MOS power device simultaneously depend on trench oxide permittivity. For a given device geometry, while trench oxide permittivity of around 4 leads to a maximal BV, a smaller (larger) permittivity value causes breakdown in the Si drift channel around the bottom (top) of the trench. Our study implies that any byproduct reducing the trench permittivity during trench filling should be avoided.

Acknowledgement

This work is financially supported by the Young Scholar Fellowship Program from Ministry of Science and Technology, Taiwan, under Grant MOST 110-2636-E-006-004.

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You are reading this latest preprint version

Impacts of Material Parameters on Breakdown Voltage and Location for Power MOSFETs

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Version 1

Abstract

Figures

I. Introduction

Ii. Simulation Approach

Iii. Result And Discussion

A. Simulations with default Si parameters

B. Simulations with modified Si parameters

Iv. Conclusion

Declarations

References

Status:

Version 1