High Resolution Digital Pulse Width Modulator Architecture using Reversible Synchronous Sequential Counter and Synchronous Phase-Shifted Circuit

Nowadays, the DC-DC converter digital control is more attracted due to its benefits, like programmability, enhanced control algorithms. As a vital part of digital control, the digital pulse width modulator (DPWM) is designed to satisfy various requirements for higher performance. The existing digital pulse width modulator architecture activated with higher resolution along higher switching frequency, also the mandatory counter clock frequency is higher. To overcome this issue, the hybrid digital pulse width modulator architecture is proposed that combines Reversible Synchronous Sequential Counter and synchronous phase-shifted circuit. The proposed architecture consists of 4 blocks, they are, decoder, synchronous reversible counter, Synchronous Phase-Shifted Circuit, Delay line. The decoder is used to divide the input duty cycle command (DCC) into three parts: most significant bits (MSB), secondary significant bits (SSB) and least significant bits (LSB). The Reversible synchronous counter is used to count trigger signal in every clock period. Here, synchronous phase shift circuit is utilized to select the clock through the quadrant phase-shifted clocks. The delay line is used to set the time resolution of DPWM. In this work, D-Flip flop is used to leave


Introduction
Generally, Digital pulse width modulator (Radhika et al,2021) is used in electronic devices that are power management chips (Rao and Chakravarthi,2020), LED drivers (Yu and Murari,2021), base band signal processing etc. In DC-DC (Rao and Chakravarthi,2020) converters are implemented using the DPWM with the advantages as insensitivity to process, voltage, temperature (PVT) variations (Papananos et al,2020), programmability advanced control algorithms, wide applicability while compare with the general analog DC-DC converters. DPWM act as a converter for the distinct duty cycle signal to an analog pulse width modulation signal that drives power transistors and it produce high resolution (Cheng et al,2020), good linearity and low power consumption. High-resolution pulse-width modulator (HRPWM) is has high precision in the pulses edges and the resolutions exceeds the period of the system clock. Counter-based DPWMs are direct signals for analog pulse width modulation, in which n-bit counter imitates triangular waveform that are likened to the digital code K[n] for producing output signal (Alzaher and Alghamdi,2020;Kipenskyi et al,2020). Delay-line-based structures are used as the propagation delay in n 2 delay element (DE) linked in the cascade to produce the higher resolution pulse width modulation signal utilizing n 2 input multiplexer including input signal M[n] to select various delay cells outputs (Crovetti et al,2020;Petric et al,2021).
In this manuscript, hybrid DPWM architecture is proposed which combines 4 blocks.
Hybrid DPWMs are executed by incorporating reversible counter, synchronous phase-shift circuit, delay line and phase locked loop (PLL). Here, HDPWM is normally use this phase locked loop to create 4 phase-shift clocks, then the time resolution is equivalent to delay among 2 nearby phase-shift clocks. By using the delay cells, the delay line base hybrid structure is designed. The hybrid structures give the counter clock frequency requirement as well as upgrade the time resolution, linearity. The cascaded DCMs have been utilized to DCM-base and delay line-base design to maximize the resolution. These 2 models not only minimize the linearity of digital PWM, but also maximize the delay of critical path along resource (area). These designs are affected through the tradeoff between the linearity, time resolution, resolution, resource (area).
The main contributions of this manuscript is summarized as,  (Sun et al,2020) respectively.
Remaining manuscript is delineated as: section 2 reviews the recent studies, section 3 illustrates about the proposed design, section 4 proves the results with discussion, and section 5 concludes the manuscript.

Literature Survey
Among the frequent research work on DPWM; some of the latest investigations were assessed in this part, In 2020, Cheng, et.al, (Cheng et al,2020)have presented the synchronous phase-shift circuit with delay line based higher resolution digital PWM. The critical path performance was analyzed by the synchronous phase-shift circuit then the resolution of time was improved with the help of delay line depending on carry chain. Similarly, the combined process shows the hybrid DPWM. Finally it gives high linearity and the time resolution. This method was limited due to output variations.
In 2020, Sun, et.al. (Sun et al,2020) have presented a Delay-Line digital pulse width modulator with Compensation Module, Delay-Adjustable Unit depends upon Delay Locked Loop. While the Duty cycle resolution was increased, digital pulse width modulations affected on its clock frequency, temperature as well as time error and it becomes larger.
Delay-adjustable unit was depending on multiplexer, delay paths along various delay time, which frequently reduce the temperature or frequency via the input clock. Error was reduced using the time compensation technique by the critical path. Its temperature was high.
In 2020, Morales, et.al., (Morales et al,2020) have presented a high-resolution all DPWM structure along tunable delay element in CMOS. It was depending on digitally controlled delay element which was the combination of the uneven time interval up to 54 picoseconds, adjustable against PVT variations. The Hybrid DPWM allows for getting the duty cycle with 18-bit resolution and it could not use the internal clock with high frequency and the low power dissipation also maintained. HDPWM has improved performances, but it was limited due to delay.
In 2021, Arora,,et.al., (Arora et al,2021)have presented the Digital Pulse Width Modulation Using Direct Digital Synthesis. DPWM was digitally controlled power converters. It was cost effective, high performance as well as functionally integrated with small packaged-sized.
Where, delay was increased.
In 2021, Bhardwaj,,et.al., (Bhardwaj et al,2020) In 2021, Nguyen, et.al., (Nguyen et al,2019) have presented the Phase-shifted carrier pulse-width modulation along enhanced dynamic performance for modular multiple level converters. The presented algorithm as well as capacitor voltage balancing control removes the tedious proportional-integral parameter tuning process requirement. It enhances the dynamic performance compared to the conventional methods. It consists of high modality, easy scalability. The presented method was limited due to low frequency.
HRHDPWM was designed using the counter, a phase shift circuit and carry chain. Dualedge-triggered flip-flops were utilized to create the signals including 45 0 phase shift in the phase-shifted circuit and the hardware compensation was used to maximize the duty cycle which affect the regulation accuracy of the converters. It was used to reduce the resource compensation but it was consumes high power.

Proposed methodology
In this, the DPWM architecture is designed and it is given in Figure 1. It includes decoder, proposed reversible synchronous counter, phase-shifted block, delay line and D flip-flop.
Here, the input duty cycle command is denoted as    replacing MUX, the synchronous phase shift circuit utilizes 4 two-input AND gates together with 1 four-input OR gate. To assure these gate locations are set in location allocations, the restriction for global signal on every path is needed, thus creating every path equivalent delay. The 4 AND gates outputs are injected into 4-input OR gate. By then, Synchronous Phase-Shifted Circuit is designed for digital pulse width modulator (DPWM) design.

Delay Line
Delay line is used to set the time resolution of DPWM. The propagation delay of carry bit in every added is constant then it is able to predict the values from 10-100ps. Similarly, to check the linearity, the carry chain total delay is equivalent to delay among the 2 adjacent phase shifted clock ( CPS D ). The carry chain uses 2 2  b adders and its equation is given in equation (2) Where, c D represents carry delay of the adder. Figure 1 contains Reversible synchronous counter, delay line, synchronous phase-shifted circuit and resolution of this circuit is given as a and it is represented as the number of bits. Thus, higher resolution DPWM is recognized by maximizing the bits count of counter, count of cascaded phase-shifted circuits, or delay line length. When maintaining better presentation of linearity with time resolution, it reaches greatest 18-bit resolution.
By using Reversible synchronous counter, synchronous phase-shifted, delay line, and the resolution of this circuit is given as a and it is represented as the number of bits parameters the high resolution DPWM is designed. To design the high resolution DPWM with the needed time resolution c D , first design parameter a . In this, a is designed for compromising resource (area) and power. If the power is increased more number of adders are included. For reducing the power and area less number of adders are used according to the equation (2) therefore the use of counter is also lowered. Therefore, the counter's clock period is given in The switching period of digital pulse width modulator is given in equation (1)  and it represents reset signal of output D-Flip flop. By this process, the negative edge of the DPWM pulse is generated.

Output of D-Flip flop
In this work, D-Flip flop is used to cause sufficient slack among the set signal and reset signal and to avert glitch. It can achieve high resolution of linearity and time resolution. While using RS latch, the slack is not able to predict, delay is non-negligible, and not able to calculate the

Result and Discussion
In this section, hybrid digital pulse width modulator architecture is proposed that combines Reversible Synchronous Sequential Counter and synchronous phase-shifted circuit is discussed. The experiment results are obtained with an external clock of 50MHz internally multiplied to 188MHz by PLL, which means the counter clock frequency is 188MHz. A total of 290 LEs are used, and the resource usage is 5%. Here, the assessment metrics such as path

Conclusion
Nowadays, the DC-DC converter digital control is more attracted due to its benefits, like programmability, enhanced control algorithms. The coding is done in Verilog and the proposed synchronous counter design has been synthesized using Xilinx ISE. Here, the assessment metrics, such as path delay, linearity, output duty cycle and time resolution are analyzed. The performance of the proposed SCD-MCT-MCF design shows lower path delay 24.94%, 28.94%, is compared with the existing design such as high resolution DPWM depending on synchronous phase-shifted circuit and delay line (Hyb DPWM-SPSE-DL), Delay-Line DPWM Architecture with Compensation Module and Delay-Adjustable Unit depending on Delay Line (Hyb DPWM-DLP) respectively.

Data availability statement
Data sharing is not applicable to this article as no new data were created or analyzed in this study.
Funding Information: