Optimization of an SSHC-based full active rectifier for piezoelectric energy harvesting

This paper presents a compact and efficient integrated interface circuit for piezoelectric energy harvesting. While state-of-the-art interface circuits require either an external inductor or a significant number of additional capacitors to achieve high voltage flip and thus improve power efficiency, the proposed Full Active Rectifier on Flipping Capacitor (FAR-FC) is based on a reduced set of flipping capacitors and an active rectifier to efficiently flip the voltage across the piezoelectric transducer. In addition, this optimized SSHC circuit reaches better power efficiency when the piezoelectric transducer operates under low mechanical excitation, i.e. when the open-circuit voltage of the piezoelectric transducer is Voc=1V\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$Voc=1\,V$$\end{document}, while usually Voc≥2V\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$Voc\ge 2\,V$$\end{document} in literature. Furthermore, the FAR-FC supports piezoelectric transducers with higher inherent capacitance values compared to those usually reported in literature, which makes the circuit potentially suitable for a larger variety of applications. The interface circuit was designed and fabricated in a 0.35 μm CMOS process. Measurement results show that the voltage flip efficiency goes up to 90%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$90\%$$\end{document}. It also reveals that the proposed FAR-FC circuit achieves power performance up to 5.64×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$5.64\times$$\end{document} higher than a conventional full-bridge rectifier.


Introduction
In the last decade, ultra-low power wireless sensors have gained increasing interest for a large variety of applications [1][2][3][4][5][6][7][8].For such sensors, batteries are the main energy sources despite their finite lifetime.However, for certain applications such as aeronautics and rail transport, significant operation time of sensors is required.This makes the battery usage impractical and adds maintenance cost due to the periodic re-charging or replacement.In order to address this issue and extend the operational lifetime of wireless sensors, there has been an emerging research interest in harvesting ambient energy.Many different kinds of energy harvesters have been proposed, such as solar, kinetic, thermal, wind.[9][10][11][12][13][14][15][16].In the case of kinetic energy, vibrationbased harvesters are the most popular ones.These are often used where mechanical vibrations occur permanently or frequently, such as the passing of vehicles, engines, or human movements [11,[17][18][19].In particular, piezoelectric energy harvesters (PEH) are widely employed due to their high power density, scalability and compatibility with conventional integrated circuit technologies compared to other implementations, such as electromagnetic and electrostatic harvesters [20,21].The direct effect of the piezoelectric material causes the generating of an electrical charge when a mechanical strain is applied to it.Yet, owing to its vibratory nature, the raw energy of this kind of harvester is unsuitable to directly power an electronic device such as a wireless sensor.Therefore, a dedicated interface circuit is necessary to rectify the voltage across the piezoelectric transducer and provide stable power supply.
Fig. 1 shows a piezoelectric energy harvesting system.It consists of a piezoelectric transducer (PT), an interface 1 3 circuit, storage and load elements.When the piezoelectric harvester vibrates at or near resonance, it can be modeled as an equivalent sinusoidal current source I peh in parallel with an inherent piezoelectric capacitor C peh .The need to discharge and recharge C peh each cycle of I peh significantly reduces the output voltage amplitude and thus the output power.This makes the use of the conventional diode-based full bridge rectifier FBR unsuitable for low PT voltage (i.e.around 1V or below) because of the threshold voltage of the rectifying diodes.
To address this problem and improve the extracted power, many approaches have been proposed in literature.In the switch-only [22] approach, a single switch is connected in parallel with the PT to instantly discharge C peh each time the output voltage of the PT reaches its maximum.This eliminates the time required to discharge C peh , doubles the output voltage and quadruples the extracted power.However, there is still a charge loss due to the need to recharge C peh each time I peh changes direction.
To reduce this charge loss, different typologies have been implemented such as Synchronized Switch Harvesting on Inductor (SSHI) [22][23][24][25] and Synchronous Electric Charge Extraction (SECE) [26][27][28][29][30][31].In theses typologies, an inductor is employed to flip the voltage across the PT at each zero crossing of I peh .Although SSHI and SECE can extract most of the energy generated by the PT, they require a large inductor in range of mH with a high quality factor to reach satisfactory extracted power.This significantly increases the overall volume of the harvesting system and makes it unsuitable for ultra-compact applications.Moreover, accurate RLC tuning is also needed to achieve acceptable power efficiency in SSHI [22], while in SECE, the PT should be weakly coupled to extract more power than that extracted by the FBR [30].These limitations are overcome by replacing the inductor with one or more capacitors in Synchronized Switch Harvesting on Capacitor (SSHC) interface circuits [19,[32][33][34][35].In SSHC, switched capacitors are used to flip the voltage across the PT.However, to reach high power efficiency, a significant number of flipping capacitors and/ or flipping phases is needed [32][33][34].This increases the system's volume and its control complexity.Furthermore, the large number of flipping capacitor/phases increases the voltage flip time and thus decreases both the conduction time and the harvested power.This sets a significant constraint on the value of C peh , which in this case should be as low as possible to reduce the RC time constant that impacts the voltage flip time [19,[32][33][34].
In addition, in most of the reported research work, the PT should operate under relatively high mechanical excitation level with an open circuit voltage greater than 1V in order to extract acceptable power [19,22,25,26,31,32,36].However, in real operation conditions the mechanical excitation may be weak, leading to reduced PT open circuit voltage and hence lower extracted power [37].
This paper presents an optimized version of the SSHC topology, named Full Active Rectifier on Flipping Capacitor (FAR-FC) [32,34].The proposed compact and efficient interface SSHC circuit uses a reduced set of capacitors to efficiently flip the voltage across the PT in only nine phases.This enables the use of PTs with higher C peh capacitance value than the ones used in literature [32,34].The paper is organized as follows: Section 2 recalls the principles of a conventional capacitor-based interface SSHC [32].The design of the FAR-FC with the detailed analysis of each building block is presented in Sect.3. Section 4 provides and discusses the measurement results.Finally, Sect. 5 summarizes and concludes this paper.

Conventional capacitor-based SSH interface
Figure 2 shows a one-capacitor SSHC interface circuit and the associated current, voltage and control signals waveforms [32].This circuit consists of a diode-based full bridge rectifier (FBR) with only one switched flipping capacitor C 0 used to flip the voltage V peh across the PT.The inversion of V peh requires five analog switches.The process takes place in three phases: 1) the sharing phase ( Φ p ) when the charge in C peh is shared with C 0 , 2) the shorting phase ( Φ 0 ) when C peh is completely discharged, and finally, 3) the building phase when C peh is recharged from C 0 in the reverse direction.
As shown in Fig. 2 (bottom), the voltage across PT before the flipping moment is V peh = V rect + 2V th .Where V rect is the voltage across the storage capacitor and V th is the threshold voltage of the FBR diode.Assuming the voltages across PT at the end of the sharing and the building phases are V sh and V b , respectively.In steady state V b becomes constant and C peh needs to further charge from V b to V rect + 2V th .In order to evaluate the performance of this interface, the charge conservation equations are applied during both the sharing and the building phases, respectively: (1) Assuming the voltage drop across the rectifying diodes of the FBR and the losses related to all switches and parasitic capacitors are negligible, the ratio between V b and V rect may be expressed as in [19]: This ratio is highly related to the voltage flip efficiency defined in [23], when neglecting the voltage drop across the rectifying diodes of the FBR.This relation can be given as: Hence, increasing K FCR leads to increase the voltage flip efficiency.Also, in [19], Chen et.al. demonstrated that the maximum output power of this interface depends on K FCR , expressed as: (2) Therefore, the maximum output power improvement ratio (MOPIR) of the one-capacitor SSHC interface as expressed in [19,22] is: where P FBR(ideal)max is the maximum output power extracted by an ideal FBR [22] with zero voltage drop across its diodes expressed as: From (3), one can notice that K FCR is related to both C peh and C 0 .When C 0 ≫ C peh , K FCR converges to 1  2 , which yields MOPIR = 4 .In order to improve the K FCR of the one-capac- itor SSHC interface circuit, several implementations have been proposed in the state of the art.In [32], using eight parallel flipping capacitors, improves the K FCR to 4/5 lead- ing to MOPIR = 9.7 .Recently, it was proved in [35], that using C 0 = 100C peh increases the output power by 35.7% .In another implementation, proposed in [19], the use of four re-configurable capacitors led to 0.85 voltage flip efficiency and MOPIR = 4.83 .This topology requires a seven-phases voltage flip scheme.Increasing the number of switching phases to 21 phases [34] improves the MOPIR to 9.3.However, the use of a large number of parallel flipping capacitors [32] increases the number of switching phases and hence the flipping time.This in turn reduces the conduction time and thus the extracted power.Also, using the re-configurable flipping capacitors [19,34] increases the number of required switches, which increases the ON resistance during one flipping phase and thus the flipping time.As a result, increasing the number of flipping capacitors or phases to improve the flipping efficiency implies fast voltage flip operation.This can be achieved only when C peh is low.Otherwise, the use of large C peh in such implementations significantly increases the charge loss and hampers the voltage flip and power efficiencies.
From ( 5), we can notice that the maximum output power is also related to the PT properties and more pointedly to the V oc , the open circuit voltage of the PT.This voltage is induced by the mechanical excitation applied to the PT.The high mechanical excitation applied to the PT, the high V oc value across the PT.We can also point out, from (5), that a small increase in V oc significantly boosts the output power.Thus a low excitation level, i.e.V oc ≤ 1V , extremely limits the SSHC extracted power.
To overcome the limitations mentioned above, the following sections propose an optimized SSHC interface circuit.While the employed PT with a high parasitic capacitor C peh is operating under low excitation conditions, the proposed circuit achieves high voltage flip efficiency using a reduced set of flipping capacitors.( 6)

FAR-FC interface circuit topology and design analysis
As we can see in Fig. 2 (bottom), increasing the building voltage from V b (red curve) to V b1 (blue curve) con- tributes to minimize the charge loss Q loss .This increases the conduction time and thus the extracted power.Yet, as mentioned above the duration of the voltage flip operation depends on the number of flipping phases, and on the time constants imposed by the RC combinations.These combinations are formed by C peh , and the capacitors and switches used for the inversion.The theoretical studies led by Chen et al. in [19] show that, on the one hand, using more than ten phases brings only little improvement in the voltage flip efficiency F , and on the other hand taking flipping capacitors larger than 5 × C peh brings limited improvement to the MOPIR.Based on these observations, our proposed interface performs an efficient voltage flip thanks to an optimized implementation of the SSHC technique.The circuit is composed of only three flipping capacitors, which corresponds to a nine-phase voltage flip operation (i.e.below ten phases).It also requires only a reduced set of flipping switches (i.e.smaller RC constants), which in turn contributes to limit the duration of each phase.This allows the use of large C peh (i.e.around 100nF) with con- tained impact on the duration of the voltage flip operation.
Figure 3 shows the architecture of the proposed FAR-FC interface circuit.It mainly consists of: a Damping/Building capacitors array (D/B) for the voltage flip, an active AC/DC rectifier, a voltage regulator (VR) and a control block (CTRL).These blocks and their corresponding signals are detailed in the subsections below.Note that the circuit also features additional blocks, namely a ring oscillator (RO) [38], another voltage regulator (VR12) [32], a charge pump (CP) [39] and level shifters (LS) [32].The VR12 is needed to provide the low power supply ( V DDL = 1.2V ) mainly to the digital parts of the circuit (CTRL, RO), while the high power supply ( V DDH = 3V ) is provided by the CP block to the rectifier and the LS.These latter are employed to ensure proper control and operation of the switches.

Damping/Building capacitors array (D/B)
This block is used to efficiently flip V peh at each zero cross- ing moment of I peh .The voltage flip operation is performed in nine phases using three re-configurable capacitors and eleven switches (Fig. 3).As in the one-capacitor SSHC interface, V peh inversion operation can be subdivided into: where C peh is dis- charged through the flipping capacitors, 2) a shorting phase ( Φ 0 ) to get rid of the remaining charge in C peh , 3) building phases ( Φ 4 , Φ 3 , Φ 2 , Φ 1 ) where C peh is recharged from the flipping capacitors.Figure 4 shows the optimized 9-phase reconfiguration cycle at each V peh inversion operation.In  n,m) at the end of the damping Φ −n and building Φ n phases, respectively.Applying the conserva- tive equations, these voltages can be expressed as follows: . As a consequence, the voltage flip efficiency can be expressed by: From (10), it is clear that increasing V b(1,m) leads to increase F .For such a configuration, fulfilling the condition C n ≫ C peh is not sufficient to reach the maximum V b (1,m) as in the one-capacitor SSHC interface.The choice of the capacitance values for this configuration is the key to optimize the voltage flip operation.The simplified calculation of V d(n,m) and V b(n,m) when m = 1 using ( 8) and ( 9) allows to find the condition to have V b (1,1) maximal.As a result V b (1,1) can be expressed as: The previous equation (11) shows that maximum V b(1,1) is achieved when C 1 < C 2,3 < C 4 .This also applies to maxi- mum V b (1,m) .To fulfill this condition, we set 2 .Based on the characteristics of the PT device (S118-J12S-1808YB) employed in our experiments, the parasitic capacitor C peh is estimated to be 100nF.To choose the capacitance values, theoretical simulation of the voltage flip efficiency F versus different C 1 C peh ratios was performed (Fig. 5).Simulation results show that increasing C 1 C peh leads to increase F .However, for , the improve- ment on F becomes negligible.Note that, this result is consistent with [19].Therefore, the value of C 1 is set to 5 × C peh , i.e.C 1 = 500nF , C 2,3 = 1 F and C 4 = 2 F in our case.
As mentioned above, this configuration requires eleven transmission gate switches (TG), represented in the D/B inset of Fig. 3.Note that there are at most three TGs in series during the damping/building operation, i.e. when the D/B array is configured as C 1 .This helps containing the total series resistance at a low value during the charge transfer between C peh and the flipping capacitors, and thus limits the total time (RC) required to accomplish the voltage flip operation.This is an important point because it allows to efficiently apply the SSHC voltage-flip technique even on PTs with C peh as high as 100nF or above, and rep- resents an improvement compared to the state-of-the-art works that report PTs with C peh = 45nF [32] or much less [37,40].
Table 1 shows the control sequence of each switch when V peh is inverted from positive to negative ( V p → V n ) .The whole set of control signals is named SWctrl in Fig. 3. Individually, the switches are named after their control signals.That explains why some switches bear the same name in Fig. 3.Note that when V peh is inverted from negative to posi- tive ( V n → V p ) , the control sequence for switches swp, swn, (11) swp4 and swn4 changes during certain phases as mentioned in red in Table 1.The AD, shown in Fig. 6 (right), is used to both prevent the current backflow from C L to PT and detect the zero cross- ing moment of the PT current.It consists of an ultra-low power comparator [32] and a PMOS switch.When V rect , the voltage across C L , becomes larger than the voltage at node V sp , i.e. the current changes its direction, the comparator output V comp goes high.This signal is used by the CTRL block to both turn off the PMOS switch, thus preventing the discharging of C L , and trigger the inversion of V peh .Note that, during the damping phase, the AD is disconnected from the PT in order to ensure proper charge transfer from C peh to the flipping capacitors.This disconnection sets the node V sp in high impedance state, which leads to the false I peh = 0 detection.To prevent this phenomenon, a switch controlled by signal Vspctrl is added to connect V sp node to the ground during the damping phases.

Voltage regulator (VR)
Figure 7 presents the circuit diagram of the on-chip voltage regulator VR.This block is used for both the overload protection and maximum power extraction requirements.In this voltage regulator, a common gate comparator presented in [23] is used to limit V rect to a constant voltage V ref which allows maximum output power extraction.
To evaluate the maximum output power extracted by FAR-FC circuit, the total charge Q rect that actually flows into C L each cycle is calculated.This amount can be defined as the difference between the available charge from PT and the charge lost each cycle to charge C peh from V b to V rect :

Table 1 Summary of control signal combination
The control sequence for switches swp, swn, swp4 and swn4 changes according to the sense of inversion of V peh .The positive to negative transition ( V p → V n ) is shown in unbold, while the negative to positive transition (  The available charge from PT every cycle can be given by: where Voc is the amplitude of V oc , and f ex is the PT's exci- tation frequency.The charge lost every cycle Q loss can be calculated by: Therefore, Q rect can be expressed as: The extracted output power is given as: From ( 16) and ( 15), P FAR−FC can be expressed as: The derivative of (17) shows that maximum output power is achieved when: This value is used as a voltage reference of the voltage regulator VR in order to extract the maximum of power.From ( 17) and ( 18), the maximum power extracted by the FAR-FC circuit can be expressed as: Therefore, the maximum output power improvement ratio of the FAR-FC circuit can be expressed as:

Control block (CTRL)
The control block CTRL shown in Fig. 8 generates the voltage flip control signals mentioned in Table 1, and the control signals of the rectifier block (Fig. 6, left).
The AD's comparator output signal V comp is used to trig- ger CTRL.Upon rising edge of V comp , a lock signal (Lock) is generated to trigger the 9-phase sequence and lock the PMOS switch of AD in open state for the whole duration of the flipping process.( 16) Figure 9 (top) details the structure of the sequence generator block.It generates the vector of non-overlapping signals SWctrl presented in Table 1, that control de D/B array (see 3.1).Figure 10 shows the timing diagram of the signals generated by both the sequence generator and the rectification control circuits.
In normal operation mode and during the first and the last phases Φ −1 , Φ 1 , signal ser1 is set high to connect C 2 and C 3 in series, thus forming the equivalent capacitance C 1 .When the D flip flop is enabled by S1, signal ser1 goes low at the end of Φ 1 , and returns again to high when the D flip flop is reset by an internal signal when the last phase Φ 1 starts ( S 9 ⋅ S 8 ).Signal par2 is generated when S2 or S8 is high, i.e during Φ −2 and Φ 2 .Signal par3 is generated when S3 or S7 is high i.e during Φ −3 and Φ 3 .To control the polarity of C 1 , C 2 and C 3 while connecting with C peh , either swp or swn is set high depending on whether V peh is positive or nega- tive, respectively.Furthermore, both swp and swn are set high during Φ 0 , which corresponds to the shorting of C peh .Signals swp and swn are generated by three internal signal swpb0, swnb0 and sw0b determined by the phase combinations ( Φ −1 , Φ −2 , Φ −3 ), ( Φ 1 , Φ 2 , Φ 3 ) and Φ 0 , respectively.Since C 4 is independent from C 1 , C 2 and C 3 it only requires signals swp4 or swn4, which are set high during Φ −4 or Φ 4 depending on whether V peh is positive or negative.
Finally, a toggle is triggered at the end of each 9-phase generation process to swap states between swp and swn so the polarities of C 1 , C 2 and C 3 match the polarity of C peh on the next voltage flip.Also, in order to match the polarities of C 4 and C peh , the same toggle used in this block is employed to swap states between swp4 and swn4.
The duration PW (Fig. 10) of each phase depends on the time required to ensures proper charge transfer between C peh and the flipping capacitors.PW is set using a clock divider of the clock generator RO and can be tuned externally.It should be noted here that to avoid overlap between two successive signals, additional NOR and DELAY logic gates are employed (see shaded zone of the sequence generator part in Fig. 9).This is important to avoid false connection between flipping capacitors nodes during the charge transfer operation, which would significantly impact the system's efficiency.
The circuit of the rectifier's control block is shown in Fig. 9 (bottom).During each positive and negative alternation of V peh , SW 1 and SW 2 signals are set high, respectively to connect the positive terminal of PT to node V sp , and the negative terminal to ground.Furthermore both signals are set low during the damping and shorting phases to disconnect C peh from C L .This ensures proper charge transfer from C peh to the flipping capacitors during the damping phases by isolating PT and D/B from the rest of the circuit.
The rectification process is realized as follows: when the damping phases start, the rising edge of V comp sets the Trig signal high.As a result, both SW 1 and SW 2 signals are set low, which disconnects C L from the PT.At the end of the damping phases, signal Trig goes low, and then both SW 1 and SW 2 are set to SW 1 _in and SW 2 _in , respectively.The latter are the outputs of a toggle clocked by the delayed Trig signal, Trig_D .The rectification process is also reset by the signal RST_int , which sets low signal Lock until the next voltage flip operation.The need for disconnecting PT from C L during the whole voltage flip sequence imposes high impedance state at node V sp , which causes its voltage to rise because of the charge injection effect in the parasitic capacitances of switches SW 1 and SW 2 .This in turn could lead V comp to go low (i.e. if V sp > V rec ), which would turn on the PMOS switch of the AD while it should stay off until the voltage flip terminates.To prevent this phenomenon, this switch is controlled by signal ADctrl (Fig. 8).Furthermore, the control block generates signal Vspctrl that ties node V sp to ground during the damping period (Fig. 8).This prevents spurious behaviour of the AD comparator that would increase the power consumption of the circuit.

Transistor-level simulations
The FAR-FC interface circuit was simulated at transistor-level with Cadence®, using the AMS-0.35μm CMOS technology parameters.The model of the PT used in FAR-FC simulations is based on the off-the-shelf device S118-J12S-1808YB by Piezo.com with C peh = 100nF , which we also used in our experiments.Îpeh and f ex were set to 62.8 A and 100Hz in order to have an open circuit voltage amplitude Voc = 1V , which corresponds to a low mechanical excitation level.For these simulations, we set V rect = 1.2V as an initial condition of the storage capaci- tor C L = 100 F .For FAR-FC performance comparison, the SSHC circuit presented in [32] with three parallel capacitors (3cap-SSHC), i.e. with the same number of FAR-FC flipping capacitors, is also simulated.Figure 11 shows the simulated V peh and V rect without regulation for the two circuits.Even though the output voltage V rect of both architectures rises close to 2 Voc = 2V , the zoom view shows yet that, in steady state, i.e. when C L is completely charged, the maximum V b achieved by the 3cap-SSHC is 1V while V b reaches 1.5V in the FAR-FC.According to (18), in order to extract the maximum power generated by the PT, the output voltage of FAR-FC and 3cap-SSHC should be regulated to 1.75V and 1.5V, respectively.Taking into account the parasitic charge losses, V rect was regu- lated to 1.6V and 1.35V in the FAR-FC and the 3cap-SSHC Fig. 10 Timing diagram of the control signals sequence at zerocrossing moments of I peh circuits, respectively, which are more realistic (Fig. 12).The zoom view shows, that in steady state, the maximum V b is only 810mV in 3cap-SSHC, which yields a maximum output power of 39.48 W according to (19).In contrast, the maximum V b is 1.3V in FAR-FC, which corresponds to a maximum extracted power of 54.45 W .In addition, the simulations also confirm that the voltage flip efficiency of FAR-FC is higher than in 3cap-SSHC, with 90.6% and 80% , respectively.
The maximum output of a non-ideal FBR can be expressed as P FBRmax = C peh f ex ( Voc − 2V th ) 2 [22].Therefore, the maximum output power extracted by a CMOS-diodebased FBR ( V th = 0.3V ) is 1.6 W . Hence, the theoretical maximum output power (MOPIR) of the FAR-FC architecture yields 28× improvement compared to an FBR.
Figure 13 details the simulated behaviour of V peh and the AD's comparator output V comp , which is the key signal in the zero-crossing detection process of I peh .The zoomed-in view shows that the comparator trips at delta = 30 s ahead of the actual zero crossing moment of I peh .This is due to the negative offset of the AD comparator.However, as delta represents only 0.6% of half the period of I peh , it has negligi- ble impact on the system's efficiency.Figure 13 also shows that V comp returns to zero after the comparator has tripped.As mentioned in 3.4, this is due to the charge injection on V sp after disconnecting this node from both C L and C peh .For this reason, connecting the node V sp to ground and blocking the AD during the voltage flip operation is mandatory to avoid the instability of the AD comparator, which would lead to a significant increase in its consumption and affect the system's efficiency.

Experimental results and discussion
The FAR-FC prototype was designed and fabricated in AMS-0.35μmCMOS technology.Fig. 14 shows the micrograph of the ASIC with all the featured blocks outlined, and the measurement setup.All blocks are fully integrated except the D/B block where the 3 flipping capacitors mentioned in Sect. 3 are implemented off-chip.The active area of the ASIC is 7.29mm 2 and the estimated Fig. 11 Simulated V peh and V rect of the 3cap-SSHC [32] and the proposed FAR-FC architectures, with no regulation Fig. 12 Simulated V peh and V rect of the 3cap-SSHC [32] and the proposed FAR-FC architectures, with regulation total volume occupied by the off-chip flipping capacitors is about 5.4mm 3 .The PT is excited by an LDS® V400 series shaker, driven by an AC power source 6813B by Agilent®.The excitation signal is a 100Hz sine waveform.The mechanical acceleration of the shaker was set so as to get Voc = 1V .A LabVIEW® platform performs both the control of the shaker and the signal acquisition via an oscilloscope.The extracted energy is stored on a conventional capacitor C L = 100 F.
Figure 15 (left) shows the measured waveform of V peh and V rect .As V rect is regulated to 1.6V, the voltage across C peh is about V b = 1.24V after the voltage inversion opera- tion.This corresponds to 88.75% voltage flip efficiency.This value is slightly lower but yet very close to the simulated one ( 90.6% ).The reason is the series resistance of  the T-gate switches combined to total parasitic capacitance of the interconnections between the test board and the PT which increase the time constant.Figure 15 (right) shows the detailed evolution of V peh during the 9-phase voltage flip operation.A phase duration PW = 32 s was empirically determined to reach the optimal voltage efficiency mentioned above.
To evaluate the performance of the FAR-FC, we measured the output power.For this experiment, we connected a variable resistor to the FAR-FC output and disabled the voltage regulator.Figure 16 shows the output power of FAR-FC for different V rect compared to the output power of an off-chip Schottky-diode-based FBR.The measured threshold voltage of the Schottky diodes is around V th ≈ 0.05V , which is con- sistent with the diode's specifications with a forward current I F ≈ 8 A at 30 • C [41].This yields a maximum output power of 7.98 W when V rect = 0.4V .With FAR-FC, the maximum output power increases to 45 W at V rect ≈ 1.6V leading to a MOPIR of 5.64.This result is consistent with the theoretical MOPIR estimated in 3.5 because the threshold voltage at low current of the Schottky diodes is much lower than that of integrated silicon diodes.Figure 16 (left) also shows that for V rect lower than 0.9V, the FAR-FC turns off.In fact, for V rect = 0.9V , the output voltage of the integrated charge pump CP, normally dedicated to supply the circuit with 3V, decreases to 1.8V, which is not sufficient to fully turn ON/ OFF the TG switches in this technology.
We also measured the FAR-FC performance for different pulse widths PW as shown in Fig. 16 (right).It is clear that best power performance is achieved when PW is set to 32 s .Furthermore, increasing the pulse width to more than 32 s leads to decrease the conduction time and thus to decrease the output power.
Table 2 lists the measured power consumption of the different blocks of FAR-FC circuit.The total consumption is 4.24 W representing 9.42% of the total extracted power and 90.58% system efficiency.
Table 3 summarizes the key characteristics and performance of the proposed FAR-FC chip compared with the reported state-of-the-art architectures.As can be noticed, most interface circuits presented in the literature report Voc higher than 1V.It is thus difficult to make a fair comparison with our work.However, [37] report about the output power when V oc ≃ 1V .As can be noticed, the maximum extracted power in [37] significantly decreases from 24.2 W to 4.7 W when the Voc decreases from 2.75V to 1.02V.In contrast, the FAR-FC circuit can extract 45 W , which is 9.5× higher than the maximum power extracted by [37].This table also shows that the proposed FAR-FC can work with a high PT inherent capacitance value, i.e. 100nF, while the value reported in the state of the art circuits is lower than 50nF.In particular, SSHC architectures that require a large number of phase [32,34,40] need to keep C peh as low as possible to limit the RC constant that hampers the voltage flipping speed.The optimized architecture of FAR-FC, combining the reduced ninephases flipping process and the reduced maximum number of series switches (i.e. 3) in the D/B array, alleviates the constraint on the C peh compared to other works, extending the variety of the PTs compatible with the proposed energy harvesting interface.

Conclusion
This paper presented an optimized SSHC interface circuit (FAR-FC) for piezoelectric energy harvesting.While the reported state-of-the-art architectures use either a large inductor (SSHI) or a large number of flipping capacitors/ phases (SSHC), the FAR-FC employs only three flipping  capacitors to achieve high power efficiency.Simulation results shows that the FAR-FC improves the voltage flip efficiency by 10.6% compared to the state-of-the-art threecapacitor SSHC circuit.This yields 37.91% maximum output power improvement.Moreover, measurement results show that the FAR-FC circuit can deliver up to 45 W with 88.75% voltage flip efficiency when Voc is only 1V, while most state-of-the-art works report Voc > 2V .This ensures sufficient energy harvesting even under tight operation conditions, i.e. the PT is weakly excited.Measurement results also reveal that the FAR-FC achieves 5.64× power perfor- mance improvement compared to a conventional diodebased FBR.Furthermore, its optimized architecture allows the proposed FAR-FC circuit to be used with a wide range of PT capacitance ( C peh ) values, i.e. up to 100nF or more.The future work is currently addressing a dynamic FAR-FC able to deal with varying mechanical excitation (i.e.different values of Voc ).

Figure 6 (
Figure 6 (left) shows the circuit diagram of this block.It consists of five switches named after their control signals and an active diode (AD) controlled by the CTRL block as shown in the following sub-sections.The rectification switches ( SW 1 , SW 2 ) are used to rectify the voltage across the PT.During the positive phase of V peh , the switches con- trolled by SW 1 and SW 2 signals are ON and OFF, respectively and vice versa during the negative phase.As a result, the node V sp is permanently connected to the positive terminal of the PT, i.e.V peh is rectified.The AD, shown in Fig.6(right), is used to both prevent the current backflow from C L to PT and detect the zero cross- ing moment of the PT current.It consists of an ultra-low power comparator[32] and a PMOS switch.When V rect , the voltage across C L , becomes larger than the voltage at node V sp , i.e. the current changes its direction, the comparator output V comp goes high.This signal is used by the CTRL block to both turn off the PMOS switch, thus preventing the

Fig. 13
Fig. 13 Waveforms of V peh , V comp and I peh .The zoomed-in view (right) shows the offset of the AD comparator and the glitchy behaviour of V comp due to the charge injection in SW 1 and SW 2

Fig. 16
Fig. 16 Output power of both FBR and FAR-FC (left), FAR-FC output power for different PW duration (right)

Table 2
Measured power breakdown of FAR-FC

Table 3
FAR-FC performance compared to the state of the art