Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling

Recently, transistors with an underlapped gate structure have been widely studied to overcome several challenges associated with nanoscale devices. In this work, underlap region is incorporated at source and drain (S/D) ends in a fully depleted Strained Silicon On Insulator (SSOI) device, with high-k dielectric material in the spacer region. The S/D underlapped region helps to reduce the leakage current and can be particularly useful for low power applications. However, increased underlap length degrades the ON current significantly. We show that this issue can be mitigated via the inclusion of a high-k spacer, which improves the ON current by enhancing the gate controllability over the S/D underlap channel region. It helps to achieve the essential requirement low power applications i.e. the high ON/OFF current ratio at extremely low value of leakage current. The strained silicon material is used in the channel region to further improve the ON current. A compact threshold voltage model is developed for the proposed device (underlap-SSOI) while maintaining the accuracy at par with TCAD simulations. This threshold voltage model incorporates underlap length, strain-induced offsets and spacer dielectric constant. This device model may be used for circuit simulations.


Introduction
In the nanoscale regime, the increased short channel effects (SCEs), parasitic capacitances and leakage current, all restrict the scaling of bulk MOSFET technology. The fully depleted Silicon On Insulator (SOI) structure has received attention as a method of achieving high performance and enhancing the scalability [1,2]. The advantages of SOI has been come from low device variability due to low channel doping, superior SCEs control due to elimination of leakage path, low parasitic capacitance and excellent compatibility with current bulk MOSFET technology [3,4]. These entire features are very useful for low power and low standby power applications such as Internet of Things (IoT), consumer multimedia, wearables, System on Chip (SoC) integration etc. [4]. However, the distance between the source and drain regions becomes very small in nanoscale overlap strained SOI (overlap-SSOI) devices. As a result, gate control over the channel current is reduced and the drain becomes prominent in governing the electric potential across the device channel. The dominance of drain voltage (V DS ) increases the drain induced barrier lowering (DIBL) effect and leakage current in the device [5]. To alleviate these problems, various advanced structures have been studied such as the FinFET [6], the silicon nanowire FET [7], CNT FET [8] and quadruple-gate MOSFET [9,10]. However, these structures are vulnerable to process variability, are difficult to realize, are costly and have complex fabrication techniques [11][12][13][14]. Alternatively, underlap structures have been reported in refs. 15-19 as a way to control SCEs especially a leakage current problem. The underlap region increases the distance between source and drain (S/D), and reduces the drain dominance over the channel electric potential. However, there is further scope for improvement in underlap devices as this modification has resulted in degradation of the ON current due to the increase in the S/D series resistance [19,20].
Various performance booster techniques required to maintain the inevitable trend of downscaling. In this direction, strain engineering has been investigated as one of the most prominent solutions to achieve high ON current with the present fabrication techniques. The strained devices show high driving capability due to enhanced carrier mobility [21]. A strained Si layer, of desired thickness, is used as the channel in SOI MOSFETs, using layer transfer (LT) techniques [22]. Moreover, recent work suggests that the high-k dielectric material as a spacer region enhances the ON current in underlap devices without degrading the OFF current and intrinsic delay of the device [18]. The International Technology Roadmap for Semiconductors (ITRS) has recommended that one of, or a combination of, the new techniques is required to continue the performance improvement in low power applications [23]. Therefore, in this work, an underlapped fully depleted strained SOI MOSFET with high-k spacer, termed as underlap-SSOI, is proposed, as shown in Fig. 1. This structure has been analyzed across the key performance metrics of: leakage current, ON current, total gate capacitance and gate delay, with the objective of achieving low power consumption.
Based on our earlier work [24], the innovative modeling approach is adapted here to develop a threshold voltage model for the underlap-SSOI structure. The threshold voltage model includes the effects of strain induced offsets, underlap length, gate length, spacer dielectric constant and channel doping.
The model results have been compared with TCAD simulations in order to establish the accuracy of the model.

Device Design and Performance Evaluation
In this section, an n-channel underlap-SSOI device is designed and compared to the performance of conventional overlap-SSOI devices. In Fig. 1, the gate underlap regions can be seen as those lengths L 1 and L 2 , between the source and the gate, and the drain and the gate, respectively. A high-k dielectric material is used to form gate oxide, spacer1 and spacer2. Strained Si is used as body of the device, with a thickness of t SSi . Channel region along the x-axis from 0 to L 1 + L + L 2 , as shown in Fig. 1, is separated into three regions, Region1, Region2 and Region3 of length 0 < x < L 1 , L 1 < x < L + L 1 and L + L 1 < x < L + L 1 + L 2 respectively. The device dimensions and electrical parameters of underlap-SSOI structure are given in Table 1.
In order to evaluate the performance of the underlap-SSOI structure, TCAD simulations are carried out using the Synopsys Sentaurus TCAD Tool, as shown in Figs. 2 to 5. In addition to the drift-diffusion transport model, the Enhanced Lombardi model with high-k mobility degradation has been enabled to account for remote coulomb scattering (RCS) and remote phonon scattering (RPS) at the high-k/ channel interface [25]. The bandgap narrowing and strain effect has been taken into consideration using Slotboom model and Monte Carlo-computed mobility for strained Si respectively [25].
The simulation results of underlap-SSOI and overlap-SSOI have been compared to experimental data of [26] as shown in Fig. 2a. Here, it is important to note that the difference between the ON current values of underlap-SSOI and overlap-SSOI is decreasing with the decrease in gate voltage. It indicates that underlap-SSOI is beneficial for low voltage operations since the I ON of underlap-SSOI is comparable to overlap-SSOI for lower gate voltage. It has also been observed that the I ON values of simulations are in the good agreement with reported experimental results [26]. Figure 2b shows the I ON   Fig. 2b that I OFF decreases significantly with L n due to reduction in charge sharing between gate and S/D regions. A small degradation in I ON is also observed with increasing L n due to an increase in the effective channel length. The I ON /I OFF current ratio of the SSOI device is slightly lower than that of the SOI device in the overlap region due to increased I OFF . However, the I ON /I OFF ratio has significantly improved in the underlap region up to L n = 4 nm, as I OFF is reduced exponentially with increasing value of L n . Thus, the results indicate that the underlap-SSOI structure with L n of 4 nm maximizes performance.
The underlap length increases the effective channel length which increases the channel resistance and lowers the I ON . The channel resistance in the underlap region has been reduced via the incorporation of a high-k spacer. The high-k spacer also reduces the I OFF due to high potential barrier in the OFF condition [27]. In this way, both I ON and I OFF improves with increasing spacer relative permittivity (ε sp ), as shown in Fig. 3. However, the use of the high-k spacer increases the parasitic capacitance in both the underlap and overlap structures.
The comparison of the total gate capacitances (C gg ) of the underlap-SSOI device versus that of the overlap-SSOI device, as a function of ε sp , has been shown in Fig. 4. The total gate capacitance is combination of gate capacitance and parasitic capacitances i.e. overlap capacitance, outer fringe capacitance (C FO ) and inner fringe capacitance (C FI ). The value of parasitic capacitance depends upon the region of operation [28]. In the saturation condition, the parasitic capacitance is modeled with the equation for underlap devices as for overlap devices [29] and a similar trend is observed from simulation resultssee Fig. 4.
For the high-k spacer, the larger C gg value results in higher intrinsic gate delay (CV/I), as depicted in Fig. 5. In the underlap-SSOI device, we observe a 6% increase in delay   for HfO 2 (ε sp = 22) spacer as compared to SiO 2 (ε sp = 3.9) spacer. On the other side, the HfO 2 spacer increases I ON and decreases I OFF by 45% and 25%, respectively, as shown in Fig. 3. It is important to note in Fig. 5 that the delay penalty of the underlap-SSOI device (using an HfO 2 spacer) is only 7% higher than that of the overlap-SSOI device, when the poor turn ON characteristics of the underlap-SSOI structure is taken into account. However, the HfO 2 spacer has increased the I ON / I OFF ratio by 470% (calculated from Fig. 3) for the underlap-SSOI device compared to the overlap-SSOI device. Therefore, in many cases, such as low power and low frequency circuit design, this may be a beneficial trade-off.

Impact of Strain on Various Parameters of Underlap-SSOI
The use of strained Si as the channel material in MOSFET technology has attracted the interest of researchers due to significant resulting improvement in device performance. In the present work, the strained Si layer, without the presence of relaxed SiGe, is used as the channel in the underlap SOI device to avoid the disadvantages of the SiGe layer [30].

Strain Induced Bandgap Offset
Strain causes an energy offset in the conduction and valence bands of Si. The presence of strain causes the six-fold degenerate valleys of the conduction band minimum to split into two groups i.e. two lower valleys and four raised valleys. This leads to an offset in the conduction band, bandgap and density of states. These energy offsets have been modeled in the literature as a function of Ge mole fraction [31,32] i.e. x: where x is Ge mole fraction, (ΔE C ) SSi is conduction band offset due to strain, E C,Si is conduction band for unstrained silicon, E C,SSi is conduction band for strained silicon, (ΔE g ) SSi is the bandgap offset due to strain, E G,Si is bandgap for unstrained silicon, E G,SSi is bandgap for strained silicon, V T is the thermal voltage, N V,Si and N V,SSi are the density of states in the valence band in unstrained and strained Si respectively.

Strain Induced Flat Band Offset
The changes in front channel flat-band voltage of underlap-SSOI, due to the offset in bandgap and conduction band can be given as [32]: where (V FB_f ) SSi and (V FB_f ) Si are the front channel flat-band voltage of strained and unstrained Si respectively, ΔV FB,f change in front channel flat-band voltage due to strain, ϕ M and ϕ Si are the gate work function and unstrained Si work function respectively. In the same way, the back channel flat-band voltage of underlap-SSOI can be modified as given below: where ϕ sub is the substrate work function. Similarly, the built-in potential at the interface of source and channel in strained Si channel as a function of strain can be formulated as: where

Model Formulation
The analytical threshold voltage model has been derived based upon the surface potential model by solving the 2D Poisson equation for the underlap-SSOI structure. This model formulation is different from the earlier model as the strain induced effect and the high-k spacer parameters have not been included in that model [24]. Figure 1 shows the schematic of underlap-SSOI with high-k spacer around gate. Channel region, beneath gate and spacer dielectric, is break up into three regions: region1, region2 and region3 with L 1 , L & L 2 lengths respectively. The potential profile in Si channel before the strong inversion condition can be expressed by Poisson equation as [33]:

Formulation of Surface Potential
where ϕ (x, y), ε si , N A , L and t SSi is the 2-D potential, dielectric constant of Si, p-type channel doping concentration, gate length and strained Si body thickness respectively. Region along y-axis is given as: The channel of underlap-SSOI has three regions and thereby potential distribution, ϕ given in Eq. (8) divided into three regions i.e. ϕ 1 , ϕ 2 and ϕ 3 as given below: where ϕ s1 , ϕ s2 and ϕ s3 are the channel surface potentials under region1, region2 and region3 respectively. Above coefficients C 11 (x) to C 32 (x) are functions of x (length along X-axis) and obtained via the following boundary conditions: The electric flux continuity at the interface of strained Sichannel/gate-oxide, strained Si-channel/region1 and strained Si-channel/region2 is given as: The effective gate to source voltage (V GS ' ) is given by where V GS is the applied gate to source bias voltage V FB_b is the back channel flat-band voltage. Mathematically, surface potential at source end is described as: Similarly, surface potential at drain end is described as: Electric flux at the interface of BOX/back channel is continuous for all three regions and is given as: where t b and ϕ b is the BOX thickness and back channel potential at the BOX/strained Si-channel interface respectively. Effective substrate bias voltage is given as V sub ' = V sub -(V FB_b ) SSi where V GS is the applied gate to source bias voltage. Electric flux continuity at the interface of spacer1/metal-gate and spacer2/metal-gate is represented as: Surface potential in region1, region2 and region3 is continuous which is given as: The coefficients C 11 (x) to C 32 (x) given in Eqs. (9)-(11) are calculated by boundary conditions (12)- (14) and (18)- (20). By taking the derivative of Eqs. (9)-(11) as per Eq. (7) which result in following equation: where α 1 , α 2 , α 3 , β 1 , β 2 and β 3 are constants and their calculated values are given below: In the above model Eqs. (28)- (31), capacitances values are front gate oxide (C f = ε ox /t f ), BOX capacitance (C b = ε box /t b ) and strained silicon channel capacitance (C si = ε si /t SSi ). The Eqs. (25)- (27) is solved further for formulating the surface potential for three different regions i.e. Region1, Region2 and Region3 as follows:

Formulation of Threshold Voltage
In this section, the threshold voltage is obtained by solving the surface potential equations for the underlap-SSOI device structure. It is well known that the threshold voltage is the gate voltage (V GS ) at which the minimum surface potential (ϕ s,min ) in channel region is equal to twice the body Fermi potential (ϕ F ). The ϕ s,min occurs at the minimum value of x (x min ). The x min is derived from Eq. (32) as follows: The ϕ s,min is equal to the threshold potential (ϕ th ) because ϕ th is the minimum potential at which surface carrier density get inverted. The A and B factors are determined from (32)-(34) by using boundary conditions described in (16)- (17) and (21)-(24) respectively. The calculated value of A and B are given below: where the associated constants are given as: The gate to source voltage (V GS ) is derived by solving (36) using (37, 38). Here, the V GS is solved for minimum surface potential condition and it is defined as threshold voltage V th as follows: where the values of constants i.e. V t1 , V t2 and γ are given in appendix.

Model Validation and Discussion
In Fig. 6, both the model and simulated data points of the surface potential have been plotted along the channel direction for underlap-SOI device at V DS = 0.2 V, 0.5 V and 1 V. It is observed from the figure that there is insignificant change occurring in surface potential under the gate terminal due to the presence of Gate-S/D underlap region. The impact of the drain potential has been restricted near the drain terminal only. Consequently, the drain voltage has less control over the ON current after saturation, which is required for low power circuit design. It is seen in the inset of Fig. 6 that the surface potential minimum is shifted only 17 mV when the drain potential is increases from 0.2 V to 1 V. This lower change in the position of surface potential minima with drain voltage leads to reduced DIBL for underlap-SOI device. Further, the model results track the numerical results very closely which establishes the accuracy of the proposed model.
The variation of threshold voltage of underlap-SSOI with Ge mole fraction (x) is shown in Fig. 7. A larger value of x reduces the energy bandgap since the bandgap offset is directly proportional to x, as given in (2). Consequently, the flatband voltage and built-in potential at S/D-channel interface has decreased. This causes the earlier onset of inversion layer in strained Si and leads to decrease in threshold voltage as shown in Fig. 7. Very high value of x (generally greater than 0.4) for a given channel thickness leads to strain relaxation due to formation of dislocations [34]. Thus, strain relaxation puts the upper limit on x value. On the other side, the lower value of x reduces the ON current due to the increase in threshold voltage. Thus, the optimum value of x can be obtained according to the required value of threshold voltage. Further, the threshold voltage calculated from model equations follow the simulation results closely thereby establishing the model accuracy. Figure 8 demonstrates the threshold voltage as a function of underlap length for different value of Ge mole fraction; x = 0.2, 0.25 and 0.3. Here the negative values of underlap length represent the overlap length between gate and S/D regions. The threshold voltage is found to be increasing with increase in underlap length. This owes to increase in series resistance for higher value of underlap length. In this way, underlap structure provides additional flexibility to achieve the desired value of the threshold voltage.
The threshold voltage decreases with decrease in channel length from 90 nm to 15 nm as seen in Fig. 9. Reduction in threshold voltage with channel length is called as threshold voltage roll-off (ΔV TH ). This is undesirable effect and it should be low for high performance nanoscale devices. The presence of S/D underlap region increases the threshold voltage (as observed in Fig. 8) which helps to reduce the ΔV TH with the channel length scaling. Consequently, low value of  The metal gate work function is a key parameter in obtaining the threshold voltage. Figure 10 shows the plot of the threshold voltage versus metal gate work function. It is clear that the threshold voltage becomes large for higher values of the metal gate work function since the metal gate work function has a direct relationship with the threshold voltage. The same trend is found in Fig. 10

Conclusion
In this work, an underlap-SSOI structure with high-k spacer is proposed to mitigate the leakage current and SCEs with the aim of enabling continued scaling for low power applications. Inclusion of underlap region in SOI structure exponentially reduces the leakage current i.e. 509%. On the other hand, underlap region degrades the ON current. In proposed structure, ON current enhances by incorporating strained Si and a high-k spacer region, without degrading the intrinsic delay of the proposed device. Using HfO 2 as the material for the high-k spacer region allows direction of the gate-fringing field towards the channel region, which helps to enhance the ON current by 45% as well as reducing the OFF current by 25%. Further, a 2D threshold voltage model is formulated for the underlap-SSOI structures by incorporating strain induced effects to formulate a new analytical model. The close match between model results and numerical simulations establishes the accuracy of proposed model. The model results show that the proposed structure achieves lower threshold-voltage roll off and provides enhanced controllability on threshold voltage as compared to conventional SOI MOSFETs.
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