Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD

A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).


Introduction
The conventional device metal-oxide-semiconductor fieldeffect transistors (MOSFET) is now saturated before further scaling due to its short channel effects, high leakage current etc. Among new devices-tunnel field-effect transistors (TFETs) are promising future benchmark device to replace the CMOS [1,2] due to their potential for very low off current as compared to MOSFET [3], sub-60mV/dec subthreshold swing [4][5][6] and higher reliability with respect to temperature changes [7,8], while for MOSFET sub-threshold swing at room temperature is 60mV/dec and it increases with temperature. The reduced swing is an essential requirement for the ultra-low power operation for the next generation of transistors. Researchers are finding Tunnel FET Menka Yadav menka.ece@mnit.ac.in The device under study is shown in Fig. 1 with channel width-50 nm, source/drain extension length 100 nm, high-κ thickness 3 nm. In this work an inverter is prepared to see the effects of source/drain extension width changes and then it is used for ring oscillator design.
With device miniaturization, there is a huge demand to develop an oscillator which can be fabricated with the chip with low cost and better reliability. Earlier days quartz crystal oscillator and L-C tank oscillators were used which are proving very heavy oscillators now a days. So, research is going on towards a low cost solution for frequency generator on the chip and one of such solution is RO, which can be fully fabricated along the chip and the output frequency can be tuned with variations in the supply voltage, thus it works like voltage control oscillator (VCO). There are different topologies used for ring oscillator to make it more reliable and low power consuming oscillator.
Ring oscillators have a wide variety of applications in transmitter and receiver systems of communication, control and feedback systems, as VCO in Phase Locked Loops, and others. Since the TFET ring oscillators are expected to perform reliably even at higher temperatures (virtue of TFETs) [8], so when the device sizes are shrinking and power density is increasing the RO with TFET can give more reliable results as compared to the CMOS technology. Thus in this work, focus is on RO design and analysis with different parameters of the device or the supply voltage, like-the effect of drain extension region widths of Tunnel FET has been studied for the inverter DC, Voltage Transfer Characteristics (VTC), and transient characteristics, and for ring oscillator application as well. The supply voltage variations and its effects on the characteristics of inverter and ring oscillator have also been explored in this work. A NSD-RO is presented to make the ring oscillator frequency more stable, and with less jitter as compared with singleended ring oscillator topology.
The work done in this paper is as follows: Simulation setup and TFET device calibration are presented in Section 2, Inverter Analysis in detail is presented in Section 3, Ring Oscillator is presented in Section 4 and the last section concludes the work done.

Simulation Setup and TFET Device Calibration
In the whole work, the simulations are performed using TCAD sdevice Sentaurus simulator [24]. The models included are -non local tunneling model, Wentzel-Kramers-Brillouin (WKB) is used with Fermi statistics, band-gap narrowing model, OldSlotboom, is included without Fermi statistics, high field saturation mobility models, carrier transport model, Shockley Reed Hall (SRH), and Auger carrier recombination, eMLDA, and hMLDA models are included for density correction due to energy quantization. The doping profiles used in the device are abrupt to make more carriers to tunnel during device ON condition. For n-type impurity, phosphorus as a pentavalent impurities is used.
The working of TFET can also be understood with the help of energy band diagrams presented in Fig. 2, here. energy band diagrams for +ve and -ve V GS are shown to understand the subsequent electrical characterics of Inverter and Ring Oscillator. The device under study is calibrated against data given in [25], which was already calibrated against experimental data. For calibration, the electron, and hole effective masses have been tuned to match the tunneling current while for recombination current calibration, the carrier life times have been tuned. The electron/hole effective masses used in the study are 0.29m 0 /0.36m 0 respectively, where m 0 is the rest mass of the electron, and the carrier life times tuned for electron/hole are 10μs/3μs respectively. The calibrated results are shown in Fig. 3. The calibration is done with intention to keep the reported result and TCAD simulation results within an error of ±4%. For device calibration the tuning of carrier life times and carrier effective mass has been done [26][27][28][29]. For n-TFET, Source is p-type with doping concentration 10 20 /cm 3 , drain is n-type with doping concentration 5 × 10 18 /cm 3 and the channel region is lightly p-type doped with doping concentration 10 17 /cm 3 , Gate work function used in the simulations is 4.5 eV. Correspondingly for p-TFET doping profiles are same but the material is changed, gate work function is 5.4 eV. The below Table 1 lists all related dimensions of Tunnel FET.

Inverter Analysis
Ring oscillator is a chain of odd number of inverters connected one after other, and the last inverter is connected back to the input of first inverter to meet the sustained oscillations criteria as shown in Fig. 9. Since inverter is the basic element for RO, so characteristics of Complementary TFET (C-TFET) based inverter are analysed here, which further can be helpful to understand the possible applications of TFET in the digital and/or analog domain. Thus different characteristics are investigated for C-TFET based inverter.  [25] (which is already calibrated against the experimental data presented Bhuwalka et al.,), for this calibration all physical dimensions are used from [25], DG Tunnel FET with high-k gate oxide with EOT=0.9nm, channel length L=20 nm, Silicon thickness T Si = 10nm, V ds = 1V N dp -drain doping 5 × 10 18 /cm 3 9 φ m -gate metal work-function 4.5 eV (n-type) 5.4 eV (p-type) 10 Carrier life times electron/hole 10μs/3μs 12 effective mass electron/hole 0.29m 0 /0.36m 0 The schematics for C-TFET inverter is shown in Fig. 4. All simulations are performed using Sentaurus TCAD (sdevice) with device channel material as Silicon and gate insulator material used as Hf O 2 .

Static Transfer Characteristics
The static transfer characteristics for both N-channel and P-channel Si DG Tunnel FETs are discussed in this section to understand the characteristics basic C-TFET inverter.
To explain the static characteristics, a resistive equivalent circuit of a TFET is taken into account by considering R S /R D source/drain extension region resistances respectively which are fixed and independent on the applied gate/drain bias voltages, R T is the tunnel junction resistance which completely depends on the applied gate, and drain voltages. This tunnel junction barrier decreases with both applied drain, and gate voltage as well. R C −is the channel resistance. The static transfer characteristics are represented in Fig. 5. It is clear from these plots that the drain current of the device (N-channel or P-channel TFET) increases with the extension region width. Here the static voltage transfer characteristics of an inverter are shown in Fig. 6.
Since the tunnel FET current is heavily controlled by the tunnel junction resistance R T and also by R S , R D , R C as well. Here R T is a function of both gate and drain voltages, thus it will change drastically as V gs or V ds is changed. R T is very high at lower drain/gate voltages, thus the drain current is very low for lower drain/gate voltages. As soon as the carriers start tunneling at the source/channel junction, the drain current is controlled by R D and R C , where drain/source extension region resistances (R S and R D ) will get reduced with increasing in width of extension region, which in turn increases the drain current of the TFET devices, as shown in Fig. 6a and b.

Voltage Transfer Characteristics
For digital systems/circuit applications, the voltage transfer characteristics (VTC) for C-TFET inverter plays significant role while the inverter gain plots are useful for analog domain applications such as sensors, amplifiers etc. The VTC for C-TFET inverter for different power supplies ranging from V dd =1.5V to 2.0V are shown in Fig. 6a. A very very small change in the VTCs with variations in extension region width (T ext ) have been observed for C-TFET inverter, therefore, VTCs for different extension region widths are not shown separately. T ext = 10 nm have been used for VTCs.
Different noise margins are observed for different power supplies. The noise margins for all power supplies are listed   Table 2. Here the lower noise margins (NM L ) are lesser than higher noise margins (NM H ), which indicates that the pull-up transistors (P-channel TFETs) are stronger than the pull-down transistors (N-channel TFETs). The lower noise margins vary from 40% to 41% while the higher noise margins are in a range of 42% to 43.5% of the power supply.
From the above discussion, it can be concluded that there is a sharper transition from high to low and vice versa (¡20% of V dd ) for these inverters. The inverter gain, which is very much useful for analog applications is shown in Fig. 6b. It is seen that the inverter gain is better for higher power supplies as in the case of MOSFETs [30]. Better inverter gain makes it suitable for amplifier applications. One such application Operational Trans-conductance Amplifier (OTA) has been presented in [31].

Transient Characteristics
Inverter's transient characteristics are useful for analysis related to timing, overshoot, undershoot etc. The transient characteristics for both of TFET structures given in Fig. 1 are presented in Fig. 7, a very minute difference between the two transient waveform of output voltages V out , for both the structures have been observed, but still there is Table 2 Inverter noise margins for source/drain extension region widths T ext = 10nm and power supply V dd = 1.5V , 1.8V and 2.0V a difference in terms of the peak undershoot, overshoot, and inverter's delay. Inverter delay will be discussed in the next Section 4, with RO. The peak overshoot, and undershoot occurs because of Miller capacitance, which is more for TFETs as compared with MOSFETs [32,33] which makes the undershoots and overshoots higher for TFET as compared to MOSFET as shown in Figs. 7 and 8, for CMOS the simulation has been done online for 0.35μm gate length (aim is just to shown that there is no overshoot and undershoot in case of CMOS) using NGSPICE online simulator, even if the CMOS inverter simulations are done for higher V dd (up to 3V for this technology node) the undershoot and overshoot are observed much far lesser than TFET.
For both of TFET structures, the fringe capacitance is different. The fringe capacitance is given as shown in Eq. 1. Gate drain capacitance (C gd ) is the sum of fringe capacitance (C f ringe ) and the gate-drain overlap capacitance (C gdov ) (2) [34], Miller capacitance for a complementary TFET inverter is the sum of gate drain capacitances of both nTFET and pTFET [32,33]. Thus the fringe capacitance has its own effect on the transient characteristics.
Since the average fringe width T f ringe gets reduced as the extension region width T ext increases, this will cause the fringe capacitance in Eq. 1 to increase while the extension region resistances R S , and R D to decrease. The combined effect of both of these will decide the peak overshoot, undershoot, and low-to-high (T plh ), and high-tolow (T phl ) inverter delay. The average propagation delay (T d ) of inverter is estimated by Eq. 4 [34].
The transient characteristics for V dd =1.5V are shown in Fig. 7a, and the undershoot, overshoot are shown in Fig. 7b for extension region width 10 nm and 36 nm. Although the study is carried out for intermediate extension region widths as well, but in order to avoid complexities in diagrams, only 10 nm, and 36 nm results are presented. It is clear that at higher T ext , a higher value of the peak overshoot, and undershoot potentials are obtained, which is because of increased fringe capacitance, while T phl and T plh will get reduced with the increased T ext due to reduced extension region resistances.
Here Fig. 8, SPICE simulated graph is included just to show that the overshoot and undershoot in CMOS based inverter is negligible as compared to CTFET inverter at the same power supply, (here technology node is different because for TFET higher supply voltage is needed as compared to MOSFETs).

Ring Oscillator Application
Ring oscillator can be fabricated along the chip which contains odd number of inverters connected back to back in order to meet Barkhausen criteria for self sustained oscillations i.e. it must provide a phase shift of 2π and have unity close loop gain. The frequency of the oscillations can be controlled by supply voltage variations thus is can be refered as VCO.
In an n-stage ring oscillator the phase shift of π/n is provided by each inverter stage, the rest π phase shift is provided by the static inversion. The frequency (f ) of ring oscillator is given by Eq. 5. It can be seen here the frequency of oscillation is inversely proportional to the number of stages (n) used in the ring oscillator. Thus larger the number of stages, lesser the frequency of operation (if the single inverter stage delay T d is constant).
Ring Oscillator time period T RO = 2 * n * T d .
To investigate the effect of drain extension width (T ext ) and supply voltage (V dd ) variations -on RO frequency, a simulation based study is performed for various parametric variations. A three stage ring oscillator is presented in Fig. 9, which is the minimum possible number of stages in RO. The RO is most widely used in PPLs, VCOs, clock generation, communication, multi-phase outputs etc.
A three stage ring oscillator is simulated with V dd = 1.5V and the output self sustained oscillations are represented in Fig. 10. Here the oscillations exceed the power Fig. 9 Three stage single ended ring oscillator under study supply voltage level because of higher Miller capacitance in TFETs as compared to CMOS RO, where the oscillations are within 0 to V dd range and overshoot/undershoot voltages are very small as compared to the TFET based inverter as shown in Fig. 11.
The oscillation does not start immediately but it starts after certain time period Fig. 10a, this time period is known as oscillator's warm-up time. During this time period all inverter stages have constant and same in magnitude and phase outputs which are equal to V dd /2. After the warmup phase the oscillator starts oscillations which will attain a fix frequency after a small time duration. Now the outputs of the different stages will be π n out of phase but same in magnitude and T jitter induced by each RO inverter stage.
The simulations are performed using three stages of inverters for Tables 3 and 4. In Table 3, a fixed T ext =10 nm is taken and power supply voltage is varied from 1.5 V to 2.0 V. and various T ext from 10 nm to 36 nm. It is clear from Table 3 and Fig. 12, as the power supply is increased f RO also increases as in case of CMOS based inverters [30] and the overshoot of the inverters is also increased. There is a distorted waveform for oscillations   Table 3 Oscillation time and frequency for different power supplies for simple single ended TFET-three stage RO with T ext = 10nm which can be improved by using increasing the number of inverter stages but it will also cause lower frequency output. The speed of operation i.e. frequency of C-TFET ring oscillator is lesser as compared with CMOS RO at the same power supply (Table 3), while the peak overshoot is much higher as compared with CMOS because of increased Miller capacitance in TFETs [32,33].
Here V peak is the peak overshoot voltage of ring oscillator, T RO is the time period of each output of RO, f RO = 1/T RO is the frequency of oscillation for RO, T d = T RO / (2 * n) is single inverter delay calculated from RO.
To see the effect of T ext on the ring oscillator, the T ext is varied from 10 nm to 36 nm in structure of RO with V dd =2.0 V, as shown in Table 4 and Fig. 12. Here the speed of operation increases at the cost of increased overshoot and undershoot. As the drain extension region width T ext is increased the Miller capacitance will also get increased as shown in Eqs. 2, and 1. This enhanced Miller capacitance increases the peak overshoot and undershoots. Although the Miller capacitance has been increased but a reduction in the extension region resistance R d is seen due to width increase. The combined effect of R d and C Miller will increase the speed of operation as shown in Table 4. The effect of T ext and V dd on the frequency of RO is also presented in Fig. 12. Further, as the number of stages is increased from three to five the frequency will decrease according to Eq. 5, the same can be compared from Tables 3 and 5.
The single ended topology of ring oscillator is the simplest form of oscillator, but the frequency of this oscillator is not fix, it suffers from higher jitter (ΔT ) -a time delay is induced in the next cycle. To overcome the effect of jitter and to make the oscillator a bit faster NSD ring oscillator topology is proposed in [35]. To see details and the circuitlevel diagram of simple (single ended inverter based RO) and NSD ring oscillator topology are shown in Figs. 9 and 13 respectively. In NSD ring oscillator topology the nTFETs are having connected in the same manner while the pTFETs are fed inputs from (n − 2) th stage in order to reduce the jitter and make the oscillator faster. The simple topology can have even three stages also but the NSD ring oscillator topology can minimum have five stages. The NSD ring oscillator topology is faster because its oscillation has much smaller magnitude as compared to the single ended inverter topology of ring oscillators as presented in Table 5, thus lesser time is required to switch in either states. Comparison of frequency of operation at V dd = 1.8V is presented in Table 5. It is found that the frequency of operation in case of NSD RO is 3.65X times of the simple single ended RO, this happens because the amplitude of sinusoidal wave generated by NSD RO is 60% of its power supply as shown in Fig. 14b while in case of simple RO it is 150% of the power supply.
Further the jitter has also reduced as compared with simple RO. Here it can be seen that because of larger overshoot in case of TFET the amplitude of the sinusoidal wave generated is much more than the conventional MOSFET device RO [35]. Further, as the number of stages are increased in the RO, the operation speed will get reduced because the inverters used are of same size. The comparison can be understood from Table 3 and 5. At V dd =1.8V and with n=3, RO is operating with f RO =0.848 GHz while for n=5 the RO's operating frequency is f RO =0.388 GHz.
The RO overshoot, peak to peak voltage, and frequency also depend on the technology used in inverter device. For CMOS based RO the full swing 0 to V dd is obtained in oscillations and the frequency is higher than TFET. There are distortions in the outputs of RO which can be reduced either by increasing the number of stages or using DTMOS like techniques for TFETs also.

RF and Mobile Applications
The range of Radio Frequencies (RF) is from 300 KHz to 300 GHz. It can be seen from Tables 3 and 4, a wide range of frequencies can be tuned with the help of power supply by end user by taking the advantage of late saturation of TFET devices. This tuning can be done by the end user but if it is desired to design an integrated RO for a particular application e.g. frequency of operation 900 MHz for mobile communication. In such case the frequency tuning with T ext can also play a vital role for RO, as for double gate devices the drain extension resistance is going to become a big problem.
Comparative study of Tables 3 and 4 or Fig. 12 shows that increasing V dd or T ext although increases the frequency of operation but it also increases the signal swing (V P eak -V min ) and simple RO waveform is much distorted as compared to NSD RO topology. Therefore, its better to use NSD RO as it give 60% of V dd waveform swing, Fig. 14, which in turn is responsible for lesser power dissipation, and

Conclusions
Tunnel FET based ring oscillator (RO) study is presented with drain extension region width and power supply variations (works like Voltage Controlled Oscillator-VCO) of Si-DG TFET. The effects of drain extension region resistance on the Tunnel FET inverter (hence on RO) has been explained with its impact on device characteristics and applied to RO. As the drain extension region width is increased the propagation delay of RO decreases that in turn makes the device faster while the peak overshoot and undershoot increases. Thus, a trade off must be maintained in order to get best results in terms of frequency, and switching power dissipation (C * V 2 * f ). Ring oscillators frequency can be tuned by the end user by tuning the power supply as well. RO faces the problem of jitter introduced in subsequent stages, to remove this jitter and make the oscillator more reliable a previously reported negative skewed delay ring oscillator (NSD RO) is designed, and simulated for comparative study with single ended simple RO. It is found on the basis of observations that the NSD RO have lesser jitter, faster speed for its single ended RO topology counterpart. It is also found that the larger the extension drain/source width, frequency will be more for the device. The comparison also includes the variations in drain extension region and its impact on the inverter, and therefore, on RO characteristics. The possible application in RF frequency range tuning with adjusting power supply by the end user, and drain extension width at the manufacturer is also discussed.