Two-dimensional (2D) semiconductors have shown great potentials for ultra-short channel field-effect transistors (FETs) in next-generation electronics. However, because of intractable surface states and interface barriers, it is challenging to realize high-quality contacts with low contact resistances for both p- and n- 2D FETs. Here, we demonstrate a graphene-enhanced van der Waals (vdWs) integration approach, which is a multi-scale (nanometer to centimeter scale) and reliable (~ 100% yield) metal transfer strategy applicable to various metals and 2D semiconductors. Scanning transmission electron microscopy imaging shows that 2D/2D/3D semiconductor/graphene/metal interfaces are atomically flat, ultraclean and defect-free. First principles calculations indicate that the sandwiched graphene monolayer can eliminate gap states induced by 3D metals in 2D semiconductors. Through this approach, we realized Schottky barrier-free contacts on both p- and n-type 2D FETs, achieving p-type MoTe2, p-type black phosphorus and n-type MoS2 FETs with on-state current densities of 404, 1520 and 761 µA µm-1, respectively, which are among the highest values reported in literatures.
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Graphene-enhanced van der Waals contacts between three-dimensional metals and two-dimensional semiconductors
https://doi.org/10.21203/rs.3.rs-1854850/v1
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Two-dimensional semiconductors have great potentials for electronic devices with ultra-short channels owing to their atomic thickness 1-4. As field-effect transistors are scaling down, contact resistances between three-dimensional (3D) metals and 2D semiconductors are becoming more influential in determining the device performance4,5. According to the Schottky-Mott model, reducing the Schottky barrier at the 3D metal/2D semiconductor contacts with metals of different work functions should have been an effective approach 6-9. However, the Fermi level at the interface is usually pinned around certain energy state in the band gap of the 2D semiconductor, which hardly changes with respect to the work function of the contact metal 10-12. The Fermi level pinning (FLP) effect can be ascribed to three major factors 6-8: (i) Metal-induced gap states (MIGS) in the band gap. When the semiconductor approaches the metal surface, wavefunction of the metal penetrates into the semiconductor and induces rehybridizations of wavefunction of the semiconductor, resulting in gap states in the band gap of the semiconductor. (ii) Impurities, defects and chemical bonds at the interface. These species induce surface reconstructions and change original energy levels of the semiconductor, causing surface states in the band gap. (iii) Local strains and lattice distortions. Metal grains in nanoscale at the interface render local strains and lattice distortions in the semiconductor, introducing energy states within the band gap. A combination of aforementioned surface states eventually leads to an irreducible Schottky barrier at the contact, hampering the ultimate performance of 2D electronics. So far, several strategies have been reported to improve the contacts, including phase engineering 13-15, doping 16-18, usage of low work function metals 19,20 and graphene contacts 3,21,22, but these strategies hardly achieved Schottky-barrier-free contact for the FLP effect.
To overcome the FLP between 2D semiconductor and 3D metal, a novel low-energy van der Waals integration of 2D semiconductors/3D metals via physical transfer 8,23 was reported to form atomically flat interface and reduce the surface states from defect, residues, strains on the 2D semiconductors created by the high-energy metal deposition and lithography processes, and the Schottky barrier height nearly followed the Schottky-mott rule 8,24. However, to increase physical transfer yield of pre-deposited metal electrodes for short channel devices, it is highly desirable to decrease the interaction between the pre-deposited metals and donor substrates, and increase the vdWs interaction between the transferred metals and 2D semiconductors. In addition, to realize Schottky barrier-free contact and high current delivery capability, the MIGS induced by 3D transferred metal electrodes should be eliminated as well. Moreover, most of 2D semiconductors are n-type or ambipolar, and most of surface states of intrinsic defects or extrinsic doping from environment and fabrication process can trap holes, thus it is more difficult to achieve low contact resistance and high current density for p-type devices than for n-type devices.
In this work, we demonstrated an approach of graphene-enhanced vdWs integration (GEVI), which was realized by the physical transfer of 2D monolayer graphene/3D metal hetero-junctions onto 2D semiconductors. The graphene monolayers were transferred on donor substrates, and then metals were thermally deposited on the graphene monolayers, where the interaction between the graphene monolayers and the metals was stronger than that between the graphene monolayers and the substrates. We found that the yields of physical transfer and release of the monolayer graphene/metal heterojunctions were ~100%, morphologies were kept precisely well, and the resolution can be down to ~ 8 nm. Thus, atomically flat and ultra-clean vdWs contacts can be generated by the reliable and high-resolution GEVI approach. More importantly, the sandwiched graphene monolayers increased the distances between 2D semiconductors and 3D metals so that the MIGS induced by metal electrodes can be eliminated, and the calculated tunneling resistance of the 2D semiconductor/2D monolayer graphene/3D metal vdWs contact was in the same order to that of the state-of-the-art MoS2/Bi contact 25. Compared with 2D semiconductor/3D metal vdWs contacts, the devices with graphene-enhanced vdWs contacts presented higher on-state current density. Through the GEVI approach, the Schottky-barrier-free contacts were achieved on both p- and n-type 2D semiconductors with metals of proper work functions. The hole on-state current density of MoTe2 and black phosphorus can reach up to ~404 μA μm-1, ~1520 μA μm-1, respectively, and the electron on-state current density of MoS2 can reach up to ~761 μA μm-1, which are among the highest values reported in literatures.
Graphene-enhanced vdWs integration approach
Fig. 1a presents the fabrication process of GEVI approach (see details in the experimental section). In brief, a large-area CVD-grown graphene monolayer was first transferred onto a silicon substrate with atomically flat surface, and metal electrodes were subsequently deposited on the graphene monolayer by lithography and electron beam physical vapor evaporation. The substrate was later subjected to oxygen or argon plasma to etch the graphene monolayer without metal protection, leaving Gr/metal electrodes. Gr/metal electrodes coated with a resilient polymethyl methacrylate (PMMA) thin film could then be readily peeled off by a stiffer adhesive thermal release tape. On a transfer station equipped with an optical microscope, the detached Gr/metal electrodes were precisely aligned and laminated on 2D semiconductors. Finally, the PMMA layer can be removed by using hot acetone vapor if necessary.
Compared with other vdWs integration approaches8,23, where metal electrodes were directly deposited on donor substrates via high-energy routes, the CVD graphene monolayers were physically transferred to our donor substrates in the manner of low-energy assembly, leading to a weaker interaction between our Gr/metal electrodes and the donor substrates. As presented in Fig. 1b-c, a typical large-scale ~ 2×2 cm2 Gr/metal electrode array was ~100% transferred and released to the target substrates along with intact outlines of pristine morphologies. Even for metals with strong adhesion to substrates (e.g. Cr, Ti and Pd), the transfer yields for the Gr/metal electrodes can be ~100%. By contrast the transfer yields were <3% in the absence of graphene layer because of strong adhesions between metals and substrates (Extended data Fig. 1b). The high-efficiency transfers of strongly adhesive metals with low (e.g. Ti), medium (e.g. Cr) or high (e.g. Pd) work functions allowed versatile contact engineering possibilities in 2D electronics (Fig. 1d). In addition, the GEVI approach was applicable to both rigid substrates (e.g. SiO2/Si, glass) and flexible substrates (e.g. PDMS) (Extended data Fig. 3), and also allowed us to transfer metal patterns with nanoscale features. Fig. 1e displays a series of transferred metal patterns (letters, triangles, pentagrams and interdigital electrodes) via GEVI, and all the patterns maintained the designed shapes. As shown in Fig. 1e, the inter-digital electrodes with 100 nm interval and nano-dots with ~8 nm nano-gap were well transferred, suggesting that the GEVI is a large-scale, reliable, and high-resolution approach for short channel nanoelectronics and optoelectronics.
Importantly, the bottom side of the peeled Gr/metal electrodes presented clean surface and replicated the atomic flatness of the silicon substrate (Fig. 1f). The cross-sectional transmission electron microscopy (TEM) image of the transferred graphene-enhanced MoTe2/Gr/Pd vdWs junction further confirmed an atomically flat, clean and intimate interface between the Gr/Pd electrode and MoTe2, and there were no defects, lattice damages and metal diffusion on the 2D semiconductor (Fig. 1g). Upon mechanically peeling-off of the transferred Gr/Metal electrode from the CVD-grown MoSe2 monolayer on SiO2/Si substrate (Fig. 1h), the underlying MoSe2 was conformally removed with the Gr/metal electrode from the substrate, indicating the intimate interface and strong vdWs coupling between the Gr/metal electrode and the 2D semiconductor. Thus, the atomically flat, clean, intimate and strong vdWs coupling contact can be generated by the GEVI approach, which can greatly reduce the surface states from the defects, strains and lattice distortions on the 2D semiconductor.
Elimination of the MIGS in the 2D semiconductor
To study the isolation effect of the graphene monolayer, first-principles calculations using density functional theory (DFT) were conducted on MoTe2/Pd and MoTe2/Gr/Pd hetero-junctions (Fig. 2). In MoTe2/Pd (Fig. 2a), projected density of states (PDOS) of Mo and Te showed similar shapes with the PDOS of Pd, indicating that the strong MIGS were introduced and thus the Fermi level was pinned in the band gap of MoTe2. The MIGS effect can be suppressed by increasing the gap distance between the metal and 2D semiconductor (Extended data Fig. 4a-i). However, the tunnelling resistance increased by more than three orders of magnitude when gap distance increased from 3 Å to 7 Å (Extended data Fig. 4j). In the case of MoTe2/Gr/Pd (Fig. 2b), the distance between Te and Pd atoms was ~6.74 Å, and metal-induced energy states presented merely in the PDOS of graphene. There were no MIGS in the band gap of MoTe2, indicating that the MIGS can be eliminated by isolating MoTe2 and Pd with a monolayer graphene. To image the clean interface between the Gr/metal electrode and MoTe2, we conducted annular dark field scanning transmission electron microscopy (ADF-STEM). As shown in Fig. 2g, the surface of MoTe2 was atomically sharp and defect-free, and the distance between MoTe2 and Pd was ~10 Å, which was sufficient to eliminate the MIGS in the 2D semiconductor. Furthermore, the calculated tunneling resistance in the MoTe2/Gr/Pd hetero-junction was ~4.3×10-9 Ω cm2 (Fig. 2h), which was in the same order of magnitude to that of the state-of-the-art MoS2/Bi contact (~1.81×10-9 Ωcm2) 25. Thus, after sandwiching the graphene monolayer, the increased distance between the metal electrode and the 2D semiconductor ideally has a minor effect on the vdWs contact resistance. It is worth noticing that one layer of graphene is enough for eliminating MIGS from the DFT calculations, and additional layers of graphene might introduce extra tunneling resistance and thereby cause poor charge transport (Extended data Fig. 5).
As shown in Fig. 2b-c, the Fermi level of MoTe2/Gr heterojunction was close to the conduction band of MoTe2, and it moved down to the valence band after forming the MoTe2/Gr/Pd vdWs contact, indicating that the hole Schottky barrier height can be tuned with the metal of high work function. Because of the strong n-doping effect of graphene for the MoTe2 monolayer, it would be very hard to realize Schottky barrier-free contact for the monolayer MoTe2/Gr/Pd. To decrease the doping contribution of graphene, further DFT calculation was performed on bilayer (2L)-MoTe2/Gr/Pd. As shown in Fig. 2d-e, the Fermi level of 2L-MoTe2/Gr was close to the valence band of MoTe2, and it moved down to the edge of valence band once Pd electrode was contacted. Impressively, the Fermi level can be also tuned to the edge of conduction band contacted with low function metal Ag for the 2L-MoTe2/Gr heterojunction (Fig. 2f). Therefore, both electron and hole Schottky barrier-free contacts could be generated with the graphene-enhanced vdWs contact.
Schottky barrier-free contacts in p-type 2D semiconductors
The realization of the Schottky barrier-free contact at 2L-MoTe2/Gr/Pd interface can be demonstrated from four pieces of evidence: high mobility, low contact resistance, negative correlation between mobility and temperature, and negative Schottky barrier height at flatband. The transfer curve (Isd-Vg) of bilayer MoTe2 FETs with two-terminal transferred Gr/Pd electrodes presented typical p-dominated transport behavior with an on/off ratio approaching 106 (Fig. 3a). The highest hole mobility of the device reached up to ~206 cm2 V-1 s-1 (Extended data Fig. 6a). Output curve (Isd-Vsd) showed good linearity (Fig. 3b), suggesting a good contact with a negligible Schottky barrier for hole transport. Contact resistance (Rc) was extracted to be ~1.35 kΩ μm at Vg = -60 V by transfer-length method (Fig. 3c). Temperature-dependent mobility plot showed that negative correlation can be fitted by μ∝T-0.77 in the range of 240-300 K, which matched well with the change of mobility with temperature arising from acoustic phonon scattering 50, indicating the electrical characteristic was not dominated by the contact resistance (Fig. 3d). In Arrhenius plots (In(Isd/T1.5) vs 1000/T) of MoTe2 FETs, the Schottky barrier was negative for hole transport (Vg= -40 V) and positive for electron transport (Vg= 50 V) (Fig. 3e). A negative value was obtained by extracting the Schottky barrier height at flatband (Fig. 3f), which was consistent with energy band levels of MoTe2/Gr/Pd in the inset of Fig. 3f.
Furthermore, we demonstrated the high current delivery capability of the graphene-enhanced vdWs contact. Fig. 3g showed output characteristics (Isd-Vsd) of bilayer MoTe2 FETs with 100-nm channel length on 45-nm-thick Al2O3 coated on silicon substrate which was assembled by transferring Gr/Pd electrodes. The linearity of the curves at low voltage showed the ohmic contact, and the on-state current density was ~404 μA μm-1. Fig. 3h-i compared GEVI with state-of-the-art contact engineering strategies for MoTe2-based FETs. Our strategy achieved the highest on-state current density and mobility on p-type MoTe2 FETs 15,27-40.
To further verify the effect of graphene-enhanced vdWs contact, we performed control experiments on MoTe2 FETs with different contacts. MoTe2 FETs with evaporated-Pd, transferred-Pd, and transferred-Gr/Pd electrodes were prepared by high-energy E-beam evapoation, low-energy metal transfer and graphene-enhanced metal transfers, and more than 6 devcies were prepared for each case (Extended data Fig. 7a). In the comparison, the MoTe2 FETs with evaporated-Pd electrodes presented lowest hole mobilities (< 20 cm2V-1s-1) and lowest current densities at Vg = -50 V(< 2 μA/μm), the devices with transferred-Pd presented higher mobility (20-70 cm2V-1s-1) and higher current densities at Vg = -50 V (2-10 μA/μm), and the devices with transferred-Gr/Pd electrodes presented the highest mobilities (90-160 cm2V-1s-1) and highest current densities at Vg = -50 V (5-20 μA/μm), indicating the GEVI is an better statergy for achieving high-performance 2D electronic devices.
Apart from p-type MoTe2, the approach can also achieve high performance p-type black phosphorus (BP) FETs. Back-gated BP FETs with ~700 nm channel length were fabricated by transferring Gr/Pd electrodes onto 8-nm-thick BP flake on silicon substrate with 300-nm-thick oxide layer, showing typical p-dominated transport behavior and linear output characteristic, and the highest hole mobility of BP FETs on SiO2/Si substrate was ~308 cm2 V-1 s-1 (Extended data Fig. 8a-b). To improve gate capacitance and reduce the substrate doping effect from SiO2 layer, BP FETs were fabricated on 45-nm-thick Al2O3/Si substrate. The highest current density of BP FETs with 700 nm channel length reached ~780 μA μm-1 at Vsd = 5 V (Fig. 3j), and the highest current density was up to ~1520 μA μm-1 when the channel length decreased to ~300 nm (Extended data Fig. 8c). The contact resistance (Rc) was extracted to be ~330 Ω μm at nh ≈ 7.9×1012 cm-2 (Fig. 3k), suggesting the high current delivery capability of the graphene-enhanced vdWs contact. To the best of our knowledge, the current density is a record-high value for BP FETs at room temperature (Fig. 3l) 41-49.
Schottky barrier-free contact in n-type 2D semiconductors
Apart from p-type 2D semiconductors, the GEVI approach can also realize Schottky barrier-free contact for n-type 2D semiconductors. Due to the atomic thickness of graphene, the Fermi level position of Gr/Metal electrode was dominated by the work function of the metal. The ultraviolet photoelectron spectroscopy (UPS) revealed that metal films with or without monolayer graphene exhibited similar work functions (~4.44 vs. ~4.46 eV) (Extended data Fig. 9). In previous theoretical study, the Fermi level of graphene widely shifted when contacting with different metals, and the shifting range reached up to 1.1eV 63. This property enabled us to achieve work function engineering on both p-type and n-type 2D-based FETs by transferring different Gr/metals electrodes. To demonstrate that, back-gated bilayer MoS2 FETs on SiO2/Si substrate were also fabricated with Ag electrode with a low work function of ~4.3 eV via GEVI. The transfer curve (Isd-Vg) of bilayer MoS2 FETs with two-terminal transferred Gr/Ag electrodes presented typical n-type transport behavior with an on/off ratio of ~108 (Fig. 4a), and the highest hole mobility of the device reached up to ~193 cm2 V-1 s-1 (Extended data Fig. 6c). The good linearity in the output curve (Isd-Vsd) suggested a low contact resistance with a negligible Schottky barrier for electron transport (Fig. 4b). The contact resistance (Rc) was extracted to be ~1.6 kΩ μm at ne ≈ 6.1×1012 cm-2 by the transfer-length method (Fig. 4c). The temperature-dependent mobility plot shows the negative correlation (Fig. 4d) which can be fitted by μ∝T-1, indicating the electrical characteristic was not dominated by the contact resistance. In Arrhenius plots (In(Isd/T1.5) vs 1000/T) of MoS2 FETs, the Schottky barrier was negative for electron transport when Vg > -30 V (Fig. 4e). A negative value was obtained by extracting Schottky barrier height at flatband (Fig. 4f), which was consistent with the projected energy band levels of MoS2/Gr/Pd in the inset of Fig. 4f. Therefore, the GEVI approach can also achieve the electron Schottky barrier-free transport for n-type 2D FETs. MoS2 FETs with 100 nm channel length were fabricated on 45-nm-thick Al2O3 gate dielectrics by transferring Gr/Ag electrodes, and the on-state current density reached up ~761 μA μm-1 (Fig. 4g). For the sake of comparison, state-of-the-art contact engineering strategies for MoS2-based FETs were summarized in Fig. 4h-i, showing that our performance is among the highest value reported in the literature 3,8,11-13,18-22,25,51-62.
Effective modulation of charge carriers with metal work functions
Apart from realizing ohmic contact for p- and n- type FETs, GEVI can be a general approach for modulating charger carrier of 2D devices. By transferring metals of different work functions via GEVI (WTi ≈ 4.3 eV, WCr ≈ 4.6 eV and WPd ≈ 5.1 eV), the majority carrier type can be systematically modulated, and the n-type, ambipolar and p-type behaviors were realized on MoTe2, MoSe2 and WSe2 FETs. (Extended data Fig. 10 and 11). When the contact metal work function increased from ~4.3 to ~5.1 eV, the hole carrier density of MoTe2 increased by ~ 4 orders of magnitude at Vg = -50 V, and the transport behavior was modulated from n- to p- type. Correspondingly, the electron carrier density of WSe2 decreased by ~4 orders of magnitude at Vg = 50 V after the contact metal work function increased from ~4.3 to ~5.1 eV, and the transport behavior transformed from ambipolar to p- type. The effective modulation of charge carrier with the metal work function confirmed that the FLP effect at the interface of the graphene-enhanced vdWs contact was very weak.
The effective modulation of charge carriers with metal work functions enabled us to develop complementary logic devices via the GEVI. As a proof-of-concept demonstration, a MoTe2-based complementary inverter was fabricated with Gr/Pd and Gr/Ti contacts, and the gain value reached up to ~9 and the static power consumption can be several nano-watt at VDD = 0.5 V (Extended data Fig. 12), showing the GEVI was very promising to develop 2D-based complementary logic devices.
In summary, a strategy of GEVI to realize atomically flat and ultra-clean 2D/2D/3D vdWs contacts on a variety of 2D semiconductors for high-performance electronics have been successfully designed and demonstrated. The monolayer graphene played an important role in four aspects: (i) Decoupling metals with the donor substrates for large-scale, high-resolution, and reliable transfer, (ii) Strong coupling with 2D semiconductors for atomically flat and intimate contact, (iii) Isolating 2D semiconductors from metal electrodes to eliminate the MIGS, (iv) Improving charge transport for high performance. As a low-energy integration strategy, the GEVI could display potentials in developing devices based on other types of film materials (e.g. carbon nanotube, perovskites, organic semiconductors) and other substrates which are incompatible with lithography or metal evaporation process.
- Fabrication and transfer of Gr/Metal electrodes.
CVD-grown monolayer graphene (Shanghai ONWAY technology) was firstly transferred onto a silicon wafer via conventional bubbling transfer method 64. Metal electrodes were patterned by using standard photolithography (SUSS MA/BA6) or electron-beam lithography (Raith, EBPG-5150). 30-nm-thick desired metal and a protective capping layer of 30-nm-thick were deposited by using electron beam evaporation. The Si wafer was then treated by oxygen or argon plasma to etch the uncovered graphene regions. Next, the wafer was placed in a customized chamber for surface modification of hexamethyldisilazane (HMDS) vapor. Briefly, 750 μL HMDS was added into the chamber by using a micropipette, and the chamber was vacuumized, sealed and placed in an oven for 30 min at 120 oC. After HMDS modification, PMMA (380K, 10 wt.% in anisole) was immediately spin-coated on the wafer with a speed of 2000 rpm. With HMDS modification, PMMA-coated Gr/Metal electrodes can be completely peeled off by a TRT and readily released onto the target substrate when the PMMA-carrying side of TRT was brought to tight contact with the target substrate and the substrate was heated to 125 oC.
2. Fabrication of 2D FETs and inverter by GEVI.
For fabrication of back-gated 2D FETs, 2D channel semiconductors were mechanically exfoliated on 300nm-SiO2/Si or Al2O3/Si substrate in the first place. Gr/metal electrodes were then transferred onto 2D materials channels via GEVI procedures with the help of a transfer station equipped with a microscope for precise patterns alignments. To minimize the possible surface oxidation, the peeling and transfer process were conducted in a glovebox with argon atmosphere. To improve the interaction between Gr/metal electrodes and the target substrate, the substrate was heated at 180 oC for 15 min after the transfer. Finally, PMMA layer was removed in 90oC acetone steam, and the substrate was heated at 200 oC in argon for 15 min for thermal annealing of the device.
45-nm-thick Al2O3 dielectric layer coated silicon substrate was prepared via atomic layer deposition (ALD). Commercial highly p-doped silicon substrate was cleaned by oxygen plasma, and ALD was conducted at 200 oC at a rate of 1.7 Å/s by using trimethylaluminum and water as precursors.
In terms of MoTe2 inverters, a 30-nm-thick Al2O3 dielectric layer was firstly deposited on silicon wafer via ALD. Next, a 3-nm-thick MoTe2 flake was exfoliated onto the Al2O3/Si substrate. Gr/Ti and Gr/Pd contact electrodes were transferred onto MoTe2 flake to achieve n-type and p-type channel of the inverter.
3. Characterization and electrical measurement.
Exfoliated 2D flakes (MoS2, MoSe2, MoTe2 and WSe2) were selected according to their contrasts under optical microscope (Nicon, LM-150). Thicknesses of flakes were determined by atomic force microscope (Bruker Dimension Icon). Raman spectra of graphene were collected on Raman spectroscope (WITEC-α-300R). Electrical properties of devices were characterized in a probe station (Lakeshore, TTPX) in vacuum, using Keithley 4200 source measurement unit. Cross-section sample was prepared by using focused ion beam (FIB) system (FEI, Scios). To protect the surface, a layer of 10 nm Pt and another layer of 1 μm Pt were successively deposited on the sample before FIB cutting. TEM was performed on JEOL JEM-3200FS, and STEM was performed on Titan Cubed Themis G2 300.
4. DFT calculations.
All calculations are based on density functional theory (DFT), using the Vienna ab initio Simulation Package (VASP) code 65. The electron ion interaction was described with the projector augmented wave method 66. The electron exchange and correlation energy were treated within the generalized gradient approximation in the Perdew–Burke–Ernzerhof formalism. The valence electrons are expanded in a plane-wave basis set with an energy cutoff of 460 eV. The Pd/MoTe2, Pd/Graphene/MoTe2 and Ag/Graphene/MoTe2 heterojunctions were modeled by slab model with a vacuum thickness of 16 Å. The Pd(111) surface and Ag(111) surface were modeled by ( × ) supercells with 6 atom layers. The MoTe2 (001) surface was modeled by (2×2) supercell and the graphene was modeled by (3×3) supercell. The lattice mismatches of all heterojunctions were smaller than 5%. The vdW interaction corrections were included to describe the interactions of all heterojunctions. All atoms of heterojunctions were relaxed during structural optimization. For the sampling of Brillouin-zone integrals, Gamma centered k-points grid of 5×5×1 was used. The convergence criterions of force and energy were set as 0.01 eV Å-1 and 10-4 eV, respectively.
5. Extraction of Schottky barriers
The drain current can be described as
where A* is the Richardson constant for 2D system, ΦSB is the Schottky barrier at the contact, kB is Boltzmann constant, T is the temperature. In the condition of Vsd >> kBT, the equation (1) can be simplified as
which can be further transformed into
By linear fitting the plot of ln(Isd/T1.5) versus 1/T, ΦSB can be extracted from the slope.
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Acknowledgements
W. Z. acknowledges the Shenzhen Peacock Plan (Grant No. KQTD2016053112042971), the Science, Technology and Innovation Commission of Shenzhen Municipality (Grant No. JCYJ20200109105422876), the Educational Commission of Guangdong Province project (Grant No. 2015KGJHZ006) and the Educational Commission of Guangdong Province project (Key program, Grant No. 2020ZDZX3041). D. Q. acknowledges the National Natural Science Foundation of China (62104152), and GuangDong Basic and Applied Basic Research Foundation (2020A1515111172). The authors also acknowledge the Photonics Center of Shenzhen University.
Author contributions
D. Q. and P. L. contributed equally to the work. D. Q. and W. Z. proposed the project and designed the experiments. D. Q. and P. L. developed the technology together. D. Q., P. L., H. O., D. W., W. L., performed the device fabrication, electrical measurements and characterizations. F. O., Z. W. and Y. C. helped to analyze the data. D. Q., P. L. and W. Z. wrote the manuscript and all authors revised the work.
Competing interests
The authors declare no conflict of interest.
Additional information
Supplementary information is available online.
There is NO Competing Interest.