A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications

The purpose of this paper is to develop the design and analytical modelling of a noise immune double suspended gate MOSFET (DSG-MOSFET) for ultra-low power applications. Also, important performance parameters of the proposed structure such as pull-in and pull-out voltages have been thoroughly investigated with respect to the valuable structural parameters. The design methodology used is EKV based analytical approach to calculate the pull-in and pull-out voltages with ingeniously developed boundary conditions which helps achieving reasonably accurate result. Also, the I-V characteristics has been modelled to justify accuracy. The experimental result shows that the pull-in and pull-out voltages are in millivolts and microvolts range and hence it can be used in ultra-low power applications. As the ratio between the pull-out and the pull-in voltage is 10^(+3) range, justifies that the proposed structure is noise immune. The ID-VGS characteristic has hysteresis and this sharp transition in pull-in and pull-out voltage indicates that it can be used as an ideal switch with infinite sub-threshold slope. This paper presents a compact EKV based analytical modelling of pull-in and pull-out voltages for a DSG-MOFET which predict the device characteristics reasonably similar to simulated results. Also, for the first time the noise immunity for a DSGMOSFET has been analyzed.


Introduction
One of the main disadvantages of CMOS architecture is the scalability of the device. Up to some range the dimension of MOSFET can be reduced and with that the other parameters such as supply voltage, threshold voltage etc. without any adverse effect on the performance of the device. However, it can be seen that when the threshold voltage (V th ) is scaled below or equal to 150 mV, it results in huge off current [1] due to the subthreshold slope (SS) constraint in case of this architecture. However, this limitation can be overcome by suspended gate field effect transistor (SGFET). SGFETs are overpowering the CMOS architecture in terms of standby power consumption which is very low in the previous one [2]. Hence, the switching characteristics for SGFETs are almost ideal, therefore these can be used as sleeping transistors which leads to efficient power management. The power management characteristics of SGFETs, make the device an advantageous one over CMOS architecture for low power applications.
More than 52 years ago, the idea of combining a mechanical switch, which is electrostatically actuated, with a MOSFET was introduced [3]. The motivation behind this innovative idea was to get a more stable structure which can operate more properly at high frequency [2]. This MEMS/FET hybrid structures had been implemented as gas as well pressure sensors with some eye-catching results [4,5].
Gate to channel modelling [6] of SGFETS based on EKV (Enz-Krummenacher-Vittoz) [14] has been reported previously. This model is also valid for all operational regimes. However, some shortcoming of this model, such as huge time consumption as it is an iterative method, was also reported in [2]. Hence, to overcome this limitation, a static model for SGFET has been developed by considering only the operational region of interest [2]. However, this mathematical model was for a single suspended gate FET. For first time, the mathematical model for a double suspended gate MOSFET has been reported in this acritical. This model gives the inside knowledge of DSGMOSFETs performance as well as the basic design rules. This article also reports the mathematical modelling for the compared structure which is depicted in Fig. 1(e).
The article is organized as follows: the operation of DSGMOSFET and the respected mathematical modelling for both a) proposed as well as b) compared structures is given in section II. Section III includes fabrication steps flowed by Section IV which includes simulation setup. Section V the performance comparison between the proposed as well the compared structure. In, Section VI, the proposed structure is analysed in depth and section VII includes the conclusion.

Working Principle and Analytical Modelling
The 3-D as well as cross section version of the proposed DSGMOSFET is showed in Fig. 1(a) and Fig. 1(b). Figure 1(c) depicts the equivalent capacitor circuit of DSGMOSFET and Fig. 1(d) shows the symbol representation of n-channel DSGMOSFET. The compared structure, without the lower gate oxide, has been given in Fig. 1(e).
DSGMOSFET is a hybrid combination of an inversion MOSFET and electrostatically actuated mechanical NEMS switch (Fig. 1). The main difference of DSGMOSFET from a MOSFET is that there is the presence of air between the gate oxides and the double gates which has been supported by anchors as show in Fig. 1(a). In case of fabrication of any SGFET structure, can be done by using sacrificial etching of the respected material which can be place on the gate oxide before the completion of gate [7,12,15]. However, by this technique the archived air gap is in the range of few hundred nanometers [5,7,12] which in turn will make the structure huge in size and also makes the device potentially unavailable to be used in ultra-low power applications. But, by using atomic layer deposition, an air gap of 10 nm has been achieved   [16] and it has been used in biosensing applications as well [17]. However, the main constraint is the width of the suspended gate [17]. If the width is too large then it will affect the bending of the gate hence the pull in and pull-out voltages will increase, hence power dissipation will also increase. Due to increments in both pull-in and pull-out voltages, the noise immunity will be affected the most. By considering all the above reasons, beam widths of 1 nm for both the gates has been considered for the proposed structure with a t gap of 10 nm and t ox of 2 nm. For the compared structure, all the parameters are same except the fact that there is no lower gate oxide present in the compared structure. AlSi [12] or polysilicon [15] can be used as gate materials, AlSi has been chosen for the both proposed and compared structure. For our suggested DSG-MOSFET of Fig. 2, we first calibrated the models utilised for simulation using COMSOL. The DSG-MOSFET COMSOL simulation result was compared to the observed data given in [2]. Figure 3 shows a reasonable agreement between the two outcomes, indicating that the chosen models are genuine.
The working principle of the proposed DSGMOSFET can be explained in the following way: both the gates are shorted and a gate voltage of V G has been applied. When gate voltage (V G ) is equal to the flatband voltage (V FB ), then the air gaps for both the case is t gap = x ( Fig. 1(b)) as there is no charge accumulation in both the electrode and in the semiconductor, 'x' represents the initial distance between gate insulator and the moving gate. As V G start to increase, positive charges start to accumulate in both the moving gates and also equivalent negative charges accumulate in the silicon substrate which results in x < t gap . Now below the pull in voltage, there will be no bending in both the moving gates as the electrostatic force is balanced by the elastic forces which are acting on the both gates Fig. 1(a). Therefore, when V G exceeds or become equal to pull in voltage Vpi, then the electrostatic forces in both the gates over powered the elastic forces, hence both the gates collapsed (pulled in) on both gate oxides ( Fig. 2 (b)) due to which the threshold voltage abruptly reduced which leads to a sudden drain current increase [6].
For compared structure ( Fig. 1(e)), the working principle will remain almost same but the absent of the lower gate oxide will play an essential role in the device operation. It can be observed from Fig. 1(b) and Fig. 1(e) that the compared structure has two different distances from two gates i.e. ×1 and ×2. It also has two different air gap values i.e. tgap1 and tgap. Hence, two different pull in and pull-out voltages will be obtained for the compared structure and discussed in analytical modelling section. Another important difference between these two structures that the first one ( Fig. 1(b)) (the proposed structure) will be working perfectly as MOSFETs for both the gates, however in case of compared structure ( Fig. 1(e)), the lower gate oxide is absent and hence, for the upper gate the device will work as a MOSFET but for lower gate it  will work as a metal-metal switch. Both structures have significant improvements over [2], but the proposed one is more advantageous in terms of power dissipation and noise immunity which is discussed in later.

Pull-in Modelling
The electrostatic force, applied between the channel and the gate, that governs the beam displacement is given by the force stiffness relationship. The total energy between two conductive plates is considered for the electro-mechanical analysis and given by At equilibrium these two forces balance each other and hence, Where, W = beam width, L = channel length, t gap0 = initial height of the beam from the oxide, ε gap =permittivity of air, Vgap = voltage drop across the air gap, x = actual height of the beam from the oxide. k is the spring constant and given as- E is the Young modulus of the moving gate material. Now V gap can be demonstrated as a function of x and the semiconductor charge density Q sc as Putting the value of eq. (3) into eq. (2) we get, The restoring force linearly depends on displacement and the electrostatic force is inverse quadratic function, hence the stable point can be achieved only when, Due to the series connection between C f and C gap , x pi is reduced to Where Cgap0= ε gap /t gap0 is the minimum gap capacitance. In this case C f is the series equivalent of C ox with C sc . By considering depletion approximation, the depletion charge can be expressed as a function of the surface potential as Where, ε si =permittivity of silicon, q = elementary charge, N A = substrate doping concentration, ψ s = surface potential.
Putting eq. (8) into eq. (5) the gate position is expressed as a function of surface potential as The well-known formulation of V pi for a suspended gate MOS capacitor is In second case of our proposed structure the lower oxide is removed, in this case the pull-in voltage will become as the metal-metal NEMS switch as

Pull-out Modelling
In this section the pull-out voltage has been discussed, starting from the force acting on the gate while the gate is pulled in. The opposing electrostatic force, restoring elastic force and adhesion force has been considered. The gate capacitance increases abruptly immediately after the gate is pulled in, and so do the charge density and the surface potential. For V G > V pi the DSGFET will behave as a conventional DGMOSFET. When V G swept back from higher value of pull in voltage, the pull-out does not occurs at V G = V pi because the higher charge density causes higher electrostatic force than those at the onset of pull in. The adhesion force between beam electrode and the oxide surface is another cause of this. As a result, the pull-out voltage V po becomes less than V pi which gives a hysteresis in SGFET characteristics.
The force balance equation just before the pull out can be approximated as The first term of the left-hand side of the above equation represent the electrostatic force whereas the right-hand side is the elastic force. F a is the surface adhesion force. F a can be approximated as From eq.(12) the pull-out voltage can be calculated as For the second structure the pull out voltage becomes

Surface Potential
The surface potential analysis of the double suspended gate MOSFET can be divided mainly in two parts: 1. Before the gates collapse 2. After the gates collapsed From the Fig. 1(c) [as shown in our figure] the gate voltage can be written as As the structure is symmetrical and the gates are tied together, the above expression is hold for both the gates. This is the generalized equation for the gate voltage.
For V G = V pi and ψ s = ψ pi , x pi can be deduced from eq. (7) as ð17Þ by expressing C f as a series combination of the oxide capacitance Cox and the semiconductor capacitanceCsc (in depletion, Csc = ε di /x di , where x di is the depletion depth at ψ s = ψ pi ) Where, By putting the value of x pi in the equation of V G we get the generalized expression for V pi as And from the first equation putting x = x pi , V G = V pi and Q sc = Q d we can obtain the solution for surface potential before the gates snap down as When the gate is pulled-in and V G ≥ V po the surface potential will become similar to the conventional mosfet. In this case eventually x will become 0, so γ will reduce to γ and the equation is given by, It is found that the membrane always snaps down near the onset of strong inversion, i.e., ψ po < ψ s < 2ϕ F which is a very unique characteristic. Moreover, this result highlights the usefulness of a unified analytical model including all regimes of MOS inversions (weak, moderate and strong).

I D -V G Characteristics
In strong inversion region the total inversion charge is the summation of the charges induced by both the gates.
i.e. Q inv = Q finv +Q binv but |Q finv | = |Q binv |so, Q inv = 2Q finv . Now when the gate voltage increases the intrinsic gate voltage, V gint becomes Where C gcint = intrinsic gate to channel capacitance.
And C gap = gap capacitance. is given by, Where or, The drain current, I D can be written as Where t r is the transit time of electron from source to drain. So, This is the approximate relationship of drain current vs gate voltage characteristics for our first device structure.

Fabrication Steps
To combine MOSFET and MEMS fabrication, an innovative process has been developed [19]. The fabrication process is consisting of three masks as well as one chemical mechanical polishing steps (Fig. 4.). At first a silicon wafer has been  Fig. 4.a). Thermal gate oxides have been grown at the active regions. In the same step, the finger like oxide layers has been achieved by etching to reduce the surface roughness. The air gap of the suspended gate is defined by the height of the isolation layer because this layer will be used as the anchor for the suspended structures. A thick photoresist mask was used to implant through the thin gate oxides after the source and drain were photolithographically established ( Fig. 4.b). To make the n and p type active regions, boron and phosphorus were used as dopants. The most important thing is to control the gap between the channel and the gates which is achieved by depositing a polysilicon sacrificial layer of 10 nm by LPCVD (Fig. 4.c). Then, a plasma of C4F8 and SF6 is used to patterned the source and drain contacts. Aluminum-silicon alloy film (AlSi 1%) has been incorporated for the suspended gates ( Fig. 4.d). Sputtering technique has been used to deposit a thin structural of AlSi (1%) under 20KHz, 2000 W pulsed-DC condition and high vacuum. Chlorin-based plasma is used to selectively etch the metal layer to get the proposed DSG-MOSFET (Fig. 4.e).

Simulation Setup
Based on the finite element approach the behaviour of the DSGMOSFET is simulated using COMSOL Multiphysics. COMSOL Multiphysics is a sophisticated interactive platform for modelling and solving partial differential equation (PDEs)based scientific and engineering issues.
The doping density of a non-degenerate semiconductor is minimal, and the donor electrons do not interact. As a result, the electron concentration can be calculated using the Maxwell-Boltzmann (MB) approximation. The electrons begin to interact as the doping density rises. The Fermi level is within the conduction band (CB) when the concentration of electrons in the CB exceeds the density of states Nc, rendering the MB approximation ineffective. As a result, Fermi-Dirac (FD) statistics were employed to calculate carrier concentrations. The mobility of carriers inside a semiconductor is affected by a number of parameters, making it a complicated function of temperature, electrical field, and density of doping. Mobility Models have been incorporated into the simulator to handle these issues. The Shockley-Read Hall (SRH) Recombination Model was used to account for carrier recombination as a result of device defects. Also, drift-diffusion model has been incorporated. The DSGMOSFET is simulated using the COMSOL Multiphysics interface and is made up of two AlSi nanomechanical bridges. The electromechanics interface is used in the proposed model to simulate and solve the associated physics for the structural deformation and electric field.

Comparison between Two Structures
In this section, the comparison between two structures (proposed & compared) in terms of pull-in and pull-out voltages with respect to the structural parameters has been analyzed (both analytical and Simulation). Channel width (T si ), air gap (t gap ), Young's modulus (E) and the beam thickness (h) of the gates have been considered as major structural parameters. All the parameters for the both the structures are considered as same such as, channel length (L), T si , t gap , oxide thickness (t ox ) double suspended beam thickness is taken as 30 nm, 50 nm, 10 nm, 2 nm and 1 nm. The doping concentration N A is 10 18 /cm 3 for both the structures. The travel range is a function of doping concentration and with larger doping concentration, it gets minimized which improves the device performance [2]. L and T si are chosen in such a way so that it falls under the small geometry devices. However, at such small geometry short channel effects may occur. Hence, Double gate structure has been considered.
The t ox is considered as 2 nm due to the fact that below 2 nm, van der Waal forces [2] and Casimir effects [18] will have significant influences on the device performance. The suspended beams will only get mechanically released if the electrostatic forces become smaller than the restoring elastic forces. However, for t ox < 2 nm, the van der Waal force will not remain weak and hence the pullout voltage will increase which in turn makes the Fig. 7 Pull-in (a) and Pull-out (b) voltage variations with respect to t beam for both proposed and compared structures for V FB = 0.13 mV, Г = 20 μJ/m 2 , D0 = 0.2 nm, E = 170GPa, t gap = 10 nm with the said device parameters Fig. 8 Pull-in (a) and Pull-out (b) voltage variations with respect to Tsi for both proposed and compared structures for V FB = 0.13 mV, Г = 20 μJ/m 2 , D 0 = 0.2 nm, E = 170GPa, t gap = 10 nm, t beam = 1 nm with the said device parameters hysteresis window width smaller [2]. Also, from eq. (11) it can be observed that the adhesion force is directly proportional to interfacial adhesion energy per unit area and inversely proportional to surface roughness. Due to air presence between the gate oxides and suspended gates, the surface roughness is already very small. However, for the both the structures, a unique finger like oxides (of 2 nm) has been considered ( Fig. 1(b)) so that the surface roughness can get more smaller but also keeping the van der Waal constraint. Hence, F a is considered negligible in pull-out voltage modelling (eq. (14,15)).
Figures 5, 6, 7 and 8 depicts the V pi and V po characteristics for varying E, tgap, suspended beam thickness (t beam ) and channel width (T si ). For both the voltages it can be observed that V pi and V po increase with increase in E, t gap and t beam but decrease with T si . There is a negligible change in.
V pi for both the structures. Equation (10) and (11) shows the V pi for proposed and compared structure and it is clear that as the oxide thickness is in addition with t gap for eq. (10), hence it will not affect the V pi significantly even when tox is absent [eq. (11)] and also t gap , E and t beam are in direct proportional with V pi whereas T si is inversely proportional. However, there is a significant change in V po for the both the structures. Equation (14) and (15) shows the V po for both the structures. As the lower gate oxide is absent in case of compared structure, hence tox and ϵox of eq. (14) is replaced by t gap and ϵ gap in eq. (15) and hence significant change can be observed. Figure 5(b) also shows that V po is in millivolt range for without lower gate oxide structure (compared) and is in micro volt range for with lower gate oxide structure (proposed). Hence, the proposed structure shown in Fig. 1(b) is the preferred structure due to lower power consumption. Young modulus is varied from 170Gpa to 2000Gpa. As the young modulus is increasing the beam gets stiffer and as a result the pull-in and pull-out voltage increase. The air gap t gap is varied from 2 nm to 10 nm. As it increases, the V pi and V po also increase due to the fact that with increasing the air gap the electrostatic force also increases which in turn makes the two voltages high. The same analysis can be done for the suspended beam thickness, t beam which is varied from 0.1 nm to 1 nm. But in case of channel width Tsi, which is varied from 30 nm to 60 nm the pull-in and also the pull-out voltage decrease with increasing the channel width. It has been noted that excessive increasing the channel width or excessive lowering the E, t gap , t beam there is a sticking chance of the beam on the oxide as the elastic force become no longer strong as the adhesion force, Fa < ktgap. The on to off capacitance ratio is an important parameter for a RF switch which should be larger than 100. Typical DSGMOSFET switching capacitance characteristics is shown in Fig. 10.
As per the analyzed result, the proposed structure has a on capacitance to off capacitance ratio, c on /c off = 265.39 which can be considered as a better result. Here the value of t ox = 2 nm. The threshold voltage of the device is set as V th = V pi . The modulation of the threshold voltage can be done by changing the pull-in voltage.
It is also found that when t ox > 2 nm, it does not have any adverse effect on the pull-in voltage [6] which can be confirmed by Fig. 11. and also confirmed the reason behind taking tox = 2 nm. Figure 12. describes the nature of I D vs V G characteristics of the proposed structure of the DGSGFET. As it is a shortchannel device, the influence of V D on V pi and V po can be noticed, but which can be minimized by increasing the substrate doping [2]. As L is smaller, the electrostatic force and the fringing fields applied to the double suspended gates by the source and drain regions become an important factor also. The I D -V GS characteristic has hysteresis, that means the pull-out voltage is lower than the pull-in voltage. An improvement to be noticed on the I ON /I OFF ratio than the conventional single gate SGFET [2]. The sharp transition in V pi and V po indicates that it can be used as an ideal switch with infinite sub-threshold slope [2].
Noise Immunity As per the detailed analysis and the graphs (Figs. 5 to 8), it can be observed that V pi and V po , for the proposed structure, are in millivolt and microvolt range. However, for the second structure (compared) both the V pi and V po are in millivolt range. Hence, for the proposed structure there is a difference of 1000 times between V pi and V po . Now in any digital circuit, if noise arrives then there is a chance that the voltage level may get changed or shifted from lower level to higher level or vice versa. Due to which the stored data in the system will get changed and it will provide erroneous data as outputs. So, system performance is highly dependent on noise. However, as there is a huge difference between V pi and V po of the proposed structure, if any noise arrives then the probability of that noise to change the voltage levels of the data is very low. Hence, the stored data of the system will remain safely encrypted which makes this structure noise immune. But this can't be said for the second (compared) structure although in terms of power consumption it is providing better performance than [2]. But with respect to the proposed structure, it will consume more power as both V pi and V po are in millivolt range. Also, there is no huge difference between those two voltages, hence in terms of noise immunity, the compared structure is not noise immune like the proposed structure. Hence, the structure depicted in Fig. 1(b) is considered as the proposed structure over the structure depicted in Fig. 1(e) in terms of both noise immunity and low power consumption, which enable the proposed structure to be used in ultra-low power applications.

Conclusion
Two different double suspended gate structures have been designed and also performance of those structures has been analysed with respect to the several structural dimensional parameters. Based on lower power consumption and noise immunity, the first structure [ Fig. 1(b)] performs better than the second structure ( Fig. 1(e)). Hence, the first structure has been considered as the proposed structure. Also, the proposed structure possessed a better I ON /I OFF ratio over single suspended gate MOSFETs. Analytical modelling of the proposed DSGMOSFETs as well as the compared structure has been developed. The proposed structure can be used in any ultra-low power applications as the V pi and V po are in millivolts and microvolts range.