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Research Article
Savio Jay Sengupta
Jadavpur University
Corresponding Author
ORCiD: https://orcid.org/0000-0002-5504-0662
License:
This work is licensed under a CC BY 4.0 License. Read Full License
Purpose
The purpose of this paper is to develop the design and analytical modelling of a noise immune double suspended gate MOSFET (DSG-MOSFET) for ultra-low power applications. Also, Important performance parameters of the proposed structure such as pull-in and pull-out voltages have been thoroughly investigated with respect to the valuable structural parameters.
Methods
The design methodology used is EKV based analytical approach to calculate the pull-in and pull-out voltages with ingeniously developed boundary conditions which helps achieving reasonably accurate result. Also, the I-V characteristics has been modelled to justify accuracy.
Results
The experimental result shows that the pull-in and pull-out voltages are in millivolts and microvolts range and hence it can be used in ultra-low power applications. As the ratio between the pull-out and the pull-in voltage is 10^(+3) range, justifies that the proposed structure is noise immune. The ID-VGS characteristic has hysteresis and this sharp transition in pull-in and pull-out voltage indicates that it can be used as an ideal switch with infinite sub-threshold slope.
Conclusion
This paper presents a compact EKV based analytical modelling of pull-in and pull-out voltages for a DSG-MOSFET which predict the device characteristics reasonably similar to simulated results. Also, for the first time the noise immunity for a DSGMOSFET has been analyzed.
Keywords
Double suspended gate MOSFET (DSGMOSFET), Microelectromechanical system (MEMS), Noise immunity, Data encryption, Mechanical Hysteresis, COMSOL
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Peer Review Timeline
CURRENT STATUS: Published
View the published article at Silicon.
Version 1
Posted 12 Feb, 2021
No community comments so far
Editorial decision: Major revisions
On 16 Apr, 2021
Reviews received
Received 11 Feb, 2021
Reviewers invited
Invitations sent on 04 Feb, 2021
Editor invited
On 03 Feb, 2021
Editor assigned
On 03 Feb, 2021
First submitted
On 29 Jan, 2021
Metrics
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PDF Downloads: ...
HTML Views: ...
Subject Areas
Electronic Materials and Devices
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A new preprint design is coming!
We have improved readability, clarity, accessibility, and opportunities for engagement.
See the published version of this preprint at Silicon.
This is a preprint, a preliminary version of a manuscript that has not completed peer review at a journal. Research Square does not conduct peer review prior to posting preprints. The posting of a preprint on this server should not be interpreted as an endorsement of its validity or suitability for dissemination as established information or for guiding clinical practice.
Learn more about In Review
Research Article
Savio Jay Sengupta
Jadavpur University
Corresponding Author
ORCiD: https://orcid.org/0000-0002-5504-0662
Badges
Prescreen
This manuscript passed our Prescreen assessment
Complete author information
Appropriate declaration statements
Potential risks to human health
Prescreen
Peer Review Timeline
CURRENT STATUS: Published
View the published article at Silicon.
Version 1
Posted 12 Feb, 2021
No community comments so far
Editorial decision: Major revisions
On 16 Apr, 2021
Reviews received
Received 11 Feb, 2021
Reviewers invited
Invitations sent on 04 Feb, 2021
Editor invited
On 03 Feb, 2021
Editor assigned
On 03 Feb, 2021
First submitted
On 29 Jan, 2021
Metrics
Comments: 0
PDF Downloads: ...
HTML Views: ...
Subject Areas
Electronic Materials and Devices
License:
This work is licensed under a CC BY 4.0 License. Read Full License
View the published article at Silicon.
Purpose
The purpose of this paper is to develop the design and analytical modelling of a noise immune double suspended gate MOSFET (DSG-MOSFET) for ultra-low power applications. Also, Important performance parameters of the proposed structure such as pull-in and pull-out voltages have been thoroughly investigated with respect to the valuable structural parameters.
Methods
The design methodology used is EKV based analytical approach to calculate the pull-in and pull-out voltages with ingeniously developed boundary conditions which helps achieving reasonably accurate result. Also, the I-V characteristics has been modelled to justify accuracy.
Results
The experimental result shows that the pull-in and pull-out voltages are in millivolts and microvolts range and hence it can be used in ultra-low power applications. As the ratio between the pull-out and the pull-in voltage is 10^(+3) range, justifies that the proposed structure is noise immune. The ID-VGS characteristic has hysteresis and this sharp transition in pull-in and pull-out voltage indicates that it can be used as an ideal switch with infinite sub-threshold slope.
Conclusion
This paper presents a compact EKV based analytical modelling of pull-in and pull-out voltages for a DSG-MOSFET which predict the device characteristics reasonably similar to simulated results. Also, for the first time the noise immunity for a DSGMOSFET has been analyzed.
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
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