A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs

This present article interprets the analytical models of central channel potential, the threshold voltage, and subthreshold current for Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs. The parabolic approximation equation with appropriate boundary conditions has been adopted to solve the 2D Poisson’s equation for determining the central channel potential. The minimum channel potential is obtained by potential channel expression, and it is utilized to determine the threshold voltage and subthreshold current by using the Drift-Diffusion method. The behaviour of GD-JL-GAA MOSFETs has been examined by varying physical device parameters such as doping concentration (NDn), channel thickness (tsi), oxide thickness (tox), and channel length ratio (L1: L2). The mathematical analysis shows that the nominal gate leakage current in GD-JL-GAA MOSFETs due to high graded abrupt junction inside the channel region. The analytical model results have been verified with simulation data extracted from a TCAD simulator.


Introduction
The junctionless (JL) field-effect transistor (FET) has been studied as the most promising alternative device for MOSFETs in the nanometre regime [1,2]. Junctionless MOSFET is a device that has no junctions between source/ drain and channel. By the merit of their junction-free nature, JL devices mitigate process demurs such as abrupt junctions and low thermal budget. The working principle of JL MOSFET is based on the bulk conduction mechanism instead of surface conduction as in conventional MOSFETs. The junctionless transistor has several advantages, such as reducing short channel effects (SCEs), high I ON /I OFF ratio, nearly ideal subthreshold slope (60mv/decade), and offer low series resistance between the source and drain [3]. The multigate structure has been proposed to improve gate control over channels and diminished SCEs, such as double gate, triple gate, surrounding gate, and π gate [4].
Multigate JLFETs acquire enhanced mobility, better scalability, higher driving current, good switching characteristics, and better trans-conductance than conventional MOSFETs. Consequently, many researchers [5][6][7][8][9][10][11][12][13][14] have proposed junctionless double-gate (JL-DG) FETs. Chiang et al. [5] investigated the bulk conduction-based analytical threshold voltage model for double-gate short channel (JL-DG) FETs. It was illustrated that JL-DG FETs exhibit better performance than junction-based DG-MOSFETs in terms of DIBL, threshold voltage roll-off, and subthreshold slope. Jin et al. [6] proposed a subthreshold current model for symmetric and asymmetric short channel DG-JL-MOSFETs. They demonstrated the variation of subthreshold characteristics caused by structure asymmetry. The enhancement of carrier transport efficiency is found in the dual-material gate-engineering device [7]. Dual material gate (DMG)-based devices are constructed using different metals with different work functions as gate electrodes. DMG structures have been proposed in DG-JL and surrounding gate all around JL FETs to optimized electrical characteristics [8,9]. Wang et al. [10] proposed the subthreshold current model for DM-DG-JLFETs. Agarwal et al. [11] derived a 2D analytical model for the surface potential of DM-DG-JLFETs. Furthermore, they have derived the expression of threshold voltage for the device. Kumari et al. [12] investigated a 2D analytical model for the subthreshold current of asymmetric DM-DG-JLFETs. Further, they have illustrated the analog and digital performance of DM-DG-JLFETs. Singh et al. [13] reported DG -JLFETs that incorporate dielectric pockets at the source and drain side. They have demonstrated that DP-DG-JLFETs exhibit improved I ON /I OFF drain current ratio, subthreshold swing characteristics, and DIBL over conventional DG-JLFETs. Gola et al. [14] investigated the effect of substrate bias voltage and induced surface potential on the threshold-voltage of Tri-gate junctionless FETs (TG-JLFETs). In specific, gate-all-around junctionless FETs (GAA-JLFETs) have been reported as promising structures for high-performance devices that considered their gate voltage controllability, exciting scalability, and improved carrier transport mechanism [15,16]. Trivedi et al. [17] investigated reliability issues of dual gate material (DMG) and single gate metal (SGM) junctionless accumulation mode surrounding gate (JAM-SG) FETs. They have reported an effect of interface charges on the device performance of SGM and DGM-JAM-FETs for different temperature variations by simulation results. Abhinav et al. [18] investigated surface potential for junctionless cylindrical surrounding gate (JL-SCG) FETs.
The kinds of literature discussed above are based on uniform doping concentration. Various channel engineering has been reported in JLFETs to deal with SCEs, mobility, and hot carrier degradation effects [5][6][7][8][9][10][11][12][13][14]. Kumari et al. [19] analyzed an empirical model for non-uniform doped symmetrical JL-DG MOSFETs. They explored different parameters such as threshold voltage, drain current, subthreshold slope, and DIBL for different peak doping concentrations. Kumari et al. [20] proposed the subthreshold model of Gaussian doped channel double gate JLFETs, including source/drain depletion length. All discussed channel engineering is based on the vertical channel doping profile. Few researchers have reported lateral channel engineering structures to deal with SCEs, mobility, and hot carrier effects [21,22]. Duksh et al. [23] formulated an analytical model of Graded Channel Double gate JLFETs (GC-DG-JLFETs). They derived the expression of subthreshold current, subthreshold swing, and threshold voltage. Based on a literature survey, till now, the analytical modeling of central channel potential, the Threshold voltage (V TH ), and Subthreshold current of Graded-Doped Junctionless-Gate-all-around (GD-JL-GAA) MOSFETs have not been derived. This article has proposed the analytical modeling of Centre channel-potential of Graded-Doped Junctionless-Gate-allaround (GD-JL-GAA) MOSFETs using the Poisson Equation with suitable novel boundary conditions. There is the minimum centre channel potential found in the L 1 channel region due to low doping concentration. The Threshold voltage (V TH ) and Subthreshold current are obtained using the minimum centre channel potential. The analytical modeling results have been verified through the TCAD simulation results, where they found excellent agreement between mathematical and simulation results. In section II, Our proposed device structure is defined with physical parameters. The analytical modeling of Centre channel Potential, Threshold Voltage (V TH ), and Subthreshold Current are derived in Section III. The model variation is written in Section IV and, in the end, concluded our proposed structure in Section V.

Device Structure
The schematic view of the GD-JL-GAA MOSFET structure is shown in Fig. 1. The channel region is wrapped by a thin oxide layer and over deposited the gate metal. The channel region is divided into two equal parts of length L 1 and L 2 , as shown in Fig. 1b. The channel length L 1 and L 2 are doped with two different doping concentrations, N D1 and N D2 , respectively. The drain side L 2 region doping concentration is higher than the source side L 1 region doping concentration in this device. The physical parameters of the proposed GD-JL-GAA MOSFET are listed in Table 1.

Channel Potential Modeling
The channel potential shows no variations with the angular (θ) axis. The channel potential ϕ(r, z) of the GD-JL-GAA MOSFET can be obtained by solving the 2D Poisson's equation in the cylindrical coordinate as [24]: Where, n = 1 and 2 are used for channel regions 1 and 2, respectively. The potential distribution in all the two-channel regions are written as a parabolic approximation: The coefficients C 0n (z), C 1n (z), and C 2n (z) are obtained by using following the boundary conditions.
∂ϕ n r; z ð Þ ∂r Where, Now, the parabolic approximation equation coefficients are obtained by using the Eq. (2) and above boundary conditions for n th channel potential as: By utilizing the above Eqs. (8)-(10) in Eq. (2), and solving the Eq. (1) using the obtained condition from Eq. (2) as ϕ Cn (z): Where, By solving the Eq. (11), the channel potential of the channel regions L 1 and L 2 can be obtained as: The above equations' coefficients are obtained (for n = 1 and 2) using the following boundary conditions. Where, The minimum channel potential location (z min ) in the zdirection can be obtained as: Using the Eq. (27) into Eqs. (14) and (15), the minimum channel potential ϕ Cn Z min ð Þ can be found as:

Threshold Voltage (V TH ) Formulation
The minimum gate voltage is required to apply in the device to become an ON-state is known as the threshold voltage. The threshold voltage (V TH ) for the GD-JL-GAA MOSFETs has been formulated when the minimum channel potential equals the Fermi potential value (V bi ) [23,25]. According to Eq. (28), the minimum channel potential occurred in region 1. Thus, the threshold voltage (V TH ) expression can be written as: Where,

Subthreshold Current
The subthreshold current equation is derived using minimum centre channel potential. The minimum channel potential has been calculated by Poisson equation derivation. The current model is derived through the Drift-Diffusion theory. It is expressed as [26]: Where q is the electron charge, μ is the electron mobility, tsi 2 is the channel radius, N i is the intrinsic electron concentration, and V t is the thermal voltage. The above Eq. (37) has been modified for more accurate results due to different channel regions' doping concentrations. Now, It can be expressed as [27] for our proposed device subthreshold current model.

Model Validation and Discussion
In this section, the proposed analytical modeling of GD-JL-GAA MOSFETs has been presented and validated with TCAD device simulator results. The following models are incorporated in the proposed GD-JL-GAA MOSFETs structure during the simulation at room temperature. Such as Concentration-dependent mobility model, High fieldsaturation mobility model, Lombardi (CVT) mobility, Fermi-Dirac, and Shockley-Real-Hall (SRH) recombination with auger models [28]. The quantum effects have been ignored in this work, as the results are unnecessary for more comprehensive than 5 nm channel thickness and 10 nm channel length [29]. The constant current method is used for the threshold voltage extraction. Figure 2 demonstrates the electrostatic channel potential along the channel length for gradeddoped and uniformly doped JL-GAA MOSFETs. As we observe from the figure, central channel potential is found to pull down in graded channel devices, suggesting that the source side barrier height increased. It is also expressed that the minimum potential transfers towards the source side in the graded-doped (GD) device. As a result, the GD-JL-GAA MOSFETs should have better immunity for short channel effects (SCE's) than uniformly doped JL-GAA MOSFETs. Figure 3 illustrates the variations of central channel potential along the channel length for various ratios of L 1 :L 2 . It is executed from the figure that the source channel's barrier height increases with the change in the ratio of L 1 :L 2 . It occurred due to an increase in the length of L 1 . The minimum central potential moves towards the drain side because of increased doping concentrations on the drain side. Thus, the L 1 :L 2 ratio may be useful as an extra parameter for optimizing the device's threshold voltage. Figure 4 shows the variation of central channel potential against the channel length. It is seen that the barrier height increases at the source end as channel length increases because the gate control over the channel charges increased. Thus, the long channel length shows better immunity towards SCE's. Figure 5 displays the channel potential variation against the channel length for distinct values of channel thickness. It has been observed from the figure, when the channel thickness increases, the minimum channel potential is pulled up, which indicates that the gate control over the channel losses gradually. It happened because a smaller thickness of the channel would be more efficient in achieving volume depletion at zero gate voltage. Thus, GD-JL-GAA MOSFETs have better immunity towards SCE's for a channel having a low thickness. Figure 6 demonstrates the channel potential with the channel length for different values of oxide thickness. It is noticed that the source channel barrier height lowers as the oxide thickness increments, which indicates that the gate control over the channel charges losses gradually with the thickness of the oxide. Thus, the minimum oxide thickness is better for immunity towards SCE's. Figure 7 present the variation in threshold voltage along the channel length for unlike value of   Figure 8 illustrates the threshold voltage against the channel length for various values of channel thickness (t si ). As we have discussed in Fig. 5, as the t si increases, the gate gradually loses its control over the channel charge. This effect attributes to a reduced threshold voltage for a higher t si , as demonstrated in Fig. 8 that degrades subthreshold characteristics. Thus, a thinner channel is required to diminish leakage current. Figure 9 shows the variation of threshold voltage with oxide thickness along the channel length. This figure reflects that the gate control over the channel charges decreases as oxide thickness increases, leading to the reduced threshold voltage. Figure 10 displays the subthreshold current with gate voltage for the uniformly doped and graded-doped (GD) JL-GAA MOSFETs. It is observed from Fig. 10 that the OFF-state current (I OFF ) reductions with a drop in the doping concentration of region 1 of the channel, N D1 . It happened because of the higher source to channel barrier height for the channelmodulated device, as seen in Fig. 2. Hence, the leakage current is insignificant in GD-JL-GAA MOSFETs. Figure 11 demonstrates the variation of subthreshold current against gate voltage for distinct channel length values. This plot reflects    that the I OFF significantly decreased when the channel length is increased from 20 nm to 40 nm. It occurred due to the barrier height being raised between the source and channel. Hence, the SCE is immune at a longer channel length. Figure 12 illustrates the variation of subthreshold current against gate voltage, unlike channel thickness values for graded channels. It is noticed that the gate loses its control over the channel for the thicker channel, and it is leading to a higher gate leakage current. Further, it is also observed from Fig. 13 that more increased oxide thickness leads to a significant gate leakage current due to loss of gate controllability.

Conclusion
In this article, the channel potential, the Threshold voltage, and Subthreshold current of Graded-Doped Junctionless-Gate-all-around (GD-JL-GAA) MOSFETs have been presented. The impact of different device physical parameters such as L 1 region doping concentration, channel length, channel thickness, oxide thickness, and channel length ratio L 1 :L 2 have been examined. The L 1 region doping concentration and channel length ratio L 1 :L 2 have been found as essential physical parameters that can be changed for optimizing device performance. Simulation results have validated the model results.