On the examination of temperature-dependent possible current-conduction mechanisms of Au/(nanocarbon-PVP)/n-Si Schottky barrier diodes in wide range of voltage

Au/(nanocarbon-PVP)/n-Si SDs were fabricated and their current-conduction mechanisms (CCMs) have been examined in elaborative by utilizing current–voltage (I–V) characteristics in a temperature range of 60-340 K at (± 3 V) ranges. The values of ideality factor (n) and zero-bias barrier height (ΦB0) determined from the linear-part of semi-logarithmic forward bias IF–VF properties based on Thermionic-Emission (TE) theory revealed that decrease in ΦB0 and increase in n with decreasing temperature. Additionally, Richardson constant (A*) value was very found close to its theoretical value. The values of ΦB0 and n changed from 0.173 eV to 0.837 eV and 16.60 to 2.85 with increasing temperature from 60 to 340 K. The ΦB0 relationship with temperature is disagreement with the negative temperature coefficient of the bandgap of Si for the ideal diode. The calculated higher value of n at low temperatures was attributed to the inhomogeneities of BH rather than the interlayer, surface-states (Nss), and image-force lowering. With lowing temperatures, CCMs may be governed by tunneling over the lower barriers, via Nss, and generation recombination (GR), as well as TE and hence a complete description of CCM and understanding of the formation BH, remain a compelling problem. Nss-(Ec–Ess) profile was also obtained from IF–VF data for each temperature.


Introduction
In the metal-semiconductor (MS) structures, the used interlayer such as insulator/oxide, organic or composite interlayers between metal (M) and semiconductor (S) is important to increase the quality/ performance of them because it may be prevented an inter-diffusion between the metal and interlayer by isolating the metal from the semiconductor and regulate the current conduction [1][2][3][4][5]. Therefore, nowadays, both scientific and technical problems of the metal-semiconductor (MS) type Schottky barrier diodes (SDs) with and without interlayer and solar cells (SCs) are appropriate to the increase in the performance of them and to reduce in the cost and easy fabrication methods [1][2][3][4]. Moreover, it is an essential demand to improve the cost-effective devices with high performance inside of conventional MS and MIS type SDs and SCs. However, the performance of these devices is decreased under real operating conditions when compared to ideal cases, especially with lowing temperatures. In other words, with lowing temperature, the probable current-conduction mechanisms (CCMs) become more complex due to deviation from the standard thermionicemission (TE) theory [5][6][7][8][9].
Usually, the observed very lower value of A * as experimental indicated that the spatial inhomogeneous of BH and potential fluctuations at the interface which contains many low and high barrier areas or patches and hence the current transport across diode would flow preferentially through these lower barriers and leads to an increase in ideality factor. Therefore, a perfect description of CCMs through barrier and comprehension of the nature of BH still at M/S interface remains a compelling problem. Under room temperatures, in these structures, several CCMs for instance TE, field/thermionic-field emission (FE/ TFE), multistep tunneling (MT) via N ss , and Gaussian distribution (GD) of BHs compete and one of them may dominate over the others in a particular temperature and bias voltage region. Besides, there may be simultaneous contributions from two or more CCMs. However, TFE and FE are effective only with lowing temperatures and high doping concentrations in semiconductors [3,[9][10][11][12][13].
In practice, utilizing the TE theory, the zero biased BH (U B0 ) values, understood from the linear portions of semi-logarithmic I-V curves in the forward-biased region, increase by increasing temperature, while the n values decrease and the traditional Richardson graph deviates considerably from linearity under room or with lowing temperatures. When the temperature becomes decrease, charge carriers can easily pass over the existence of patches of lower barriers at around mean BH and so leads to a large ideality factor, but as temperature increase, these lower barriers and patches are offset by the much greater area of the uniform region, consequently, most current flows through the uniform region. Besides, the magnitude of the A * obtained from the Richardson plot can be some orders less than the theoretical value. It is well known that the increase in BH with increasing temperature does not correspond to the prohibited band gap negative temperature of the semiconductors.
The inconsistency observed between experimental and theoretical values is related to many magnitudes. For example, surface fabrication may include natural or a layer or both thickness and homogeneity, BH homogeneity at the M/S interface, voltage, surface temperature, surface conditions of these devices (N ss ), series and shunt-resistances (R s , R sh ) [12][13][14][15][16][17][18]. When observed experimentally, the low A * value shows that the effective area is much smaller than the diode area [19][20][21][22][23]. Therefore, analysis of CCMs in the temperature amplitude and applied pre-voltage voltage can ensure us with a lot of information, on the other hand, only in narrow or narrow-temperature range BH does not give knowledge about the nature of the CCMs and the effect of the interlayer.
Polyvinylpyrrolidone (PVP) is an important polymer, which has an impact on the electrical and dielectric properties of structures. Since PVP has various features such as high environmental stability, easy and cheap production and non-toxic properties, it is used in various fields, especially the medical and food industry [24][25][26]. As an industry practice, by doping PVP with various metal or metal-oxides groups in diodes or capacitors their conductivity and capacitive properties can be examined [24,[27][28][29][30][31].
The purpose of this work is to produce Au/(nanocarbon-PVP)/n-Si (MPS) SDs and investigate the probable CCMs by utilizing the I-V-T properties in a wide range of temperature (60-340 K) to get more acknowledge on the nature of BH, CCMs and effect of the interlayer. The energy-dependent profiles of the surface-states (N ss vs E c -E ss ) were found in consideration of voltage-dependent BH and n for each temperature. We observed that U B0 magnitude increases with increasing temperature, n decreases, this behavior is clarified by TE mechanism which is a GD of BH rather than other CCMs such as TFE and FE. characterize this as-received material. In this working, Au/(nanocarbon-PVP)/n-Si (MPS) SDs were performed on phosphor doped (n-Si) substrate with (100) float -zone, 300 lm thickness, and 1 X cm resistivity. First, the substrate went through ultrasonic acetone, alcohol, deionize (DI) water with 18 MX.cm resistivity cleaning and a dilute HF dip in the ultrasonic bath to remove oxide produced on the surface. After that, it was cleaned in H 2 O, H 2 O 2 , and NH 4 OH (3:1:1) solution at 70°C and then rinsed with high-pure deionize water at about 10 min. Immediately it was dried with dry N 2 gas and subsequently was placed inside the deposition chamber to perform ohmic contact. After that high-pure gold (99.999%) with 150 nm thick was thermally evaporated on the whole backside of the substrate at 10 -6 Torr. In order to perform a good ohmic contact with low resistance and high quality, the backside coated p-Si was annealed at 450°C for 30 s in the nitrogen ambient. The prepared (nanocarbon-PVP) composite was grown on the front of n-Si substrate at a spin speed of 2000 rpm for 45 s by the spin-coating method. Finally, circular dots with 1 mm diameter and 150 nm thick high-pure of Au rectifying contacts were produced on the (nanocarbon-PVP) composite through a metal-shadow mask in the high-vacuum thermal evaporation system at 10 -6 Torr. To perform the forward and reverse bias I-V measurements of the SDs, they were fixed on a Cu holder by silver paste and electrode connections were made by silvercoated thin Cu wires. The morphological and structural nanocarbon-PVP composite was performed using Scanning Electron Microscope (SEM), XRD analysis was recorded by Philips X'Pert, X-ray diffractometer using Cu Ka radiation (wavelength = 1.54056 Å ), I-V measurements were performed on a Janis VPF-475 cryostat temperature controller utilizing a Keithley 2400 I-V source meter. All measurements were made utilizing a microcomputer via an IEEE-488 ac/dc converter board.

Experimental results and discussions
X-ray diffraction (XRD) provides information on the characterization of materials. It is also used to analyze structural parameters such as the mean crystal size (D), crystal structure and defects of particles. The XRD pattern of the sheetlike nanocarbon is shown in Fig. 1. All the diffraction peaks at 2h: 26.5°, 43.0°, 54.6°, and 77.8°can be indexed as the (002), (100), (004) and (110) plans of nanocarbon. The strong diffraction peaks at 2h = 26.5°could be ascribed to the (0 0 2) reflection and (1 0) band of nanocarbon. The mean crystal size (D) of the nanostructure was estimated using Debye-Scherer's equation [32,33].
where h is the Bragg angle, k is the so-called Scherrer constant and the other units are available in the literature [32,33]. The k value used was 0.9. The XRD result reveals that the mean crystal size (D) of nanostructure has an estimated value of 15 nm. The topographical and morphological of the interface layer coated on the front of the semiconductor can be affected the electrical properties and performance of the diode [34][35][36][37]. Thus, the topographical and morphological of the interface layer should be examined. Scanning Electron Microscope (SEM) provides information about topographical and morphological and details them. It can also detect and analyze surface fractures. Figure 2 shows the representative SEM images of sheetlike nanocarbon at different magnifications. While the average size of the clusters was found about a micrometer, the meansize of the nanoparticles was found less than 50 nm.
The ln(I) vs V plot s of the Au/(nanocarbon-PVP)/ n-Si (MPS) type SD was given in Fig. 3 in the wide temperature range (60-340 K). In this figure, the forward bias ln(I) vs V plot has a good straight line with different slopes and then deviated from the linearity at enough high forward-bias voltages due to the existence of R s and (nanocarbon-PVP) interlayer for each temperature [38,39]. The effect of R s in the linear On the other hand, the value of current at the forward bias voltage increases with increasing voltage almost exponentially and starts to deviate from the linearity for enough high-forward bias voltage due to the effect of R s and polymer interlayer for each temperature. Such behavior of the current with bias voltage is known as ''rectifying rate'' (RR = I F /I R ) and it decrease with increasing temperature. Since the MS and MIS type SDs have an R s , the connection with I and V for them based on standard TE theory (V C 3 kT/q) is given as [14,15,40]: In Eq. 2; V is the applied voltage on the diode, A* is the Richardson constant (= 112 A/K 2 cm 2 for n-Si) and the other units are known in the literature [41][42][43][44][45][46]. The expressions in front of brackets are called the reverse-saturation current (I 0 ) which is obtained from the interception of the linear parts ln(I) vs V plot. Thus, the value of zero-bias BH (U B0 ) can be calculated from the expression (I 0 ) as following equality for each temperature.
The other important magnitude of SDs is the ideality factor (n) which is more effective in the performance by controlling on the CCMs through interfaces and it can be also obtained from the slope of ln(I) vs V plot as given follow [15,47,48]: where the e s is the dielectric constant of semiconductor, and the other units are known in the literature [41][42][43]. Thus, the obtained experimental values of these main electrical magnitudes (I 0 , n, U B0 ) of the Au/(nanocarbon-PVP)/n-Si (MPS) type SD are shown in Table 1. As shown both in Table 1 and Fig. 4, values of main electrical magnitudes (I 0 , n, U B0 ) are a strong function of temperature and changed from the 1.14 9 10 -12 A, 16.60, and 0.173 eV for 60 K to 4.05 9 10 -8 A, 2.85, and 0.837 eV for 340 K.
As can be seen in Eq. 4, the use a high dielectric interfacial layer (e i ) takes the square bracket closer to zero. On the other hand, the obtained high values of n, particularly at low temperatures can be attributed to the thickness of interfacial polymer layer (d i ), surface states (N ss ) located at interlayer/semiconductor interface, a spatial barrier inhomogeneities at M/S interface, depletion layer width (W D ) or doping level of donor atoms (N D ), image force lowering under electric field, and interface recombination. Because an inhomogeneity of barrier height (BH) includes many lower barriers/patches at around of mean BH and hence the current transport across the diode would flow preferentially through these patches at low temperature and leads to a large ideality factor. As the temperature increase, these patches are offset by the much greater area of the uniform region, as a result, most current flows through the uniform region [49][50][51]. Additionally, in Table 1 and Fig. 4, while n increases with decreasing temperature exponentially, U B0 decreases as exponentially. Such alteration in U B0 with temperature is disagreement with the negative temperature coefficient (a = dE g /dT = -4.73 9 10 -4 eV/K for Si) of the bandgap of Si. According to Tung [22], this state of BH with temperature is the result of a treated system of discrete regions or ''patches'' of low BHs embedded in a higher background uniform BH.
Studies on the devices obtained by adding different materials with PVP on various substrates such as n-Si or p-Si are available in the literature [27][28][29][30][31][52][53][54]. For example; Azizian-Kalandaragh et al. [28] fabricated Al/(PVP:Zn-TeO 2 )/p-Si heterojunction structures and examined the effect of the interlayer on the electrical and dielectric properties at room temperature. Tatarog lu et al. [54] fabricated diode with and without (Gr-PVP) and compared their electrical properties. They have experimentally proven an increase in the electrical performance of MS diode of (Gr-PVP) interfacial layer at room temperature. The value of the ideality factor (n), which determines the quality of the structures, obtained at room temperature of the two studies mentioned above was found Table 1 The extracted temperature-dependent some experimental values from the forward bias I-V characteristics for the Au/ (nanocarbon-PVP)/n-Si SD  to be much higher than the ideality factor (n) obtained in this study. The structure resistance (R i ) of the Au/(nanocarbon-PVP)/n-Si SD is a function of applied voltage (V i ), but as shown in Fig. 5, the real values of R s correspond to enough high forward while shunt resistance (R sh ) corresponds to enough low reverse voltages. R s can occur for a number of the reasons such as the ohmic contact made on the back surface of the crystal, factors such as dust and dirt that may occur between crystal and ohmic contact during or before creating the back contact, and the presence of a natural or doped interface layer between the metal and the semiconductor, the bulk resistance of the semiconductor, and the extremely non-homogeneity doping distribution doping atoms in the semiconductor [55]. R sh may be originated from a leakage oxide, leakage current paths along the interlayer, patches from the probe wire to the ground, and some defects in the junction area [55]. The semi-logarithmic I-V plots (Fig. 3) deviation from the linearity towards to higher bias voltages because of the effect of R s for each temperature and hence both the R s and R sh values were calculated as a function of temperature by utilizing Ohm's Law (R i = dV i /dI i ) at ± 3 V, respectively, and were also shown in Table 1. Additionally, Ohm's law provides quick results for the calculation of R s and R sh of MS and MIS type SDs; therefore, it was usually utilized for extraction of these two resistances values from the I-V data. In Table 1 and Fig. 5, both the value of R s and R sh are strong functions of temperature and decrease with the increasing temperature almost as exponentially.
Such decreasing behavior in the R s and R sh can be attributed to the increase in the free carrier concentrations because of decreasing of the forbidden band gap of Si and gained thermal energy [15,20,23].
The conventional Richardson plots give also more information on the spatial distribution of both activation energy (E a ) and BH or Richardson constant. Therefore, the ln(I 0 /T 2 ) vs q/kT was drawn and shown in Fig. 6. In Fig. 6, the plotted conventional Richardson/Arrhenius plot of the Au/(nanocarbon-PVP)/n-Si SD has a straight line at intermediate and high temperatures (160-340 K) but starts to deviate from linearity at with lowing temperatures (60-140 K). The E a and A* values were found as 0.172 eV and 6.77 9 10 -11 A/cm 2 K 2 for the Au/(nanocarbon-PVP)/n-Si SD by utilizing Eq. 4.
The obtained experimental value of A* is very very lower than the theoretical value (112 A/cm 2 K 2 for n-Si). The obtained value of E a is also considerably lower than the mid-gap of Si. The obtained low value of A* may be affected by lateral inhomogeneity of the BH [7,56]. These discrepancies between their experimental and theoretical values have already been reported by many researchers and are often attributed to the spatial inhomogeneity of BH and potential fluctuations involving many low BHs or patches at the M/S interface [1,2,[56][57][58][59]. In this case, electrons can easily pass over these lower BHs even at low temperatures and so leads to an increase in the ideality factor. But, at enough high temperatures, Fig. 5 The changes in R s and R sh with temperature in Au/ (nanocarbon-PVP)/n-Si SD Fig. 6 The conventional Richardson/Arrhenius plot of the Au/ (nanocarbon-PVP)/n-Si SD these charges gain enough energy to surpass the higher barriers, as a result, the apparent barrier height (U ap = U B0 ) increases with the increasing temperature [57][58][59][60].
Because the semiconductor has atoms with high doping concentrations, electrons can be tunneled from semiconductor to metal, and this process is known as a tunnel of quantum mechanics involving thermionic field and field emission (TFE, FE) CTMs [11][12][13]. Tunneling the mechanism can only be dominated at low temperatures and high doping concentrations, and in this case, n.T becomes almost constant. Besides, MS or MIS type SDs have many surface states/traps (N ss ) and dislocation between interlayer and semiconductor, current conduction may be governed via these traps and dislocation. For the tunneling type CTMs, the slope of ln(I) vs V plot is usually independent of temperature. To determine either or not to dominate the tunneling and T 0 anomaly, the theoretically (for n = 1) and experimental nkT/q vs kT/q plots were drawn and in Fig. 7. In Fig. 7, the FE and TFE may be dominated partly because the values of (n.T) are almost constant or independent from temperature.
Additionally, both the FE and TFE type CTMs have also required an alteration in the tunneling current magnitude with temperature as [3,11,13]: In Eq. 6, the m e * is the effective mass of electrons and e s is dielectric of the Si. The value of E 00 was found as 0.36 meV by using m e * * m 0 (= 9.1 9 10 -31 kg), dielectric of Si e s (= 11.8 e o ), dielectric of vacuum (8.85 9 10 -12 F/m), and N D (= 4.31 9 10 21 m -3 ) supplied by the manufacturer. This experimental value of E 00 is quite lower than the thermal energy (= kT/q) even at measured at low temperature (60 K). This theoretical value of E 00 shows that FE and TFE theories are unlike mechanism in the whole temperature range of (60-340 K). But, as can be seen in both Figs. 7 and 8, the value of E 00 was found at about 69 meV which is higher than kT/q for all measured temperatures. This is the second evidence of the existence of FE and TFE.
Mö nch and co-authors used Tung's theory [1, 2, 6] and obtained a good linear connection with U B0 and n. Thus, a significant decrease in U B0 and an increase in n with lowing temperature explained the average GD in BH at the M/S interface. Therefore, to obtain some evidence of GD of BDs, we plotted both U B0 and n and U B0 vs q/2kT of Au/ (nanocarbon-PVP)/n-Si SD and are given in Figs. 9 and 10, respectively. In Figs. 9 and 10, the eU B0 vs n and q/2kT plots have distinctive two linear regimes with different slopes. The extrapolation of the U B0 vs n plot to n = 1 was given a homogeneous BH as 1.176 eV for moderate and high temperatures (160-340 K) and 0.495 eV for low temperature (60-140 K) region, respectively.
With the increase in U B0 and the decrease n as the temperature increases, the observed linear relationship between them can be expressed by the lateral distribution of BH. In other words, it has a GD of the Fig. 7 The nkT/q vs kT/q plot of the Au/(nanocarbon-PVP)/n-Si SD Fig. 8 The n tun vs T plot of the Au/(nanocarbon-PVP)/n-Si SD far various E 00 BH over the diode area with the mean value of BH (U B0 ) and standard deviation (r s0 ) [16,[21][22][23][56][57][58][59][60]. In this case, the GD of the BH (U ap = U B0 ) and ideality factor (n = n ap ) with temperature is explained as the following relations: In Eq. 7, the temperature-dependent of r s0 is can be neglected low. Otherwise, the quantities of q 2 and q 3 are the voltage deformation coefficients of n which may be depended on temperature. Thus, the magnitudes of U B0 and r s0 were found from the intercept and slope of the U B0 vs q/2kT plot (Fig. 10) as 1.127 eV and 0.136 eV for moderate and high temperatures (160-340 K) and 0.578 eV and 0.067 eV for low temperatures (60-140 K), respectively. These magnitudes of r s0 are not small compared with U B0 and they show that a presence of the barrier in-homogeneities at M/S interface. Similarly, q 2 and q 3 values were also found from the intercept and slope of the (n -1 -1) vs q/2kT plot (Fig. 11) as 0.547 and 0.0068 eV for moderate and high temperatures, and 0.753 and 0.0021 eV for low temperatures, respectively. The observed two linear regimes both in Figs. 10 and 11 are the results of the existence of double GD of BHs in the SD area in the Au/(nanocarbon-PVP)/n-Si SD and N ss at (nanocarbon-PVP)/n-Si interface [43,[61][62][63][64][65]. Similar results on the barrier inhomogeneity and the effects of N ss , R s and interlayer on the performance electrical characteristics were also reported in the literature in recent years [43,50,[66][67][68][69][70]. Now, by utilizing the values of r so for moderatehigh (160-340 K) and low (60-140 K) temperatures regimes, the conventional Richardson or Arsenious as following [71]: In Fig. 10, the changed Richardson plot has two linear regimes with different slopes. Thus, by fitting Eq. 9, the U B0 and A * magnitudes for the Au/(nanocarbon-PVP)/n-Si SD were found to be 1.127 eV and 118.16 A/K 2 cm 2 for moderate-high temperatures and to be 0.529 and 83.35 A/K 2 cm 2 for low-temperatures, respectively. A * especially for moderate-high Fig. 9 Temperature-dependent U B0 vs n plot of the Au/ (nanocarbon-PVP)/n-Si SD Fig. 10 The U B0 vs q/2kT plot of the Au/(nanocarbon-PVP)/n-Si SBD Fig. 11 The (n -1 -1) vs q/2kT plot of the Au/(nanocarbon-PVP)/ n-Si SD temperature range is very close to its theoretical magnitude 112 A/K 2 cm 2 . As a result, the CTMs in the sample are governed by double GD of BH rather than a tunneling mechanism (Fig. 12). The mean magnitudes of U B0 extracted from Figs. 9, 10 and 13 are in good agreement with each other.
According to Card and Rhoderick [65] the energy associated with N ss can be successfully calculated from the forward I-V zone for each temperature, take account of the voltage dependence of the ideal factor (n(V)) and effective BH (U e ) utilizing the following formulas [65].
In Eq. 10, b(=dU e /dV=1-1/n(V)) is the voltage coefficient of BH used in the place of the U B0 [65,72]. Thus, the N ss vs (E c -E ss ) was extracted from Eqs. 11 and 12 as follow [39,65,73]: In Fig. 13 is an exponential growth of the N ss from mid-gap of Si towards the bottom of E c for each temperature and the mean value of them altered from the 4.9 9 10 13 eV -1 cm -2 at 60 K to 0.95 9 10 12 -eV -1 cm -2 at 340 K which are reasonable for the MPS type SD. Changes in this magnitude and their positioning with temperature can be associated with reordering and restructuring under the effects of electric field and temperature.

Conclusions
In this work, the current-voltage-temperature (I-V-T) properties of the fabricated Au/(nanocarbon-PVP)/ n-Si SDs have been examined in temperature (60-340 K) and bias voltage (± 3 V). All electrical magnitudes of them, for instance, I 0 , n, U 0 , R s , R sh and N ss have obtained a function of temperature and the changes of them with temperature become more distinctive especial with lowing temperature and moderate temperatures. The magnitude of U B0 increased from 0.173 eV to 0.837 eV, while the n value decreased from 16.60 to 2.85 with the temperature rising from 60 to 340 K. Especially, the higher value of n with lowing temperature is attributed to inhomogeneous barriers rather than the presence of the organic intermediate layer and N ss . The traditional Richardson plot also deviated from the linearity with lowing temperature (T B 140 K), and the value of A * was considerably lower than its theoretical magnitude. By utilizing the obtained values of r so from the intercept of the U B0 vs q/2kT plots, the conventional Richardson was modified. Thereafter, the slope of U B0 and A * values for Au/(nanocarbon-PVP)/n-Si SD were found and cut this graph to 1.127 eV and 118.16 A/K 2 cm 2 for the temperature range 160-340 K and 0.529 and 83.35 A/K 2 cm 2 for 60-140 K, respectively. A * magnitude is very close to the theoretical 112 A/K 2 cm 2 magnitudes, especially for the medium-high temperature range. Consequently, the CTMs in the Au/(nanocarbon-PVP)/n-Si SD are governed by double GD of BH rather than tunneling mechanism. The N ss vs (E c -E ss ) profile for each temperature was also calculated from the forward bias I-V data by taking into account voltage-dependent of n and effective BH. This mean value of them changed from the 4.9 9 10 13 eV -1cm -2 at 60 K to 0.95 9 10 12 eV -1 cm -2 at 340 K which is reasonable for the MPS type SD. Changes in this magnitude and their positioning with temperature can be associated with reordering and restructuring under the effects of electric field and temperature.