In this study, a 5th-order active-RC lowpass filter with a power-up stable DC offset cancellation (DCOC) circuit is designed. The filter achieves a 120 MHz cutoff frequency with a 4-bit programmable 0-18 dB gain. The DCOC circuit is utilized for the last stage of the filter and can compensate for a 3σ, 128 mV offset voltage to 1.2 mV in the maximum gain setting. The settling time of the DCOC circuit is approximately 50 μs. DCOC introduces a 46 kHz and 11.3 kHz lower cutoff frequencies for maximum and minimum gain settings respectively. The design is realized in the commercial ST 130 nm PD SOI process, and the main supply voltage is 1.2 V along with 1.8 V utilized in a section of DCOC. The total power consumption of the design is 21 mW with a 590 μs x 280 μs active layout area for the design.