Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs

This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis was done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.


Introduction
One of the advantages of the SOI technology is the isolation of the active part from the substrate, but some disadvantages are also presented, such as the increase in the breakdown voltage, floating body and dependency of the threshold voltage to the silicon thickness [1]. The graded-channel (GC) technology was proposed to circumvent some of those disadvantages [2]. Figure 1 shows the schematic cross section of a GC SOI nMOSFET. The graded-channel transistor has two doping concentrations in its channel, highly doped near the source with length L HD and a lightly doped close to the drain with length L LD . Some of the advantages of the GC SOI MOSFET are the increase in drain current, transconductance and voltage gain, and decreasing of the output conductance, apart from increasing the breakdown voltage, depending on the ratio L LD /L (L being the total channel length) [3].
Later a new structure where presented, the self-cascode (SC) association of transistors, formed by two transistors associated in series and tied by the gates, with the main objective of improving the analog performance [4,5]. The transistor MD limits the channel modulation effect decreasing the output conductance (g D ) and increasing the voltage gain. The transistor MS has high doping increasing the transconductance (g m ) and its cutoff frequency [4].
The asymmetric self-cascode (A-SC) increases the resistance of MD, making its threshold voltage low. The transistor MS has larger threshold voltage due to its doping concentration, therefore being responsible for increasing the threshold voltage of the overall structure. This structure has a shorter area compared to the SC device, enhanced transconductance (g m ), a reduced output conductance (g D ) and increased intrinsic voltage gain [2,4,5,6]. Figure 2 shows a cross section of an asymmetric self-cascode SOI nMOSFET.
Previous study shows that both GC and A-SC with same dimensions structures exhibit transconductance values close to those of a single transistor with reduced L, but with the reduction of the output conductance [5].
The study of gate-to-source capacitance (C GS ) and gateto-drain capacitance (C GD ) are as important as the study of the gate-to-gate capacitance (C GG ), since for analog circuit designer all the transcapacitances can affect the time factor of circuits. The gate-to-gate capacitance is the sum of C GD + C GS + C GX + C GB for the A-SC SOI, and for the GC SOI the sum of C GD + C GS + C GB [7].
The usage of both GC and A-SC devices for analog applications have already reported in the literature, mainly focusing on the voltage gain, transconductance and breakdown voltage. However, no comparison in terms of the intrinsic capacitances of these advantageous architectures has been reported so far. The device's intrinsic capacitances can greatly affect the time factor and frequency 1 3 for both analog and digital circuits. This importance does not stop at the gate-gate capacitance, it also includes the gate-to-source and gate-to-drain capacitances. Therefore, a comparative analysis between these structures can give valuable information for integrated circuit designers, seeking for MOSFETs with high analog performance.
This paper presents a comparative study of transcapacitances of FD A-SC and GC SOI MOSFETs by means of two-dimensional numerical simulations. Section 2 presents devices' structure and simulation details. Section 3 presents the analysis of each simulated capacitance. Section 4 presents the study of the C GG behavior by two-dimensional simulations. Section 5 presents the study of the electron concentration, also by two-dimensional simulations. The main conclusions are summarized in Sect. 6.

Simulated devices
The simulations of A-SC and GC SOI MOSFETs were performed using Sentaurus Device simulator [8]. The structures used has highly doped concentration of 5 × 10 16 cm −3 and lightly doped concentration of 1 × 10 15 cm −3 . The thickness of the silicon layer is 80 nm, buried and gate oxide thicknesses are 390 and 31 nm, respectively. The drain was biased at 50 and 1.5 V, and frequency has kept fixed at 1 MHz.
The lengths and ratios are shown on Table 1. Physical models considered in this simulation sets include mobility models with doping density dependency, parallel electrical field and high field saturation, as well as carrier recombination effects and bandgap narrowing. Figure 3 shows the simulated C GG capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and V DS = 50 mV. Three GC and A-SC transistors with fixed highly doped region/channel length of 0.5 µm and different total lengths are shown. Another pair of devices with lightly doped region length of 0.5 µm is also Fig. 1 Schematic cross section of a GC SOI nMOSFET. LHD and LLD stands for the channel length of the highly and lightly doped region, respectively, t oxf is the thickness of the gate oxide, t Si is the thickness of the active silicon layer, t oxb is the thickness of the BOX and S, G and D are the nodes for the source, gate and drain, respectively shown. The maximum capacitances are about the same for A-SC and GC of same dimensions, as for the minimum capacitance the A-SC presents higher values. For devices with the same L HD , which are the devices with length of 0.667, 1 and 2.5 µm, as the length ratio increases the capacitance increases, due to the increase in total gate area. The device with length of 0.625 µm has smaller total length, in which most of its channel as a lightly doped region, making the capacitance lower if compared to the longer devices. Also, for devices with longer channel length, the presence of bumps on the transition from depletion to saturation can be seen better for both devices. Figure 4 shows the simulated C GD capacitances of A-SC and GC SOI MOSFETs, presented in Fig. 3. The minimum gate-to-drain capacitance values are about the same for all devices, independent of the lengths and lengths ratios. As for the maximum capacitance, GC devices presents a higher capacitance than the A-SC devices. The maximum capacitance values for the GC devices reaches saturation at slightly later V GS , and the peak that occurs at a V GS close to the V T of MD is discrete for the A-SC, and prominent to the GC. After reaching the maximum value, the capacitance starts to decrease reflecting the change in the inversion charge density of the channel MD. As for the length ratio, the increase in the lightly doped region length, with larger inversion charge due to the longer lightly doped region, is responsible for the pronounced peak seen in the device with total length of 2.5 µm. Figure 5 shows the simulated C GS capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and V DS = 50 mV. The minimum capacitance for all devices is about the same. The maximum capacitance for the A-SC device, with L MS with the same length, the C GS are about the same, but looking closely as L MD /L ratio increases the lower the capacitance. For the GC device this behavior is opposite, as L LD /L ratio increases the higher the capacitance, and the variation of the capacitance is larger. The values of C GS from the A-SC device is smaller than the ones presented on the GC device. This shows how significant the depletion region closer to the drain is affected directly by the L MD , and since the A-SC devices has the intermediate region and its capacitance is the main component on C GG (this will be shown after on Sect. 4), C GS is lower for these devices. Figure 6 shows the simulated C GG capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and V DS = 1.5 V. The saturation occurs at later V GS , with the maximum capacitance being reached at V GS higher than the simulation as the depletion region near the drain increases, and therefore making the bumps smoother.    Figure 7 shows the simulated C GD capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and V DS = 1.5 V. With higher drain bias the variation of the capacitance on the A-SC increases, making more visible how it is higher as the length ration increases. The capacitance values of the A-SC become closer to the ones presented on the GC devices but are still lower than the GC capacitance. Figure 8 shows the simulated C GS capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and V DS = 1.5 V. For the A-SC device with higher drain bias, in saturation the variation of the capacitance is higher, making the decrease in the C GS as the length ratio increases in better seen. This is due to the increase in the C GD values due to the increase in depletion region of MD and how it affects MS. Figure 9 shows the simulated capacitances of A-SC and GC SOI MOSFETs, with L = 1 µm, L MD /L = 0.500 and V DS = 50 mV. Since both structures present the same total length, the minimum and maximum values of C GG are about the same. The presence of bumps, on the transition from depletion to saturation, on the curve C GG is perceptible on both structures. On the A-SC device, these bumps can be also seen on the C GX curve, which is the major portion of C GG , indicating the direct influence of the intermediate region on C GG . For the GC device the major portion is C GD , and also presents those bumps. Figure 10 shows the simulated capacitances of A-SC and GC SOI MOSFETs, with L = 1 µm, L MD /L = 0.500 and V DS = 1.5 V. When increasing V DS , the variation of C GG on the transition from depletion to saturation is smaller, reaching the maximum capacitance at later V GS and making the bumps almost unseen. Also, C GD and C GS saturation occurs at later V GS .

Density simulation results
To help explain the presence of the bumps, the electron density of the device with length of 1 µm and ratio of 0.500 were extracted from two-dimensional simulations for the A-SC (suppressing the intermediate region) and GC SOI MOSFETs. The V GS used have been extracted through the second derivative of C GG versus V GS and correspond to the threshold voltage of the lightly and highly doped region/ transistor of each device. The doping concentration is also presented in this graph. Figure 11 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for negative V GS and drain bias of 50 mV. For both transistors of the A-SC (MD and MS), the electron density starts in inversion, goes through depletion, and then go back to inversion. For the GC device on the highly doped region (correspondent to the MS transistor) the electron density starts in inversion and goes through depletion, when it reaches the lightly doped region the electron density changes to inversion. So, the behavior of the electron density (going from inversion to depletion than going back to inversion) on the A-SC takes places on each transistor, while the GC it happens on all the device length. This explains the reason the bump on the A-SC device is so prominent. Figure 12 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for negative V GS and drain bias of 1.5 V . When V DS is increased, the behavior of the A-SC device is similar to smaller V DS , but for the GC device it changes: it goes through inversion to depletion, not going back to inversion which indicates why there is not a presence of the second bump on the capacitance curve. Figure 13 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for positive V GS and drain bias of 50 mV. For the A-SC the same behavior from negative V GS occurs for the MS transistor, on the MD side it stays in inversion. Almost the same behavior of the A-SC device can be seen on the GC device. Figure 14 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for positive V GS and drain bias of 1.5 V . For higher V DS the behavior is like the behavior presented for negative V GS , the A-SC going though inversion-depletion-inversion on each transistor and the GC going though inversion-depletion on the whole length of the channel.

Conclusions
The maximum capacitance of C GG comparing A-SC and GC SOI MOSFETs is about the same for lower drain bias, with higher drain bias the A-SC capacitance is slightly higher than the GC capacitance. C GD and C GS are opposite on the A-SC, increasing L MD /L makes C GD higher and C GS lower, this maintain C GG about the same over the threshold voltage. The C GS and C GD capacitances for the A-SC are smaller than the ones presented on the GC device,  since the main component of C GG for the A-SC device is the capacitance between the gate and the intermediate node, C GX . The bumps presented on the C GG curve are more expressive with higher length With negative V GS applied, the operation's variation on the A-SC (going through inversion-depletion-inversion) on each transistor makes the first bump appear With positive V GS applied, the operation's variation on the A-SC (MS goes through inversion-depletion-inversion, MD stays in inversion) makes the second bump smoother For the GC device the change on the operation is done on the whole channel, making the bumps smoother.
Funding The authors have not disclosed any funding.

Declarations
Data availability Enquiries about data availability should be directed to the authors.