Research Article
Comparative of Analog Performance of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs
https://doi.org/10.21203/rs.3.rs-1995082/v1
This work is licensed under a CC BY 4.0 License
published 04 Jan, 2023
Read the published version in Journal of Computational Electronics →
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This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis were done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.
MOSFET
Asymmetric
Self-cascode
Capacitance
Analog Performance
Silicon-On-Insulator
One of the advantages of the SOI technology is the isolation of the active part from the substract, but some disadvantages are also presented such as the increase of the breakdown voltage, floating body and dependency of the threshold voltage to the silicon thickness [1]. The graded-channel (GC) technology was proposed to circumvent some of those disadvantages [2].
Figure 1 shows the schematic cross-section of a GC SOI nMOSFET. The graded-channel transistor has two doping concentrations in its channel, highly doped near the source with length LHD and a lightly doped close to the drain with length LLD. Some of the advantages of the GC SOI MOSFET are the increase of drain current, transconductance and voltage gain, and decreasing of the output conductance, apart from increasing the breakdown voltage, depending on the ratio LLD/L (L being the total channel length) [3].
Later a new structure where presented, the self-cascode (SC) association of transistors, formed by two transistors associated in series and tied by the gates, with the main objective of improving the analog performance [4][5]. The tra’nsistor MD limits the channel modulation effect decreasing the output conductance (gD) and increasing the voltage gain. The transistor MS has high doping increasing the transconductance (gm) and its cutoff frequency [4].
The asymmetric self-cascode (A-SC) increases the resistance of MD, making its threshold voltage low. The transistor MS has larger threshold voltage due to its doping concentration, therefore beeing responsible for increasing the threshold voltage of the overall structure. This structure has na shorter area compared to the SC device, enhanced transconductance (gm), a reduced output conductance (gD) and increased intrinsic voltage gain [2][5][6]. Figure 2 shows a cross-section of an asymmetric self-cascode SOI nMOSFET.
Previous study shows that both GC and A-SC with same dimensions structures exhibit transconductance values close to those of a single transistor with reduced L, but with the reduction of the output conductance [5].
The study of gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD) are as important as the study of the gate-to-gate capacitance (CGG), since for analog circuit designer all the transcapacitances can affect the time factor of circuits. The gate-to-gate capacitance is the sum of CGD+CGS+CGX+CGB for the A-SC SOI, and for the GC SOI the sum of CGD+CGS+CGB [7].
This paper presents a comparative study of transcapacitances of FD A-SC and GC SOI MOSFETs by means of two-dimensional numerical simulations. Section II presents devices structure and simulation details. Section III presents the analysis of each simulated capacitance. Section IV presents the study of the CGG behavior by two-dimensional simulations. Section V presents the study of the electron concentration, also by two-dimensional simulations. The main conclusions are summarized in Section VI.
The simulations of A-SC and GC SOI MOSFETs were performed using Sentaurus Device simulator. The structures used has highly doped concentration of 5×1016 cm-3 and lightly doped concentration of 1×1015 cm-3. The thicknesses of the silicon layer is 80 nm, buried oxide thickness is 390 nm and gate oxide thickness is 31 nm. The drain was biased at 50 mV and 1.5 V, and frequency has kept fixed at 1 MHz.
The lengths and ratios are shown on Table 1.
| L [µm] | LHD or LMS [µm] | LLD or LMD [µm] | LLD/L or LMD/L |
|---|---|---|---|
| 0.625 | 0.125 | 0.500 | 0.800 |
| 0.667 | 0.500 | 0.167 | 0.250 |
| 1.000 | 0.500 | 0.500 | 0.500 |
| 2.500 | 0.500 | 2.000 | 0.800 |
Physical models considered in this simulation sets include mobility models with doping density dependency, parallel electrical field and high field saturation, as well as carrier recombination effects and bandgap narrowing [8].
Figure 3 shows the simulated CGG capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and VDS = 50 mV. The maximum capacitances are about the same for each structure, as for the minimum capacitance the A-SC presents higher values. For devices with the same LHD, which are the devices with length of 0.667, 1 and 2.5 µm, as the length ratio increases the capacitance increases. The device with length of 0.625 µm has most of its channel as a lightly doped region, making the capacitance lower if compared to the device with same ratio (length of 2.5 µm). This show how important is the highly doped region to the capacitance values. Also, for devices with longer channel length, the presence of bumps on the transition from depletion to saturation can be seen better for both devices.
Figure 4 shows the simulated CGD capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and VDS = 50 mV. The minimum capacitance are about the same for all devices, independent of the lengths and lengths ratios. As for the maximum capacitance, GC devices presents a higher capacitance than the A-SC devices. The maximum capacitances for the GC devices reaches saturation at slightly later VGS, and the peak that occurs at a VGS close to the VT of MD is discrete for the A-SC, and prominent to the GC. After reaching the maximum value, the capacitance starts to decrease reflecting the change in the inversion charge density of the channel MD. As for the length ratio, as it increases the higher the capacitance.
Figure 5 shows the simulated CGS capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and VDS = 50 mV. The minimum capacitance for all devices are about the same. The maximum capacitance for the A-SC device, with LMS with the same length, the CGS are about the same, but looking closely as LMD/L ratio increases the lower the capacitance. For the GC device this behavior is opposite, as LLD/L ratio increases the higher the capacitance, and the variation of the capacitance is larger. The values of CGS from the A-SC device is smaller than the ones presented on the GC device. This shows how significant the depletion region closer to the drain is affected directly by the LMD, and since the A-SC devices has the intermediate region and its capacitance is the main component on CGG (this will be shown after on section IV), CGS is lower for these devices.
Figure 6 shows the simulated CGG capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and VDS = 1.5 V. The saturation occurs at later VGS, with the maximum capacitance being reached at VGS higher than the simulation as the depletion region near the drain increases, and therefore making the bumps smoother.
Figure 7 shows the simulated CGD capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and VDS = 1.5 V. With higher drain bias the variation of the capacitance on the A-SC increases, making more visible how it is higher as the length ration increases. The capacitance values of the A-SC becomes closer to the ones presented on the GC devices, but are still lower than the GC capacitance.
Figure 8 shows the simulated CGS capacitances of A-SC and GC SOI MOSFETs, with different lengths and lengths ratios and VDS = 1.5 V. For the A-SC device with higher drain bias, in saturation the variation of the capacitance is higher, making the decrease of the CGS as the length ratio increases in better seen. This is due to the increase of the CGD values due to the increase of depletion region of MD and how it affects MS.
Figure 9 shows the simulated capacitances of A-SC and GC SOI MOSFETs, with L = 1 µm, LMD/L = 0.500 and VDS = 50 mV. Since both structures present the same total length, the minimum and maximum values of CGG are about the same. The presence of bumps, on the transition from depletion to saturation, on the curve CGG is perceptible on both structures. On the A-SC device, these bumps can be also seen on the CGX curve, which is the major portion of CGG, indicating the direct influence of the intermediate region on CGG. For the GC device the major portion is CGD, and also presents those bumps.
Figure 10 shows the simulated capacitances of A-SC and GC SOI MOSFETs, with L = 1 µm, LMD/L = 0.500 and VDS = 1.5 V. When increasing VDS, the variation of CGG on the transition from depletion to saturation is smaller, reaching the maximum capacitance at later VGS and making the bumps almost unsee. Also CGD and CGS saturation occurs at later VGS.
To help explain the presence of the bumps, the electron density of the device with length of 1 µm and ratio of 0.500 were extracted from two-dimensional simulations for the A-SC (suppressing the intermediate region) and GC SOI MOSFETs. The VGS used have been extracted through the second derivative of CGG vs VGS and correspond to the threshold voltage of the lightly and highly doped region/transistor of each device. The doping concentration is also presented in this graph.
Figure 11 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for negative VGS and drain bias of 50 mV. For both transistors of the A-SC (MD and MS), the electron density starts in inversion, goes through depletion and then go back to inversion. For the GC device on the highly doped region (correspondent to the MS transistor) the electron density starts in inversion and goes through depletion, when it reaches the lightly doped region the electron density changes to inversion. So, the behavior of the electron density (going from inversion to depletion than going back to inversion) on the A-SC takes places on each transistor, while the GC it happens on all the device length. This explains the reason why the bump on the A-SC device is so prominent.
Figure 12 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for negative VGS and drain bias of 1.5 V. When VDS is increased, the behavior of the A-SC device is similar to smaller VDS, but for the GC device it changes: it goes through inversion to depletion, not going back to inversion which indicates why there is not a presence of the second bump on the capacitance curve.
Figure 13 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for positive VGS and drain bias of 50 mV. For the A-SC the same behavior from negative VGS occurs for the MS transistor, on the MD side it stays in inversion. Almost the same behavior of the A-SC device can be see on the GC device.
Figure 14 presents the electron density of an A-SC SOI MOSFET and a GC SOI MOSFET for positive VGS and drain bias of 1.5 V. For higher VDS the behavior is similar to the behavior presented for negative VGS, the A-SC going though inversion-depletion-inversion on each transistor and the GC going though inversion-depletion on the whole length of the channel.
The maximum capacitance of CGG comparing A-SC and GC SOI MOSFETs is about the same for lower drain bias, with higher drain bias the A-SC capacitance is slightly higher than the GC capacitance. CGD and CGS are opposite on the A-SC, increasing LMD/L makes CGD higher and CGS lower, this maintain CGG about the same over the threshold voltage. The CGS and CGD capacitances for the A-SC are smaller than the ones presented on the GC device, since the main component of CGG for the A-SC device is CGX.
The bumps presented on the CGG curve are more expressive with higher length. With negative VGS applied, the operation’s variation on the A-SC (going through inversion-depletion-inversion) on each transistor makes the first bump appear. With positive VGS applied, the operation’s variation on the A-SC (MS goes through inversion-depletion-inversion, MD stays in inversion) makes the second bump smoother. For the GC device the change on the operation is done on the whole channel, making the bumps smoother.
published 04 Jan, 2023
Read the published version in Journal of Computational Electronics →
Reviewers agreed at journal
05 Oct, 2022
Reviewers invited by journal
05 Oct, 2022
Editor invited by journal
29 Aug, 2022
Editor assigned by journal
26 Aug, 2022
First submitted to journal
24 Aug, 2022
You are reading this latest preprint version