MOS only nano-watt sub-bandgap voltage reference

This paper presents a nano-watt bandgap voltage reference (BGR). The self-cascode structure is provided as a proportional-to-absolute-temperature (PTAT) voltage. Due to the low slope of the PTAT voltage, a voltage divider consisting of five similar MOSFET transistors is presented. The resulting output voltage will be one-fifth of the complementary-to-absolute-temperature voltage and four-fifths of the PTAT voltage. All MOSFETs are standard CMOS transistors biased in the sub-threshold region where one of them is utilized as a diode. Post-layout simulation results using the standard 0.18 µm CMOS process show a nominal output voltage of 0.132 V. The power consumption is 12.7 nW at 0.7 V of the power supply. The average temperature coefficient (TC) is about 28.5 ppm/°C over a temperature range of 0 °C–100 °C. The proposed BGR occupies a small area of 0.00083 mm2.


Introduction
Voltage references (VRs) are an essential block of analog and mixed-signal circuits and systems. Demand for lowpower systems increases dramatically, and VRs are no exception. Conventional BGRs, which operate at a relatively high supply voltage, use V BE of bipolar junction transistors (BJT) to generate the CTAT and the PTAT voltages. Then, a proper combination of the CTAT and the PTAT voltages is obtained by a ratio of resistors [1]. Low-power BGR requires large resistors. Therefore, different resistor-less approaches have recently been presented to propose low-power, lowvoltage MOS BGRs [2][3][4][5]. In [2], a nano-watt BGR utilizes self-cascode PTAT voltage which compensates the negative TC of V BE . However, because the TC of self-cascode PTAT voltage is very low, five cascaded stages are utilized, resulting in a large area and power consumption. Based on the voltage difference of two nMOS transistors, a self-cascode PTAT voltage is generated and combined with CTAT voltage while the presented nano-Watt BGR is still applying BJT and resistors [6]. A MOS-only nano-Watt BGR presented in [7] uses three self-cascode PTAT stages while V TH is applied as the CTAT voltage. However, It is more sensitive to process variation because of V TH variation.
Different approaches like mutual compensation of the thermal voltage (V T ) and pMOS threshold voltage (V THP ), V T and V BE , V THN, and V THP have also been presented [8][9][10][11]. This paper presents a nano-Watt BGR based on using only one self-cascode PTAT voltage stage. V D -V GS is applied as a CTAT voltage, where V D is the anode to cathode voltage of a diode implemented by a pMOS transistor. The proper weighting of the self cascode PTAT voltage and the CTAT voltage is done by five similar pMOS transistors, which are biased in the sub-threshold region. In fact, MOS-FETs act as large resistors which make a voltage divider. This paper is organized as follows. Section II presents the proposed circuit and design considerations. The simulation results are presented in the third section.

Proposed structure
The simplified circuit of the proposed BGR is presented in Fig. 1 Therefore, the high slope of the negative term (V N ) is balanced, and zero TC could be obtained by appropriately sizing the aspect ratio of M 1 to M 3 and R * .
The CTAT voltage could be supplied directly from the anode of D 1 (V D ), but due to the more negative slope of this node, more dividing resistors were needed, which would lead to an increase in the chip area. As can be explained in the next section, D 1 , M 3 , R * , and a current mirror form a self-bias current circuit. Figure 2 shows the proposed BGR circuit, consisting of the PTAT circuit, the CTAT circuit, current mirrors, and the voltage divider. All MOSFETs are biased in the subthreshold (1)

Circuit description
region to reduce power consumption. The gate, source, and drain of M 14 form the anode of the diode, and the bulk of M 14 provides the cathode [12]. M 3 , M 4 , M 5 , M 6 , and M 14 constitute the bias circuit. Considering the voltage across the diode is about 500 millivolts, M 3 and M 4 have been biased in the sub-threshold region. Both N and D nodes can be applied as the CTAT voltage, but the slope at the N point is less; therefore, the N node is used as the CTAT voltage. M 8 to M 12 act as large resistors. These transistors have the same size and type, completely similar. Therefore act as voltage dividers despite the non-linearity of their I-V characteristic. Because the V GS of these transistors is a small value, the current passing through them is much lower than the drain current of M 2 and M 3 . It is around 0.36 nA at room temperature, while I d2 and I d3 are greater than 14.35 nA. Thus, the loading effect of M 8 to M 12 on V N and V P can be ignored. In FS and FF corners or at high temperatures, where the threshold voltage of pMOS transistors is relatively small, the current pass through M 8 to M 12 will be increased, which can cause a slight loading effect on the P node. M 13 is utilized to alleviate this effect where its drain current is 0.28 nA at room temperature and TT corner. In FF and FS corners or high temperatures, the drain current of M 13 is also increased, which can compensate for the problem relatively. Applying M 13 also decreases the loading effect in the TT corner because the load effect current is reduced to (I D12 -I D13 ). At room temperature and TT corner, I D12 -I D13 ≈ 0.8 nA is a very small value compared to I D2 .

Self-cascode PTAT voltage
Ignoring the body effect of M 2 and the loading effect, we can write: μ is electron carrier mobility, C OX is gate-oxide capacitance density, m is the subthreshold slope factor, V T is the thermal voltage, and V THN is nMOS transistor threshold voltage [13]. Thus, assuming that m 1 ≈ m 2 = m, V P is obtained from Eq. 2.
It is important to mention that Eq. 2 is valid on the condition that V DS1 /V T & V DS2 /V T are great enough. Figure 3 shows the voltage at node P over a temperature range of (2)

CTAT voltage
The CTAT voltage is obtained from the bias circuit to reduce power dissipation and chip area. As can be explained in [12], M 14 acts as a diode. In fact, we have two parallel diodes, drain to bulk and source to bulk, where the bulk of M 14 is a cathode of the diode. It should be noted that the forward voltage drop of a diode is significantly less process dependent in comparison to V GS . This is the reason for utilizing a diode in the CTAT circuit. Since V Diode = V GS3 + V SG4 , transistors M 3 and M 4 work in the sub-threshold region. Therefore, if V DS3,4 > 0.1 V, the I D3 can be obtained from the following equation.
M 5 and M 6 are similar transistors. Thus, I Diode = I D5 = I D6 = I D3 is considered. I SD is the equivalent saturation current of the presented two parallel diodes, drain to bulk and source to bulk. The voltage at node N can be driven as: Thus, the negative TC term is obtained from V N instead of V D . Figure 4 shows the voltage of nodes D and N over a temperature range of 0 °C to 100 °C. As can be seen, slopes are about −2.5 mV/°C and−0.95 mV/°C, respectively, at the D node and N node.

Vref
Finally, V ref is obtained from the proper weighting of V P and V N . Considering the similarity of transistors M 8 to M 12 and the negligible current passing through them compared to the I D1 to I D4 , the voltage difference between node N and node P, (V N -V P ) is equally distributed among the drain-source voltage of M 8 to M 12 . Therefore, the output voltage is obtained from Eq. 1. As observed in Eq. 1, zero TC is obtained in a condition that |ΔV N / ΔT|= 4 | ΔV P / ΔT|. The size of transistors M 1 to M 4 is chosen in such a way that this condition is satisfied.

Simulation Results
Post-layout simulation is performed with the set of 0.18 µm CMOS technology. All presented results are achieved by post-layout simulations. The layout of the proposed BGR including guard rings is shown in Fig. 5.
It occupies approximately 29.9 μm × 27.8 μm (831.2 μm 2 ) of silicon area. The proposed BGR works with 0.7 V to 1.8 V of power supply. The power consumption is 12.7 nW at room temperature and 0.7 V of V dd . The transistor sizes are summarized in Table 1.      Power supply rejection ripple (PSRR) is obtained as -47.6 dB, -58.1 dB, and -59.2 dB at 0.7 V, 1 V, and 1.8 V of V dd , respectively, as shown in Fig. 9a. As can be seen, the cutoff frequency of PSRR is about 704 Hz at V dd = 1 V. Also, the PSRR derived from pre-layout and post-layout simulation are compared in Fig. 9b while V dd = 1 V. As can be seen, parasitic capacitors slightly degrade the PSRR value at high frequencies.
It should be noted that the pre-layout and post-layout simulation results for other graphs are very close and almost equivalent. This is because the parasitic capacitors extracted from the layout do not affect the DC operation of the circuit and parasitic resistors have no significant effects in circuits with nano amper current of operation.
The proposed BGR works without the additional startup circuit. Leakage current from drain to bulk diode of wide width transistor M 3, drives M 6 , M 7, and M 14, and start-up the circuit. The performance of the proposed BGR in the initial moments is evaluated by applying a very slow ramp function with a slope of 0.01 V/ms from 0 to 1 V as a power supply. The plot of V ref versus time is shown in Fig. 10. As observed, the proposed BGR operates correctly with the slow rising of V dd .
Process variations and mismatches are considered using Monte Carlo simulation. Figure 11a and Fig. 11b show the Monte Carlo simulation results of 1000 runs for TC and V ref with V dd = 1 V, respectively. As can be seen, the mean (µ) and standard deviation (σ) of the TC, without using a trimming circuit, are 28.51 ppm/°C and 17.56 ppm/°C, respectively. Also, µ = 131.95 mV and σ = 1.7 mV are obtained for V ref . Figure 11c shows the Monte Carlo simulation results for the PSRR value with µ = -57.8 dB and σ = 0.57 dB at V dd = 1 V. Table 2 summarizes the proposed voltage reference characteristics compared with other similar works. Gate-Source voltage of an nMOS biased in the sub-threshold region is utilized as a CTAT voltage in [5] and [7], while |V BE | provides the CTAT voltage in [6] and [11]. The generation of the PTAT voltage in all references except [11] is utilized by self-cascode PTAT, although they have used several stages to increase the slope. As can be seen, the proposed BGR occupies a small area at 12.7 nW of power consumption compared to other works. It should be noted that the active area of ref [7] is reported without providing guard rings.

Conclusion
This paper proposes a nano-watt voltage reference using standard CMOS transistors biased in the sub-threshold region. The presented BGR works based on properly weighting the slow slope self-cascode PTAT voltage and the   Funding The author declares that there is no specific grant from any funding agency for this research in the public, commercial, or not-forprofit sectors.
Data availability All data needed to evaluate the conclusions in the study are included in this published article.

Conflict of interest
The author declares that he has no known competing financial interests, conflict interests, or personal relationships that could have appeared to influence the work reported in this paper.