Design and simulation of reconfigurable optical logic gates for integrated optical circuits

The proposed work presents design and simulation of a new reconfigurable optical logic AND, NOT and NOR gate constructed in a two dimensional (2D) photonic crystals (PhCs). Due to many advantages like high speed, fast response, high bit rate and compact size these optical gates find applications in optical devices, communications and optical sensors for next generation optical systems. The proposed gate structures can be used in realization of all optical devices used in photonic integrated optical circuits. These optical logic gates are constructed in 6 µm * 6 µm in 2D PhCs square lattice structure with a lattice constant a = 0.648 µm. All the gates are realized by creating structural disorders in the cross-waveguide geometries of 2D PhCs. The plane wave expansion (PWE) is utilised to get the complete band gap and required band of the waveguide. Finite difference time domain (FDTD) technique is utilised to investigate the performance of these gates. The several performance parameters are examined using this structure and observed that proposed structure has reduced size, fast response time, better contrast ratio against the existing designs and high bit rates of 1.88 Tbit/s and 1.55 Tbit/s for NOT and NOR gates respectively. The amplitude of the optical signal larger than 0.5 arbitrary units (a.u.) and less than 0.1 (a.u.) at output are considered as logic ‘1’ and ‘0’ respectively. The gates are implemented in third optical window at the wavelength of 1.55 µm. RSoft FullWAVE simulator is used to perform simulation.


Introduction
The rapid increase in communication traffic has created the demand for wide bandwidth and fast computing speed. Optical signal processing using all optical devices will overcome the speed limitations imposed by electronic devices (Haq Shaik and Rangaswamy 2016;Pirzadi et al. 2016;Ansari et al. 2021), increases data-rate capacity and deceases the power consumption as it eliminates optical-to-electrical conversion (Mohebbi et al. 2018;Haq Shaik and Rangaswamy 2018;Soma et al. 2019). These properties of the optical devices make them as outstanding for data processing and high-speed computing in optical communication. Logic gates are the fundamental devices used to realize complex logic functions.
Logic gates by using Photonic Crystal platform can be constructed by employing three criteria (Mohebzadeh-Bahabady and Olyaee 2019): interference structures, nonlinear structures and self-collimation structures. Nonlinear structure is designed by inserting nonlinear materials in the PhC structure. Optical logic devices designed by using this principle have high power requirements and low response time. Logic operation in self-collimation devices are realized by using self-collimated reflected and transmitted beams but has large size. By creating photonic band gap (PBG) in a periodically modulated dielectric media we can confine and control the propagation of light (Rani et al. 2015;Olyaee et al. 2018;Taylor et al. 2017;Sonth et al. 2018Sonth et al. , 2021a. PhCs nanocavity is formed by creating line defect in the structure through which light with specific wavelength is made to propagate (Ghadrdan and Mansouri-Birjandi 2013;Saidani et al. 2015;Achary 2015;Mahesh et al. 2018;Sonth et al. 2020;D'souza and Mathew 2016).
Many multifunctional optical logic gates (Geerthana et al. 2022;Sonth et al. 2021b;Rezaei et al. 2020;Ghadi 2020;Sankar Rao et al. 2020;Anguluri et al. 2021;Charles et al. 2022) can be realized by using photonic crystal nanocavity. There are various approaches used for designing the structures of these logic gates: one of the approaches is they can be constructed using Semiconductor Optical Amplifier (SOA) (Singh et al. 2013) and Multimode Interferometer (MMI) (Tang et al. 2014) but it consumes more power and requires large space. Optical amplifiers, directional couplers and phase modulators can be used to build the electro-optical gates (Lin et al. 2022). Basic gates can be designed and simulated by using nanoplasmonic structure, where plasmonic waveguides can be coupled to ring and Kerr resonators (Danaie and Kaatuzian 2012;Ghadi and Darzi 2023) and Mach-Zehnder Interferometer (MZI) structures can be used to realize the multiple operation of basic logic gates (Kumar et al. 2014Heydarian et al. 2022). This design is realised on 2D-PhC of rods-in-air structure with infinite rod height which needs high pump power. Many lattice structures like triangular (Mondal et al. 2022), ring, disk, square, elliptical and rectangular can be used to construct PhC structures. Plasmonic structures are the new approach for designing of basic logic gates using plasmonic waveguides (Abdulnabi and Abbas 2019a; Choudhary and Kumar 2021), combinational circuits based on nano-ring insulator and metal-insulator plasmonic waveguide (Abdulnabi and Abbas 2019b) and multiplexers on a based on plasmonic multilayer structure (Abdulnabi and Abbas 2022) used in Optical integrated circuits. By using photonic crystal which can be used to construct many devices operating with several wavelengths, integrated on a single chip.
This proposed work presents the designing and simulation of NOT, AND and NOR logic gates using 2-D PhC. Proposed structure creates a square lattice structures with Si rods in the air to guide the light in one mode in a very broad wavelength region. The working principle of these gates is on either destructive or constructive interference occurring between input and control signals applied at the input and control port of the waveguide (Abdulnabi and Abbas 2019a). The performance of these gates is achieved by the criteria: contrast ratio, response time and bit rate.
The rest of the paper is ordered as follows: Sect. 2 presents the proposed structural design with detailed description. The Sect. 3 discusses fundamental principle of the gate structure; the Sect. 4 discusses the detailed results of this optical logic gates and followed by conclusion in the Sect. 5.

Structural design
The presented optical logic gates structure is designed in 2D PhCs using square lattice because of its simple geometry, it allows for easy confinement of light as shown in Fig. 1a. The structure consists of 13 Si rods in X and Z direction in the air. The refractive indexes of Si and air, n = 3.40 and n = 1 respectively. Two line defects are created in both directions to form a cross waveguide in the structure.
The dispersion diagram of the proposed structure is shown in Fig. 1b gives information about TE band Gap. If a linear defect (as the waveguide) is created in the PhC, these frequencies can be transmitted from the waveguide because they see the PhC network on both sides of the defect and do not have the ability to propagate it. PWE is utilized to obtain the photonic band gap for this structure. Blue lines present the Transverse Electric (TE) modes. Using photonic band gap we have calculated a normalized frequency of single-mode frequency which exists in the range from (a/λ) = 0.36 to 0.48. The wavelength of the light which is to be launched into the structure is found by the set of frequency signal which falls in the photonic band gap and corresponding wavelength ranges from 1.34 to 1.79 µm. The proposed devices are operated at 1550 nm of operating wavelength which falls in the initial band gap. The lattice constant 'a' is 0.648 µm and Si rod radius 'r' is 0.19a is the perfect size for light to propagate in the proposed structure. The overall size of this structure is only 6 × 6 μm 2 .

Working principle of all optical logic gates
Port A, B, C and D are the four ports used in the structure to apply the input and get output. Light input is made to propagate from port A, B, C and output is obtained at port Y. Port A is used as reference input or control input which provides the output power even if the input is not applied and port B and port C is used as input ports of logic gates. Optical signal with operating wavelength of λ = 1.55 µm is applied at inputs. Cross waveguides in the structure guide the light and hence control the interference effect of light beams propagating through them. Working principle of all the logic gates can be acquired by referring to the wave optic theory, constructive interference of light occurs when a phase shift among two optical inputs is 2kπ and destructive interference occurs when a phase change among two optical inputs signal is (2 k + 1)π (where k = 0, 1, 2,…). No optical signal is viewed as logic '0' input and optical signal as logic '1' input.
In few cases like NOT gates when the input light signal is not given, output is supposed to be logic. It is not possible to generate output light signal with no light signal at the input, so an extra input light signal called control signal is introduced which produces output light signal (logic 1) even when input light signal is not existing. In these structure powers of input is same as that of control input. Depending on type of gate we want to analyze, input and control signal is given to different inputs A, B, C.

Simulation results
The operation of the proposed gate structure is realized after simulating it by utilising FDTD technique and RSoft FullWAVE simulators. Performance parameters are analyzed by simulating the proposed structure in TE mode. The optical signal amplitude at the output will decide whether the output is logic 1 or logic 0. Intensity of the optical signal larger than 0.5 Pin is considered as logic '1' and < 0.1 Pin is considered as logic '0'. The fraction of ON power level and OFF power level is called contrast ratio for the logic gate.
Contrast ratio is determined (Abdulnabi and Abbas 2022) by using the Eq. 1.
where P out /ON represents the power levels for '1' output and P out /OFF is the power levels for '0' output. The contrast ratio for the NOT gate of our structure is 8.64 dB.
Operating bit rate is obtained by using response time. Response time is the time required for the output to reach 90% of its maximum output value from the beginning of the input which causes the output to change. The response time in the proposed work is determined from the transient responses. An average optical power at the output port is noticed with respect to time. The total time is the addition of delay time (t 1 ) and rise time (t 2 ). Response time is twice 2t 2 and bit rate is determined by taking the inverse of response time.

Results of NOT gate
To realize logic NOT gate, a high control signal is always sent at port A, and input is applied at ports B, port C is not used in this gate. When light signal is not applied to B input (B = 0), then input applied at control port couples with cavity and gives output at port Y. The output port obtains a power of Y = 0.659 which is considered as logic 1 (ON state). When light input is given at the port B (B = 1), then input given at control input A and B interfere destructively and gives the output at the port Y = 0.09 a.u. which is almost logic zero (OFF state).The electrical field intensity for both the input values are shown in Fig. 2. Figure 3 presents the simulation results of NOT gate. When B = 0, output at the Y port is HIGH power and will be 66% of the applied input. When B = 1 output at the Y port is LOW power and will be 10% of the applied input. The signal amplitude larger than 0.5 arbitrary units (a.u.), 50% of the input and < 0.1 (a.u.), 10% of the input are considered as logic '1' and '0' respectively. So, contrast ratio = 10log 0.659/0.09 = 8.6 dB and the power level of NOT gate reaches 0.659 a.u. and 0.09 a.u. when cT is 80 µs and 50 µs respectively.

Results of AND gate
The working principle of AND gate is achieved by making a Gaussian input light signal to propagate through ports B and C. Output is observed at port Y. Port A is not used in this gate. When both the input B&C is equal to zero there is no output. The electrical field distribution for '01', '10' & '11' combination of input is shown in Fig. 4.
The transient response of the proposed work for different combination of input is shown in Fig. 5. When either of B and C input is equal to zero, both the inputs interfere destructively and gives the power at the output port of around 12% of the applied input Y = 0.12 a.u. (OFF state). With both A and B equal to 1, both the inputs interfere constructively and gives 70% of the applied input at the output port Y = 0.7 a.u. which is considered as logic 1 (ON state). The contrast ratio for AND gate for '11' and'01,'10' combination is 7.5 dB and all other performance parameters are listed in the Table 1.

Results of NOR gate
To neither realize the operation of NOR gate control signal is given A port and input is applied at B and C port. Figure 6 shows the electrical field intensity for all combination of input. When both the inputs B & C is equal to zero, input applied at port A produces a transient response of around 68% of input at the output port Y = 0.68 and it is considered as logic 1 output. When either B or C is equal to logic 1, destructive interference takes place between B or C and produces a transient response of around 18% of input at the output port Y = 0.18 a.u which is to be considered as logic 0 output. When both B & C inputs are logic 1, transient response is around 18% of input at the output port Y = 0.18 a.u which is to be considered as logic 0. The transient response for all the combination of input is shown in Fig. 7. Table 1 gives the ideal output and actual output for the different combination of input for NOT gate, AND gate and NOR gate. The contrast ratio is 5.7 dB, 7.78 dB and 8.64 dB in case of NOR gate, AND gate and NOT gate respectively. Other performance parameters like response time and Bit rate is also calculated for the mentioned gate and reflected in the table.
We have compared the performance of our proposed structure with other logic gate's structure mentioned in the Table 2 w.r.t. contrast ratio, size, response time and

Conclusion
The proposed work focuses on design and simulation of various types of optical logic NOT, AND and NOR by using 2D PhCs cross waveguide. The performance of the logic gate structure is examined by changing Si rod radius in the cross waveguide and by changing the phase of the input signal. This structure can also be used to construct and analyze the performance of OR and NAND gates. Depending on type of gate we want to analyze input and control signal is given to different inputs and output is measured at the output port (Y). Size of the proposed structure is only 6 × 6 μm 2 smaller than previous works, simple and clear operating principle with high bit rate of 1.88 Tbit/s and 1.55 Tbit/s for NOT and NOR gate respectively. Comparative result analysis of the proposed design with previous research work is given in Table 2. The proposed structure gives better contrast ratio with less geometry area and little compensating the response time. We used RSOFT FullWAVE simulator to realize all logic gates operation. This structure can be used for future integrated photonic circuits.