In this work, a GaN transistor based two-stage Class-AB/J PA has been designed and simulated at an operating frequency of 3.5GHz (i.e., sub-6GHz). As the selection of operating frequency for proposed PA is also an important consideration, various frequency bands such as LTE & 5G new radio (NR) [24]- [26] are analysed for appropriate selection of proposed PA’s operating frequency and BW. Based on the analysis, a new sub-6 GHz frequency band with a centre frequency of 3.5GHz, called Citizen Broadband Radio Service (CBRS) [27] will be the appropriate choice for 5G wireless communications of AMI in a smart grid. Therefore, the proposed PA initially designed to operate at 3.5GHz centre frequency. The simulations of this PA were performed with A 10W GaN transistor model (CGH40010F) from CREE using ADS EDA tool. The main purpose of choosing a two-stage PA topology is to get desired power output by feeding it with lower input power. Among class-A, B, AB and C modes that are often used for the driver stage design of two-stage PA, in this work class AB is chosen due to its low distortion compared to other modes. The proposed two-stage PA design methodology is illustrated using the flowchart shown in Fig. 1, and its stepwise procedure is explained in detail as follows.

As an initial step of the PA design, a GaN transistor is chosen for this work, because of its high output power density compared to the GaAs, which makes them withstand high operational voltage [28] & [29], and they can provide higher efficiency over wider BW. Among different GaN transistor large-signal models, a Cree’s CGH40010F model transistor from Wolf speed is chosen as its features [30] can provide the desired design specifications proposed two-stage PA. According to S.C. Cripps [16], in Class-J mode by presenting a complex impedance and a pure reactive impedance as expressed by equations (1) & (2) as fundamental and second harmonic loads respectively to the selected transistor, a harmonic boost with a phase shift in the intrinsic drain voltage (VDS) of the transistor can be observed, that reduces the overlap with the drain current (ID),which represents the main feature of the Class- J mode of operation

$$Zf0=\frac{\left({V}_{DD}-{V}_{th}\right)\left(1+j\alpha \right)}{Imax/2}={R}_{opt}+j\alpha {R}_{opt}$$

1

$${Z}_{2}f0=-\frac{\left({V}_{DD}-{V}_{th}\right)j\alpha }{\begin{array}{c}2\left(\frac{{I}_{max}}{3\pi }\right)\end{array}} =-\frac{j3\pi }{8}\alpha {R}_{opt}$$

2

where the optimum resistance can be expressed as show in Eq. (3)

\(R\) opt \(=\) 2(\({V}_{DD}-{V}_{th}\))/Imax (3)

Therefore, after selecting the transistor, the load-line analysis of power stage was performed to obtain the class-J mode’s target reference impedances. Based on this analysis, the selected transistor’s drain is biased with a DC voltage of 28V and gate is biased with ≅ -3V (i.e., almost the threshold voltage).The theoretical drain voltage of the transistor can be expressed as shown in Eq. (4)

$${V}_{J}\left(\theta \right)={V}_{dc}(1+sin\theta )(1+\alpha cos\theta )$$

4

The “Alpha” factor (α) as shown in Eq. (4) can be varied over a range from − 1to1. Because, each drain voltage waveforms for different values of *α* when combine with half rectified current it results in same theoretical efficiency causes the class-J mode to expand its BW. Therefore, when (α) is moved from “0” (i.e., class-B mode) to “1”on the slider, the drain voltage and current waveforms which resembles Class-J operation mode can be noticed as shown in Fig. 2 and corresponding load-line based target reference optimum impedances (ZS and ZL) are represented on a smith chart as shown in Fig. 3.

Similar to the power stage, from the load line analysis of the driver stage the drain is biased with voltage = 28V, and the gate is biased with voltage = -2.7 V(i.e., class-AB mode).For corresponding biasing point the target reference impedances for the driver stage are obtained from the device datasheet as ZS =3.18-j*13.3 and ZL=14.6 + j*7.45.

Once the power stage (Class-J) and driver (Class-AB) stage transistors are biased, the stability analysis was performed for a frequency range of (3–4) GHz corresponding to their biasing points and a stabilization resistor is connected in series with transistor’s gate terminal to make Rollet stability factor (K) > 1,which ensures the transistor’s unconditionally stability. After ensuring the unconditional stability of the transistor to obtain the it’s optimum input and output impedances (ZS and ZL) corresponding to the maximum output power and PAE for both driver and power stages of the PA, load-pull simulations were performed on stabilized transistors by taking the target impedances obtained from the load line analysis as reference impedances using 1-Tone load pull instrument of ADS EDA tool as shown in Fig. 4.

The optimum impedances (ZS and ZL) corresponding to the Max PAE that are obtained from the LOADPULL simulations are validated by presenting them to the transistor’s terminals instead of 50 Ω terminations for both driver (class-AB) and power (Class-J) stages with respective biasing voltages and input powers at 3.5 GHz input RF frequency.

The next important step after validation of their optimum impedances (ZS and ZL) is, the design of appropriate Matching Networks ( M.Ns). Initially, the driver and power stage transistors are represented as “Z2P_Eqn” blocks and their optimum impedances (ZS and ZL) are represented as Z [1, 1] and Z [2, 2] of Z2P_Eqn blocks by ignoring the Z [1, 2] and Z [2, 1] (i.e., transfer impedances). Because the M.Ns will be designed to match only these Z [1, 1] and Z [2, 2] ) of driver and power stage transistors with each other and also with the corresponding source and load terminations. As the proposed PA is of a two-stage structure, we need to design 3 M.Ns termed as input, output and interstage. Generally, these M.Ns are designed with passive elements like capacitors and spiral inductors, but they are bulky with low Q factor and fixed inductance value. In addition, such spiral inductors are incompatible with low-cost CMOS process for integration. This issue can be resolved by replacing passive lumped elements of the PA with the active elements such as active inductors, Mos capacitors and active resistors to make it feasible for integration as proposed in our previous work [31]. Therefore, in this work the actual idea is to replace the passive lumped inductors of M.Ns with “tunable Active inductors “as shown in Fig. 5, once the PA design with lumped element-based M.Ns is validated.

So, initially 3 lumped element-based M.Ns such as L-type ,T-type and π-type were designed using their general design procedure for input, interstage and output of the proposed two-stage PA respectively to operate around 500MHz BW with centre frequency of 3.5GHz (i.e., SUB 6 GHz frequency) using ADS EDA tool as shown in Fig. 6.

Now, these designed M.Ns are validated by placing them at the appropriate places of proposed two-stage PA with the 50 Ω source and load terminations, as shown in Fig. 7.As the GaN transistor is used as the active device in the class-J power stage, second harmonic impedance condition is satisfied by the transistor’s parasitic drain source capacitance (Cds) and C3 of π-type OMN.