Design of Multistage Class-AB/J Power Amplifier for 5G Smart grid’s Advanced Metering Infrastructure Applications

doi:10.21203/rs.3.rs-2131062/v1

Download PDF

Article

Design of Multistage Class-AB/J Power Amplifier for 5G Smart grid’s Advanced Metering Infrastructure Applications

https://doi.org/10.21203/rs.3.rs-2131062/v1

This work is licensed under a CC BY 4.0 License

Version 1

posted

You are reading this latest preprint version

The wireless communication networks for Advanced Metering Infrastructure (AMI) / smart metering applications of a smart grid are in need of emerging 5G technology for providing a significant enhancement in bandwidth (BW) to support a large amount of data transmission between the Meter data management system (MDMS) of operation centre and smart meters efficiently. The entire wireless communication network’s BW and efficiency mainly depend on its Power Amplifier (PA). The design of PA that can provide high efficiency with linearity over a wide BW is essential to meet the 5G wireless communication network requirements of AMI / smart metering applications. This paper presents the design methodology of a two-stage PA that operates at a 3.5 GHz centre frequency by utilizing the CGH40010F model GaN transistor. This PA employs a Class-J mode for the power stage that will be driven by a Class-AB mode to achieve high efficiency with improved power gain over desired BW. The matching Networks(M.Ns) of the proposed two-stage PA are designed with the idea to replace its passive lumped inductors with active inductors, based on the desired optimum impedance values obtained from the load-pull techniques utilizing the ADS EDA tool. The proposed two-stage PA delivers a power output of 41dBm with 21 dB of power gain over a BW around 400 MHz, a maximum Power Added Efficiency (PAE ) of 53% and maximum drain efficiency (D.E) of 54% with a small signal gain of 27dB at 3.5GHz using 28V power supply into 50 Ω load.

smart grid

Power amplifier

3.5GHz

matching networks

With the revolution in wireless communication technology, the deployment of 5G technology has been initiated worldwide. Along with the “mobile communication sector ” there is a significant need for emerging 5G technology [1] in the “power sector” particularly for smart grid wireless communications due to the tremendous increase in the amount of data to be transmitted. Compare to the conventional power grid, the Smart grid integrates the power grid and communication technologies [2] & [3] that provide bidirectional communications to transfer the data for more reliable and efficient transmission and distribution of electricity. Among various Smart grid applications, the Advanced Metering Infrastructure (AMI)/ smart metering application [4] plays a major role, as it enables two-way communication for transmitting a large amount of data between the MDMS of the operation centre and smart meters to provide a bridge between utilities and consumers. Traditional centralized communication architecture used for AMI may cause congestion or loss of data as it cannot provide the required data rates due to the rapid increase in the smart meters count and their frequent readings. To overcome these practical limitations, a distributed architecture was proposed by J. Zhou [5], in which the data from the smart meters will be collected using data concentrators and then transferred to the MDMS of distributed Operation centre [6] making smart grid communications more efficient and cost-effective with an appropriate communication technology. The smart grid communication requirements particularly for AMI / smart metering applications has been reviewed in [7] & [8]. At present, these distributed operation centres are utilizing (3G/4G) wireless communication technologies to communicate with data concentrators, which can be replaced by emerging 5G technology to provide the reliability, along with the desired BW to support data transfer speed in the AMI of the smart grid. Two key considerations while implementing the 5G wireless communication network in AMI / smart metering applications are its energy consumption and BW. It is well known that the PA of a wireless communication network decides its overall energy consumption and BW. Various linear PA modes like class-A,B,AB with less efficiency and switching PAs like class- E, F that delivers high efficiency with lower linearity [9–15] reveal that they are restricted to narrow BW and will not be suitable for wideband applications. Therefore, this paper’s main contribution involves in the design of a two-stage PA that is suitable for 5G wireless communication networks used in AMI of the smart grid and its simulations were performed using the ADS EDA tool. The remaining portion of the paper is organized with the following sections.Section-2 describes the suitability of existing class-J PAs. Section-3 explains the proposed two-stage PA’s design methodology in detail using a flow chart. The results of simulated two-stage PA and its comparison with other similar PA designs is discussed in Section-4. Based on the simulation results obtained, the paper's conclusion is summarized in section-5.

Among various modes of PAs, a class-J PA introduced by Steve Crips [16] has proved its potential in achieving good efficiency over a wide BW along with the linearity. Various class-J PA designs were reviewed and analysed to check its suitability for emerging 5G smart grid’s AMI applications. A broadband class-J PA’s design methodology was presented in [17] achieved good linearity and high efficiency over extensive BW. A class-J PA that was designed based on GaN technology by considering OMN element losses was presented in [18],but compare to discrete type PAs its power output and efficiency are low due to low Q and limitations of the device technology. A CMOS technology-based class-J PA, whose design equations were modified based on effect of threshold voltage to analyse the second harmonic losses, is presented in [19]. However, due to low breakdown voltage limitation, CMOS-staked FET design must be used for PA design. The Class-J PAs presented in [20] and [21] demonstrated the improvement in power output and drain efficiency with the realization of proper half rectified sin waveforms at the transistor gate. Although these methods are useful, this PA's design and implementation is complicated due to the need for additional circuitry for higher-order filters. An active power injection method at the second harmonic to improve the performance of Class-J PA was proposed in [22], but the design becomes complicated due to filtering, doubling circuits and also reduces the feasibility of integration due to increased chip area. A CMOS class-J PA designed at MM wave frequency of 28GHz using 2-stage structure in [23] achieves good efficiency over enhanced BW and reveals its suitability for wideband 5G wireless communication applications.

Based on the review and analysis of different Class-J PAs, it can be noticed that this PA can be able to provide a possible solution for efficiency BW and linearity trade-off with the design of proper M.Ns. Therefore, this work a two-stage PA is proposed with a class-J mode power stage driven by a Class-AB mode gain stage to achieve the desired performance metrics that satisfies the 5G wireless communication network’s requirements used in AMI of the smart grid.

In this work, a GaN transistor based two-stage Class-AB/J PA has been designed and simulated at an operating frequency of 3.5GHz (i.e., sub-6GHz). As the selection of operating frequency for proposed PA is also an important consideration, various frequency bands such as LTE & 5G new radio (NR) [24]- [26] are analysed for appropriate selection of proposed PA’s operating frequency and BW. Based on the analysis, a new sub-6 GHz frequency band with a centre frequency of 3.5GHz, called Citizen Broadband Radio Service (CBRS) [27] will be the appropriate choice for 5G wireless communications of AMI in a smart grid. Therefore, the proposed PA initially designed to operate at 3.5GHz centre frequency. The simulations of this PA were performed with A 10W GaN transistor model (CGH40010F) from CREE using ADS EDA tool. The main purpose of choosing a two-stage PA topology is to get desired power output by feeding it with lower input power. Among class-A, B, AB and C modes that are often used for the driver stage design of two-stage PA, in this work class AB is chosen due to its low distortion compared to other modes. The proposed two-stage PA design methodology is illustrated using the flowchart shown in Fig. 1, and its stepwise procedure is explained in detail as follows.

As an initial step of the PA design, a GaN transistor is chosen for this work, because of its high output power density compared to the GaAs, which makes them withstand high operational voltage [28] & [29], and they can provide higher efficiency over wider BW. Among different GaN transistor large-signal models, a Cree’s CGH40010F model transistor from Wolf speed is chosen as its features [30] can provide the desired design specifications proposed two-stage PA. According to S.C. Cripps [16], in Class-J mode by presenting a complex impedance and a pure reactive impedance as expressed by equations (1) & (2) as fundamental and second harmonic loads respectively to the selected transistor, a harmonic boost with a phase shift in the intrinsic drain voltage (VDS) of the transistor can be observed, that reduces the overlap with the drain current (ID),which represents the main feature of the Class- J mode of operation

$$Zf0=\frac{\left({V}_{DD}-{V}_{th}\right)\left(1+j\alpha \right)}{Imax/2}={R}_{opt}+j\alpha {R}_{opt}$$

$${Z}_{2}f0=-\frac{\left({V}_{DD}-{V}_{th}\right)j\alpha }{\begin{array}{c}2\left(\frac{{I}_{max}}{3\pi }\right)\end{array}} =-\frac{j3\pi }{8}\alpha {R}_{opt}$$

where the optimum resistance can be expressed as show in Eq. (3)

$R$ _opt $=$ 2(${V}_{DD}-{V}_{th}$)/I_max (3)

Therefore, after selecting the transistor, the load-line analysis of power stage was performed to obtain the class-J mode’s target reference impedances. Based on this analysis, the selected transistor’s drain is biased with a DC voltage of 28V and gate is biased with ≅ -3V (i.e., almost the threshold voltage).The theoretical drain voltage of the transistor can be expressed as shown in Eq. (4)

$${V}_{J}\left(\theta \right)={V}_{dc}(1+sin\theta )(1+\alpha cos\theta )$$

The “Alpha” factor (α) as shown in Eq. (4) can be varied over a range from − 1to1. Because, each drain voltage waveforms for different values of α when combine with half rectified current it results in same theoretical efficiency causes the class-J mode to expand its BW. Therefore, when (α) is moved from “0” (i.e., class-B mode) to “1”on the slider, the drain voltage and current waveforms which resembles Class-J operation mode can be noticed as shown in Fig. 2 and corresponding load-line based target reference optimum impedances (Z_S and Z_L) are represented on a smith chart as shown in Fig. 3.

Similar to the power stage, from the load line analysis of the driver stage the drain is biased with voltage = 28V, and the gate is biased with voltage = -2.7 V(i.e., class-AB mode).For corresponding biasing point the target reference impedances for the driver stage are obtained from the device datasheet as Z_S =3.18-j*13.3 and Z_L=14.6 + j*7.45.

Once the power stage (Class-J) and driver (Class-AB) stage transistors are biased, the stability analysis was performed for a frequency range of (3–4) GHz corresponding to their biasing points and a stabilization resistor is connected in series with transistor’s gate terminal to make Rollet stability factor (K) > 1,which ensures the transistor’s unconditionally stability. After ensuring the unconditional stability of the transistor to obtain the it’s optimum input and output impedances (Z_S and Z_L) corresponding to the maximum output power and PAE for both driver and power stages of the PA, load-pull simulations were performed on stabilized transistors by taking the target impedances obtained from the load line analysis as reference impedances using 1-Tone load pull instrument of ADS EDA tool as shown in Fig. 4.

The optimum impedances (Z_S and Z_L) corresponding to the Max PAE that are obtained from the LOADPULL simulations are validated by presenting them to the transistor’s terminals instead of 50 Ω terminations for both driver (class-AB) and power (Class-J) stages with respective biasing voltages and input powers at 3.5 GHz input RF frequency.

The next important step after validation of their optimum impedances (Z_S and Z_L) is, the design of appropriate Matching Networks ( M.Ns). Initially, the driver and power stage transistors are represented as “Z2P_Eqn” blocks and their optimum impedances (Z_S and Z_L) are represented as Z [1, 1] and Z [2, 2] of Z2P_Eqn blocks by ignoring the Z [1, 2] and Z [2, 1] (i.e., transfer impedances). Because the M.Ns will be designed to match only these Z [1, 1] and Z [2, 2] ) of driver and power stage transistors with each other and also with the corresponding source and load terminations. As the proposed PA is of a two-stage structure, we need to design 3 M.Ns termed as input, output and interstage. Generally, these M.Ns are designed with passive elements like capacitors and spiral inductors, but they are bulky with low Q factor and fixed inductance value. In addition, such spiral inductors are incompatible with low-cost CMOS process for integration. This issue can be resolved by replacing passive lumped elements of the PA with the active elements such as active inductors, Mos capacitors and active resistors to make it feasible for integration as proposed in our previous work [31]. Therefore, in this work the actual idea is to replace the passive lumped inductors of M.Ns with “tunable Active inductors “as shown in Fig. 5, once the PA design with lumped element-based M.Ns is validated.

So, initially 3 lumped element-based M.Ns such as L-type ,T-type and π-type were designed using their general design procedure for input, interstage and output of the proposed two-stage PA respectively to operate around 500MHz BW with centre frequency of 3.5GHz (i.e., SUB 6 GHz frequency) using ADS EDA tool as shown in Fig. 6.

Now, these designed M.Ns are validated by placing them at the appropriate places of proposed two-stage PA with the 50 Ω source and load terminations, as shown in Fig. 7.As the GaN transistor is used as the active device in the class-J power stage, second harmonic impedance condition is satisfied by the transistor’s parasitic drain source capacitance (C_ds) and C₃ of π-type OMN.

From the simulation results of the proposed two-stage PA, based on the stability analysis, the device is unstable as stability factor (K) is < 1with out any stabilization resistance ,with the placement of a series resistance at the gate of the transistor, it is observed that the K becomes > 1and stability measure is > 0 over desire frequency range (3–4) GHz that ensures the unconditional stability of the power and driver stages transistors as shown in Fig. 8.

From the load pull simulation results of power and driver stage’s stabilized transistors ,the respective optimum source and load impedances obtained corresponding to the maximum PAE and maximum Power/gain respectively are as shown in Table-1.

Table-1. Optimum impedances obtained from load pull analysis

Stage	Optimum impedance	Load Pull Analysis	Max PAE (%)	Max Power (dBm)
Power	Source	6.32 + j*14.0	@ 66	40.5
Power	Load	16.2 + j*4.8	@ 66	40.5
Driver	Source	6.0 + j*15.0	31	@ 34.5
Driver	Load	11.0 + j*4.0	31	@ 34.5

By presenting these optimum impedances at respective transistor terminals the power ,driver stages without M.Ns and two-stage PA with M.Ns are validated by computing their performance parameters using equations with help of “MeasEqn” component of the harmonic balance HB simulator in ADS EDA tool respectively. From the validation of power stage, it is observed that there is a harmonic boost in intrinsic drain voltage time domain signal ts(X2.Q1.vdsi) approximately up to 3 times (i.e., ≈ 84V) of the supplied drain voltage of 28V along with a phase shift that reduces the overlap with half rectified drain current time domain signal ts(-x2.Q1.idi) as shown in Fig. 9, which resembles the Class-J operation mode.

These harmonic boost and phase shift in intrinsic drain voltage are due to the sin2θ and cosθ terms respectively that can be noticed by expanding the Eq. (4) ($for \alpha =1)$ as shown in Eq. (5).

$${V}_{J}\left(\theta \right)={V}_{dc}(1+sin\theta +cos\theta +\frac{1}{2}sin2\theta )$$

It is observed that the power stage (class-J)’s PAE and D.E are estimated as 60.5% and 73.4%. The power output is estimated as 41.5dBm with the small power gain of 7.5 dB by feeding the power stage class-J PA with 34 dBm input power at 3.5 GHz centre frequency. Similarly, the driver stage delivers a power output of 34.9 dBm with a power gain of 12.9 dB by feeding it with 22 dBm input power at 3.5 GHz centre frequency. Finally, by driving the Class-J power stage using class-AB driver stage with proper M.Ns design as shown in Fig. 7, the proposed 2-stage PA delivers power output of 41.1 dBm with overall power gain of 21.1dB with the reduced input power of 20dBm. These performance parameters are tabulated as shown in Table-2.

Table-2.Performance parameters of two-stage PA

Stage	Pin (dBm)	LS_Gain (dB)	Pout (dBm)	PAE (%)	D.E (%)
Power (Without M.Ns)	34	7.5	41.5	60.5	73.4
Driver (Without M.Ns)	22	12.9	34.9	32	33
Two-stage (With M.Ns)	20	21.1	41.1	53	54

The simulation results of these performance parameter variations by sweeping the available source power (Pavs_dBm) or input power (Pin) using the HB simulator, as shown in Fig. 10, demonstrate that, maximum D.E of 54% and maximum PAE of 53% and 41 dBm power output with 21 dB power gain were obtained for corresponding available source power (Pavs_dBm) of 20dBm with 28V DC supply to a 50 Ω load. However, this improvement in the proposed two-stage PA’s power gain is obtained at the cost of its D.E and PAE reduction. It is also noticed that the power output at 3dB compression point is 40.7 dBm which is almost near to the saturated power output value 41.4 dBm, represents the good linearity of the proposed PA.

Similarly, the variations of proposed two-stage PA’s performance parameters Vs RF frequency were measured using HB simulator and the respective simulation results reveal that D.E of 54% ,PAE of 53% at 3.5GHz centre frequency and 41 dBm power output with approximately 21 dB power gain over a 400 MHz BW (i.e., 3.3 to 3.7 GHz) were obtained as shown in Fig. 11.

The S-parameters such as small-signal gain S (2,1) and input, output reflection coefficients S (1,1), S (2,2) of optimised two-stage PA measured using and S-parameter simulator are shown in Fig. 12.

It can be noticed that a small signal gain S (2,1) above 25 dB over 400MHz BW (i.e., 3.3 to 3.7 MHz) with maximum value of approximately 27dB along with the reflection coefficients S (1,1), S (2,2) > -25dB were obtained at 3.5 GHz centre frequency.

The proposed two-stage PA’s improved performance parameters were compared with similar PAs in the literature, as shown in Table 3.

Table 3

Performance comparison
Ref	[19] 2017	[32] 2018	[33] 2020	[34] 2020	[35] 2021	This work
Technology	CMOS	GaN	GaN	GaAs	CMOS	GaN
Class	J	J	J	J	J	J
Frequency [GHz]	3.5	5	3.7	10	9.5	3.5
BW [GHz]	2.1–4.5	4.9–5.9	3.3–4.2	9.1–10.8	8.7–11.8	3.3–3.7
Max Pout [dBm]	22	37.7	39.8	29	20	41
Max gain [dB]	17.4	31.7	-	12	15	21
Max PAE [%]	43.7	54.6	50.6	50	29.7	53
Max D.E [%]	45.1	-	-	71	-	54

Although it is difficult to compare the performance of the PA of this work with the recent similar PAs due to their different design frequencies and technologies, it is worth noting that a 2-stack structure-based CMOS class-J PA with 3.5GHz centre frequency presented in [19] delivers a max Pout of 22dBm.Compared to this, the PA of our work based on GaN transistor delivers a max Pout of 41dBm without any stacked structure due to its high-power handling capability. A 5GHz integrated class-J PA designed for WLAN 802.11ax applications using GaN technology presented in [32] delivers almost same performance metrics like 55% maximum PAE and 38dbM power output. However, this PA’s power gain is comparatively higher than our work due to its 3-stage structure. A dynamic matching network-based Class-J PA design that operates at 5G frequency band is presented in [33], delivers saturated Power of 39.8dBm and maximum PAE of 50.6%.Whereas our Class-J PA delivers maximum PAE of 53% with max power output of 41dBm. However, the performance of PA can be further improved using active inductor based OMN structure. A Class-J PA with the 2-stage structure design using active load modulation technique for X-band presented in [34] eliminates the class-J2 PA’s filter and doubler networks to improves its feasibility for integration. It delivers 50% PAE with the use of an auxiliary circuit for phase-shifting that may require additional space. Whereas the proposed PA of this work delivers a PAE of 53% using the similar 2-stage structure without any auxiliary network for phase-shifting. A CMOS-based 2-stage stacked Class-J PA that delivers a max Pout of 20.2dBm with 15dB power gain and 29.7% PAE was presented in [35]. Using a similar 2-stage structure, the PA of this work based on GaN transistor delivers a max Pout of 41dBm with 21dB power gain and 53% PAE without any stacked structure due to its high-power handling capability. However, the two-stage PA designed in this work exhibits good performance parameters over desired BW with lumped element-based M.Ns, they can be enhanced further by replacing the passive lumped inductors of the PA circuit with tunable Active inductor design to make it more appealing for emerging 5G applications.

A two-stage class-AB/J mode PA’s design methodology using lumped element-based M.Ns that operates at 3.5GHz centre frequency (i.e., sub-6GHz 5G frequency) was presented in this paper. From the simulation results, it is observed that the proposed two-stage PA delivers 54% D.E and 53% PAE at 3.5GHz centre frequency with 27dB small signal gain and 41 dBm power output with improve power gain of approximately 21 dB over a 400 MHz BW (i.e., 3.3 to 3.7 GHz). Although, the proposed two-stage PA is appealing for emerging AMI/smart metering applications of 5G smart grid, its performance parameters can be further improved. However, this work is in progress to replace the proposed PA’s lumped elements with active-element based designs for its integration feasibility and performance parameters enhancement, which makes this PA more appropriate for (sub-6GHz) AMI/smart metering applications of 5G smart grid.

Acknowledgment

We would like to sincerely thank the Multimedia University and Ministry of Higher Education (MOHE), Malaysia for supporting our research work through FRGS MMUE/190075.

Author contributions

Mr. Nagisetty Sridhar- carried out the simulations and drafted the original manuscript, Dr. Chinnaiyan Senthilpari-validated and supervised this research work, Dr. Mardeni R- co-supervised this research work and verified the simulation results , Dr. Wong Hin Yong- verified the simulation results, Dr. T Nandha Kumar-supervised the overall manuscript. All the authors discussed the results and agreed to this final version of the manuscript.

Competing Interests

No competing interests were disclosed

Data availability

Data sharing not applicable to this article as no datasets were generated or analysed during the current study.

Funding information

The Ministry of Higher Education (MOHE), Malaysia, was funded this research work under the FRGS grants.

Ho, T. M., “Next-generation Wireless Solutions for the Smart Factory, Smart Vehicles, the Smart Grid and Smart Cities”, <i>arXiv e-prints</i>, 2019.
Yan et al., “A Survey on Smart Grid Communication Infrastructures: Motivations, Requirements and Challenges,” IEEECommun. Surveys & Tutorials, vol. 15, no. 1, 1st qtr. 2013, pp. 5–20.
Ahmed, T. M. Gondal, M. Adil, S. A. Malik and R. Qureshi, "A Survey on Communication Technologies in Smart Grid," 2019 IEEE PES GTD Grand International Conference and Exposition Asia (GTD Asia), 2019, pp. 7-12, doi: 10.1109/GTDAsia.2019.8715993.
https://www.energy.gov/sites/prod/files/2016/12/f34/AMI%20Summary%20Report_09-26-16.pdf AMI and Customer Systems: Results from the SGIG Program
Zhou, R. Qing yang Hu and Y. Qian, "Scalable Distributed Communication Architectures to Support Advanced Metering Infrastructure in Smart Grid," in IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 9, pp. 1632-1642, Sept. 2012, doi: 10.1109/TPDS.2012.53.
Jiang J, Qian Y. Distributed Communication Architecture for Smart Grid Applications. IEEE Communications Magazine. 2016.Dec16;54(12):6067. https://doi.org/10.1109/MCOM.2016.1600321CM
S SR, Dragičević T, Siano P, Prabaharan SRS. Future Generation 5G Wireless Networks for Smart Grid: A Comprehensive Review. Energies. 2019; 12(11):2140. https://doi.org/10.3390/en12112140
Murat Kuzlu, Manisa Pipattanasomporn, Saifur Rahman, Communication network requirements for major smart grid applications in HAN, NAN and WAN, Computer Networks, Volume 67,2014, Pages 74-88, ISSN 1389-1286, https://doi.org/10.1016/j.comnet.2014.03.029.
A. Z. Murad, M. F. Ahamd, M. M. Shahimin, R. C. Ismail, K. L. Cheng and R. Sapawi, "High efficiency CMOS Class E power amplifier using 0.13 µm technology," 2012 IEEE Symposium on Wireless Technology and Applications (ISWTA), 2012, pp. 85-88, doi: 10.1109/ISWTA.2012.6373883.
Sahu, Shridhar & Deshmukh, Amol. (2013). Design of High Efficiency Two Stage Power Amplifier in 0.13µM RF CMOS Technology for 2.4GHZ WLAN Application. International Journal of VLSI Design & Communication Systems. 4. 31-40. DOI 10.5121/vlsic.2013.4404.
Yi-Hsin Chen, K. Kao, Chun-Yen Chao and K. Lin, "A 24 GHz CMOS power amplifier with successive IM2 feed-forward IMD3 cancellation," 2015 IEEE MTT-S International Microwave Symposium, 2015, pp. 1-4, doi: 10.1109/MWSYM.2015.7166914.
Kazuaki kunihiro, Shinichi hori, Tomoya kaneko, “High Efficiency Power Amplifiers for Mobile Base Stations: Recent Trends and Future Prospects for 5G”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018, Volume E101.A, Issue 2, Pages 374-384, Released February 01, 2018, Online ISSN 1745-1337, Print ISSN 0916-8508, https://doi.org/10.1587/transfun.E101.A.374
Reynaert, Y. Cao, M. Vigilante and P. Indirayanti, "Doherty techniques for 5G RF and mm-wave power amplifiers," 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016, pp. 1-2, doi: 10.1109/VLSI-TSA.2016.7480475.
M. Asbeck, "Will Doherty continue to rule for 5G?" 2016 IEEE MTT-S International Microwave Symposium (IMS), 2016, pp. 1-4, doi: 10.1109/MWSYM.2016.7540208.
A. Jayamon, J. F. Buckwalter and P. M. Asbeck, "28 GHz >250 mW CMOS Power Amplifier Using Multigate-Cell Design," 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2015, pp. 1-4, Doi: 10.1109/CSICS.2015.7314460.
C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Boston, MA, Artech, 2006.
Wright, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “"A methodology for realizing high-efficiency class-J in a linear and broadband PA”" IEEE Trans. Microwave Theory Tech., vol. 57, no. 12, pp.3196–3204, Dec. 2009
Rezaei, L. Belostotski, F. M. Ghannouchi and P. Alfaki, “"Integrated Design of a Class-J Power Amplifier”" in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 4, pp. 1639-1648, April 2013, DOI: 10.1109/TMTT.2013.2247618.
Dong, L. Mao and S. Xie, "Fully Integrated Class-J Power Amplifier in Standard CMOS Technology," in IEEE Microwave and Wireless Components Letters, vol. 27, no. 1, pp. 64-66, Jan. 2017, Doi: 10.1109/LMWC.2016.2630920.
Alizadeh, M. Frounchi and A. Medi, "Waveform Engineering at Gate Node of Class-J Power Amplifiers," in IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 7, pp. 2409-2417, July 2017, doi: 10.1109/TMTT.2017.2651814.
Alizadeh and A. Medi, "Investigation of a Class-J Mode Power Amplifier in Presence of a Second-Harmonic Voltage at the Gate Node of the Transistor," in IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 8, pp. 3024-3033, Aug. 2017, doi: 10.1109/TMTT.2017.2666145.
Alizadeh, M. Yaghoobi and A. Medi, "Class-J2 Power Amplifiers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 8, pp. 1989-2002, Aug. 2017, doi: 10.1109/TCSI.2017.2683067.
Hanna, N. Deltimple and S. Frégonèse, "A class-J power amplifier for 5G applications in 28nm CMOS FD-SOI technology," 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI), 2017, pp. 110-113.
K. Hiew, N. M. Aripin, S. Jayavalan and N. M. Din, "Spectrum band for smart grid implementation in Malaysia," 2013 IEEE Student Conference on Research and Development, 2013, pp. 26-30, doi: 10.1109/SCOReD.2013.7002534
Roslee, A. Alhammadi, M. Y. Alias, K. Anuar and P. U. Nmenme, "Efficient handoff spectrum scheme using fuzzy decision making in cognitive radio system," 2017 3rd International Conference on Frontiers of Signal Processing (ICFSP), 2017, pp. 72-75, doi: 10.1109/ICFSP.2017.8097144.
https://www.techplayon.com/5g-nr-frequency-bands
Parvez, Imtiaz & Sarwat, Arif. (2019). “A Spectrum Sharing based Metering Infrastructure for Smart Grid Utilizing LTE and WiFi.” Advances in Science, Technology and Engineering Systems Journal. 4. 70-77. 10.25046/aj040209.
Husna Hamza, D. Nirmal, A review of GaN HEMT broadband power amplifiers, AEU - International Journal of Electronics and Communications, Volume116,2020,153040, ISSN14348411, https://doi.org/10.1016/j.aeue.2019.153040.
https://www.armms.org/media/uploads/05_armms_apr13_rpengelly.pdf
https://assets.wolfspeed.com/uploads/2020/12/CGH40010.pdf
Sridhar, N., Senthilpari, C., Mardeni, R. et al. A low power, highly efficient, linear, enhanced wideband Class-J mode power amplifier for 5G applications. Sci Rep 12, 8101 (2022). https://doi.org/10.1038/s41598-022-12235-z
Liu, M. Mao, C. C. Boon, P. Choi, D. Khanna and E. A. Fitzgerald, "A Fully Integrated Class-J GaN MMIC Power Amplifier for 5-GHz WLAN 802.11ax Application," in IEEE Microwave and Wireless Components Letters, vol. 28, no. 5, pp. 434-436, May 2018, Doi: 10.1109/LMWC.2018.2811338.
Gao, Y. Luo, C. Shen and R. Lei, "Design of Class-J Power Amplifier with Dynamic Matching Network for 5G Frequency Band," 2020 IEEE 20th International Conference on Communication Technology (ICCT), 2020, pp. 472-475, doi: 10.1109/ICCT50939.2020.9295827
Alizadeh, S. Hassanzadehyamchi, A. Medi and S. Kiaei, “"An X-Band Class-J Power Amplifier with Active Load Modulation to Boost Drain Efficiency”" in IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2020.2991184. May 2020.
Zhang et al., "An X-Band Broadband High-Efficiency Power Amplifier with Class-J Mode Matching Network," 2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2021, pp. 1-3,

No competing interests reported.

Download PDF

Version 1

posted

You are reading this latest preprint version

Design of Multistage Class-AB/J Power Amplifier for 5G Smart grid’s Advanced Metering Infrastructure Applications

Status:

Version 1

Abstract

Figures

1. Introduction

2. Related Works

3. Two-stage Pa Design Methodology:

4. Results & Discussion

Conclusion

Declarations

References

Additional Declarations

Status:

Version 1