Optimizing of Communications Systems Power Eciency Considerations: Ecient Implementing Approach of Hamming Codes Utilizing FS-GDI

Due to the power eciency importance of digital signal processing and data protection in different communications systems, this paper proposes an ecient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power eciency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the eciency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves ecient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.


Introduction
The channel coding techniques play important role in the transmitted data protection over the wireless communications channels. The amount of consumed power limits the utilizing of error coding techniques and the powerful data security techniques due to its computational complexity [1]. In this paper, low power error control hamming codes design is proposed using FS-GDI approach. The FS-GDI approach is power e cient low power VLSI logic style compared to the traditional approaches [2][3][4][5][6][7][8][9][10].
In [11] the complexity in the wireless communications due to the amount of the transmitted data encoding is analyzed based on the used error control code is the Convolutional codes and the Hamming code. The presented analysis in this paper proved that the complexity is related to the amount of required/consumed power. That means with increasing the computational complexity, the consumed power increases. On the other hand. the power e ciency of the communications systems is considered in several research papers [12][13][14][15][16][17][18][19]. The power is main constraint for the application of the data protection techniques. Hence, design low power error control schemes using the power e cient approach will be increasing the capability of data protection techniques using and enhancing the power e ciency of the systems in general [20].
In this paper, different Hamming codes design is proposed based on GDI and FS-GDI approaches. The proposed codes design is compared with the traditional CMOS approach utilizing different metrics such as the delay time, consumed power, Power Delay Product (PDP) and number of transistors which are required for implementing the Hamming codes by the different traditional CMOS, GDI and FS_GDI Page 3/15 approaches. The simulation experiments prove the superiority of the proposed Hamming code design using FS-GDI compared to the traditional approach. The software package which is used for performing the design and the simulation experiments is Cadence Virtuoso simulator [21][22][23][24].
In the following, the rest of paper is presented as follows: section 2 presents the low power VLSI approaches and its sub-approaches. GDI approach Development and Versions are introduced in section 3. In section 4, the complexity due to the encoding process is discussed. The proposed work description of different Hamming implementation and experiments codes are presented in section 5. In section 6, result analysis is presented. the conclusion is introduced in section 7.

Low Power Vlsi Approaches Overview
The different styles of the VLSI are presented in this section. In the following, the different approaches advantages and disadvantages are discussed. Figures 1 and 2 give AND and XOR logic gates realizing using the different approaches, respectively.
The Complementary symmetry metal-oxide-semiconductor CMOS is the most popular approach, it has several advantages such as, low noise margin, high speed, low power, easy to develop, common in most chips design of VLSI. Also, it suffers some problems such as, high power dissipation, large number of transistors/area, long delay time, power consumption high. The second common approach is the Pass Transistor Logic (PTL), it is popular as CMOS approach, its features as decreased silicon area, speed, reduced power consumption, slower at reduced power, signi cant power dissipation [25][26][27][28].
The third approach is the Transmission Gate (TG), its feature is less transistor for implementing complex gates, PMOS and NMOS combination avoid noise margin, power dissipation, switching, require control, limited TG cascade. The fourth approach is the Complementary Pass-Transistor logic-(CPL), ( N-MOSFET approach), its advantages is high speed, low i/p capacitance and easy to implement complex logic by NMOD net. It is drawbacks is drop in threshold voltage, static power consumption and delay increases with long pass-transistor chains. The Double Pass-transistor Logic (DPL) approach is the modi ed of CPL approach, it has some advantages as well-balanced input capacitance No drop voltage, no need buffers, full swing and low power, its main problems are large area and inverters need [29][30][31][32].

Gdi Approach Development And Versions
A long fourteen years, Morgenshtein et al. presented the GDI approach for low power VLSI implementing.
In 2002, 2010 and 2014, the original cell of GDI, modi ed GDI and Full Swing GDI have been presented, respectively by Morgenshtein. Gate diffusion input (GDI) is a new low power technique using small silicon chip area for digital VLSI design compared to another logic style proposed by Morgenshtein. This approach aimed to improve the power consumption and area as well as propagation time of the logic gates implementing compared to the traditional approaches [33][34][35].
In 2001, the GDI approach was invented, it allowed complex gate implementing by two transistors. This method is suitable for the design of fast, low-power circuits, using a reduced number of transistors (as compared to CMOS and existing PTL techniques) as shown in Table 1 [33]. As shown in this table the different logic gates hardware can be simpli ed by reducing the number of transistors to be more power e cient.  The logic gates such as AND, OR and XOR gates can be implemented with full swing operation can be achieved but with increasing the transistor count from 2 to 3 compared to the original GDI design.

Encoding Process Complexity
As mentioned in section 1, the computational complexity is the amount of operations in the systems for perfuming its function. The complexity is directly related to the amount of the required power and the process time, it is called also time complexity. The error control codes utilizing for data protection is essential issue. The computational complexity of these codes differs according to its type and capabilities. The block codes such as Hamming codes complexity is determined based on its data-word (k) and codeword (n) length, in general it simpler than the Convolutional codes. The Convolutional codes encoding/decoding have high complex compared to the block codes [40]. In this paper, the simpler block codes (Hamming codes) are chosen for evaluating the proposed design of data protection techniques by the FS-GDI approach.
The complexity basis of error control codes is presented in this section. Block codes complexity is limited and lower than Convolutional codes [20]. Mostly, complexity of block codes is controlled by two factors, which are the input length of the encoder and the codeword the output of the encoder. In the block codes the length of the processed data is not important factor, the packet already segmented to small parts each one of them has length of data word. In the Convolutional codes, the complexity is controlled by many factors, length of input it is the processed data in the same time interval, the length of output, the length of the processed data "packet length" and nally, length of the memory in Convolutional encoder.
In fact, the computational complexity of the Convolutional codes increases with the constraint length increasing [41][42].
In this table, the extra computational complexity related to the proposed technique is considered and the complexity related to the memory length of the convolutional encoder also. As shown in the numerical analysis of the hardware complexity of the traditional CMOS approach and FS-GDI approach Hamming codes in Table 4, it proves that the superiority of the proposed technique complexity especially with the longer data-word packets processing.

The Proposed Scheme Description
In this section, the different Hamming codes (7,4) and (11,7) implementation approaches are presented. The FS-GDI approach are proposed for implementing the Hamming codes as an approach for achieving power e cient data encoding tool.

The Proposed FS-GDI Hamming Code (7,4) Design Implementing
In this section, simple data protection Hamming code (7, 4) error control scheme is implemented and realized by the FS-GDI approach for enhancing its power e ciency and hardware simplicity. In this error control code, 7 number represents the number of output of Hamming encoder bits it is 7 bits. The number 4 refers to the number of bits encoder input, it is 4 bits in this encoder.
Hamming Algorithm mechanism:-The Hamming code algorithm is working as described following steps: -The parity bits (P) are generated and added to (k) bits data-word to form the code-word of (n)n=k+P bits.
-The P bits are generated by the simple equations from the input data (data-word).
The data-word is the input of the encoder circuit, it performs XOR operations on the k data-word, hence the required (p) parity bits generated. Parity bits and data bits together form the code word. An encoder circuit of Hamming code for 4-bit data word is shown Fig. 4. Following this circuit pattern, we can design an encoder circuit of hamming code for 7-bit data word and it is implemented in cadence virtuoso tool. Fig. 4 consists of 4-bit data word, parity bit generator and 7-bit code word. The 4-bit data word is applied as an input to the encoder circuit, now the encoder output consist of 7-bits i.e. 4-data bits D 1 , D 2 , D 3 & D 4 and 3-parity bits P 1 , P 2 & P 4 , as in Eqs (1-3): The Codeword : D 4 D 3 D 2 P 4 D 1 P 2 P 1 The data word is applied as an input to the encoder circuit which performs XOR operations on the given data word thus the required parity bits are generated from the parity bit generator. Parity bits and data bits together form the code word. An encoder circuit of hamming code for 4-bit data word is shown in Fig.  4. The Hamming encoder consists of 4-bit data word, parity bit generator and 7-bit code word. The 4-bit data word is applied as an input to the encoder circuit, now the encoder output consists of 7-bits i.e. 4data bits D 1 , D 2 , D 3 & D 4 and 3-parity bits P 1 , P 2 & P 4 , as in Eqs (1-3).
a. Testing the Proposed design of Hamming Encoder (7, 4) Performance Simulations were done using the spectre based Cadence Virtuoso simulator with a power supply of 1V and frequency 100M HZ, the size of PMOS is twice the NMOS transistor size Wp/L=240/60, Wn/L=120/60 (PMOS and NMOS) respectively to achieve the best power and delay performance. Each component is analyzed in terms of propagation delay, power dissipation, and their product. The propagation delay is measured by accounting the time taken from 50% of the input voltage swing to 50% of the output voltage swing for each transition. Table 2 shows the values of the evaluating metrics of the proposed implementing approach of Hamming code (7, 4). The second implemented Hamming code by the FS-GDI for a 7-bit data word, the code word consists of 11-bits i.e. 7-data bits D1, D2, D3, D4, D5, D6, D7 and 4-parity bits P1, P2, P4 & P8 as shown in Table 2.
The parity bits calculated for 7-bit data is as follows in Eqs (4-6): The Codeword :. D 7 D 6 D 5 P 8 D 4 D 3 D 2 P 4 D 1 P 2 P 1 a. Performance Evaluating of the Proposed Hamming Encoder (11, 7) Design  Table 3 shows the values of the evaluating metrics of the proposed implementing approach of Hamming code (11,7). As shown in the previous experiments which are devoted for evaluating the performance of the proposed design of the different Hamming codes with the various data-word and codeword lengths.
The values of the utilized metrics which are measured in these experiments clear the superiority of the Hamming codes implementation based on the FS-GDI compared to the CMOS approach based.

The Results Analysis
In this section, the previous experiments results are analyzed numerically. By considering the metrics results of the CMOS approach scenario is the standard and traditional approach, the improving percentage denotes by +, This + symbol means there is amount of improvement. On the other hand the (-) symbol means there is not improving. In Table 4, the results are analyzed numerically as cleared. As shown in Table 4, the proposed Hamming codes implementing using the FS-GDI achieves power e ciency 44.77% and 26.93% for the Hamming codes (7,4) and (11,7), respectively compared to the CMOS approach. While these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7,4) and (11,7), respectively. These results clear the e ciency of the presented approach for implementing the different error control techniques. In general, the utilizing these proposed implementation approach reduces the power consumption of the data encoding. On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % as shown in the results analysis table.

Conclusion
This paper proposes the FS-GDI approach for implementation the error control schemes for enhancing the power e ciency of the data encoding process. The paper presents proposed implementation of Hamming codes (7,4) and (11,7) using FS-GDI approach. The proposed design and simulation experiments are carried out using Cadence Virtuoso simulator package. There are different metrics are utilized for measuring the performance of the proposed FS-GDI based Hamming codes. The simulation experiments results prove the superiority of the proposed data encoding tool compared to the traditional approach. The proposed approach for Hamming codes implementation achieves 50 % H/W simplicity. Also, the power e ciency of the proposed Hamming codes is improved by 44.77% and 26.93% for the Hamming codes (7,4) and (11,7), respectively compared to the CMOS approach. On the other hand, the delay time is optimized in the proposed Hamming codes implementation approach compared to the traditional CMOS approach. Finally, the proposed Hamming codes in this research paper presents a method for high e cient power data encoding process. This approach can be suitable for implementing the complex error control schemes.

Declarations
Con ict of Interest: Author 1: Mohsen A. M. El-Bendary declares that he has no con ict of interest. Author 2: O. El-Badry declares that he has no con ict of interest. Declaration: Authors declare and con rm that there is no funding was received for this work.
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