Effect of Negative Capacitance in Partially Ground Plane based SELBOX FET on Capacitance Matching and SCEs

Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET) over FDSOI. The ferro-electric layer is placed in the gate stack of PGP-SELBOX NCFET to generate the negative capacitance phenomenon. Ferro-electric(FE) materials are similar to dielectric materials but differ in terms of their polarization properties. FE-HFO2 is used as ferroelectric material due to its sufficient polarization rate with high dielectric capacitance and better reliability. The effect of ferro-electric material parameters like coercive field(Ec) and remnant polarization(PR) on the capacitance matching of NCFET are analyzed. The simulation results reveal that the RPE factor, which is the ratio of PR to Ec, is closely related to better capacitance matching. In addition, the effect of variation in thickness of ferro-electric layer on the average sub-threshold swing(SS) is also explored. The relation between short channel effects (Vth rolloff and DIBL) and thickness of the ferro-electric (tfe) for PGP-SELBOX NCFET is also analyzed. The simulation results clearly show that PGP-SELBOX NCFET is having reduced SCEs and 103 times better IONIOFF\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$\frac {\mathrm {I}_{\text {ON}}}{\mathrm {I}_{\text {OFF}}}$\end{document} ratio over FDSOI NCFET. For optimized value of ferro-electric parameters average SS for proposed device is found as 50 mV/decade at tfe = 5nm which is lesser than FDSOI NCFET (56 mV/decade).


Introduction
In today's era, demand for low power devices at nanoscale level is continuously increasing. But with continuous scaling, issues related to gate control, leakage current and static power dissipation reached an unmanageable level and SS stuck at the fundamental thermal limit of 60 mV/dec, which is known as Boltzmann tyranny [1]. It is difficult to achieve low power consumption and high performance of the device due to this tyranny limit.
Shalini Chaudhary 2019rec9066@mnit.ac.in 1 Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur, Rajasthan, 302017, India There are various concepts given to improve the SS. Based on current phenomenon, such as band to band tunneling in tunnel FET (TFET) [2,3] and impact ionization technique in impact ionization MOS (IMOS) [4] to improvise the SS below 60 mV/dec. The main disadvantage of TFET is that it could not address the issue of low ON current and its ambi polarity nature. IMOS too has drawback of operating at a very high voltage.
Due to these disadvantages of TFET and IMOS, the negative-capacitance FETs (NCFETs) [5] have draw much attention as a new type of steep switching device. The NCFETs can achieve steeper SS and higher I ON . It is due to the amplification of the gate voltage by negative capacitance phenomenon obtained by integrating ferro-electric material in the gate stack of the traditional MOSFET [6][7][8][9][10]. Hence the lower value of SS is achieved.
However due to the continuous scaling of MOSFET (< 65nm), the performance is severely affected by short channel effects (SCEs). When length of the channel decreases, the control of the gate over the channel gets reduced due to presence of SCEs like DIBL, V th rolloff, mobility degradation and gate leakage current. A thin-film siliconon-insulator (SOI) based MOSFET was introduced to overcome these SCEs. They are capable of performing at low power consumption and leakage power along with a steeper subthreshold slope [11,12]. But the main disadvantages associated with this are self heating and low breakdown voltage [13]. The self heating basically degrades the overall performance of the device and reliability too.
The self-heating problem is considerably reduced by using the silicon over partial BOX. One such example is the selective buried oxide (SELBOX) device [14,15]. This BOX is like a window which joins the active region of device with substrate and provides path for the dissipation of heat. So there is reduction in self heating during the achievement of high breakdown voltage. But issues with such structure is that the magnitude of short channel effects is higher in these devices. These short channel effects create many issues like increase in leakage current, increase in DIBL voltage, shift in threshold voltage with decreasing channel length, decrease in subthreshold slope and reliability issues like hot carrier effect [16].
To overcome the drawbacks of SELBOX structure, partial ground plane(PGP) is incorporated with SELBOX [17], due to which SCEs is reduced significantly. This also creates the scope of further scaling of the device. In this device, the BOX is made under the source and drain regions and another region is made under the channel region which worked like a window for this structure. The heavily doped PGPs is used under the SELBOX, which is placed along the edge of SELBOX and in line with the source/drain. This PGP type structure stops the electric field lines from reaching drain to source directly and minimize the coupling of field lines. Due to this, short channel effects like DIBL is reduced [18,19]. We have considered PGP in place of continuous ground plane because it increases the parasitic capacitance related to the source and drain and increases crosstalk. Hence for performing the NCFET operations, PGP-SELBOX as a baseline device is taken [17]. Figure 1(a) shows comparison of the current characteristics of the FDSOI and PGP-SELBOX FET and we found that the I ON /I OF F is better in case of the PGP-SELBOX. Due to this high I ON /I OF F ratio and other advantages of PGP-SELBOX which are described above, we took this structure as baseline and did performance analysis by converting it into a NCFET. The doped hafnium oxide (FE-HFO 2 ) is used as FE material [20]. Because of the low dielectric constant (30) and high coercive field (1-2 MV/cm) of doped hafnium oxide, we can easily incorporate it into current CMOS technology node.

Fabrication Flow of this Proposed Device
For the fabrication of PGP-SELBOX NCFET the starting material is taken as p-type (100) oriented Czochralski silicon wafers having resistivity range of 15-25 cm. A thin oxide layer can be grown over the channel region by photolithography and reactive ion etching to stop oxygen implantation. After that oxygen ion implantation with proper doses and at optimized implant energies is taken place. For creating patterned BOX, a low dose SIMOX (separation by implantation of oxygen) Technique is used [21]. High dose SIMOX technique generates stress and dislocations. For partial BOX, dose is in the range of (2.5 -4.8)×10 17 O + cm − 2 at optimized implant energies of 70-140 keV. After formation of these BOXs oxide masks are removed and annealed it. For making PGP, nitride layer is deposited over pad oxide over the SELBOX part. By using masking and photolithography positions are formed where p+ impurities is needed. However, the nitride and oxide are kept intact where the gate is accomplished. Ion implantation is done to make p+ PGPs that are aligned with gate and SELBOX. Bulk of the wafer is removed by mechanical and chemical polishing and wet chemical etching.
Afterwards, gate stack was deposited and defined by the lithography. The high-K Hf O 2 , FE-H F O 2 and metallic TiN layers were prepared by ALD at 300 • C. The oxygen/nitrogen sources are H 2 O vapor andN 2 /H 2 plasma for Hf O 2 and TiN, respectively. The Pt electrodes were prepared by the RF sputtering. Afterwards, the thermal evaporation, lift-off process, and rapid thermal annealing at 400 • C were utilized to form the NiSi contacts at the source and the drain [22].

Deliverables and Organization of this Work
In this paper we propose a new geometrically negative capacitance FET which have a single gate and shows the performance like multigate FET. This proposed device uses the advantage of PGP-SELBOX FET and provide better FET design when it is combined with a ferro-electric layer in the gate stack for providing negative capacitance effect. When heavily doped ground plane is present then it prevents the electric field lines from reaching drain to source directly. With PGP, coupling of electric field lines is minimized which results in reduction of short channel effects like DIBL, SS,V th roll off. This manuscript is organized as Section 2 in which the device architectural specifications and simulation methodology is discussed. In Section 3 the proposed device is mainly analyzed for capacitance matching in terms of ferro-electric material parameters and also discuss about short channel effects.

Device Structure and Simulation Methodology
For preventing the complications related to parasitic capacitance and the short channel effects PGP-SELBOX technology is used, which is suitable for a baseline structure. Therefore the PGP-SELBOX structure with negative capacitance is analyzed in our work. The schematic of the investigated NCFETs and its corresponding capacitance model are shown in Fig. 2(b) and (c) respectively. In this work only n-channel structure is presented but the approach used in the simulation is equally valid for the p channel NCFET [6,23]. In Fig. 2(c) the equivalent capacitance model of this structure is given and according to this, total capacitance of device is series combination of MOS capacitance (C MOS ) and ferro-electric capacitance (C fe ). C MOS is the series combination of the oxide capacitance( C OX ) across oxide layer of baseline device and semiconductor(depletion) capacitance (C S ) of the baseline device. If we use the BOX structure then MOS capacitance is a series combination of capacitance of insulating layer, BOX layer and semiconductor. In Fig. 2(c), V g is gate voltage across the NCFET structure and V MOS is the mos voltage across the baseline device. The parameters values used in this structure are given Fig. 2(a). We used Equivalent oxide thickness(EOT) concept in place of the insulating layer of SiO 2 only and for that we have taken combination of HfO 2 with the thin layer of SiO 2 layer. Channel length( L g )is taken as 30 nm and SELBOX length is also 30 nm. PGP is like a square box of dimension 10 nm.
There are two approaches to fabricate the NCFET. One is by directly integrating the ferro-electric material on the oxide layer in the gate stack like Metal ferroelectric insulator semiconductor (MFIS) and other one is the use of metallic layer in the gate stack before applying the ferro-electric material layer [24]. The latter one is like connecting a regular FET with the NC capacitor and this also called Metal-ferroelectric-metal-insulatorsemiconductor(MFMIS) approach and we adopted this approach in our work. The purpose of using the metallic layer between the two dielectrics is that it cancels out the non-uniform potential profile across channel and charge non uniformity due to domain formation in the ferroelectric [25] and controlling the matching of capacitance and overcome the interference generated due to spacer. Figure 2(d) shows the process flow of the simulation approach.
As we go for MFMIS structure, first we simulated our baseline structure in Silvaco TCAD [26]. Before simulating the structure, TCAD tool is calibrated against the data present in reference [17]. For simulation purpose standard models like CONSRH (concentration dependent Shockley Read Hall re-combination model), AUGER (Auger recombination model), BGN (bandgap narrowing model) and CONMOB (concentration dependent mobility model) are used. For obtaining the calibrated results we tuned energy band density of states (NC300, NV300) and carrier lifetimes (electron lifetime: TAUN0, hole lifetime: TAUP0). For subsequent work, same calibrated model file and tuned parameters are used but dimensions are changed for simulation of this device. The calibrated graph for the simulator is given in the Fig. 1(b). After getting charge density, current characteristics and other parameters from simulation, we solve self consistently Landau-Khalatnikov (L-K) model with these simulated results and obtained the characteristics of the NCFET in the MATLAB.
According to the L-K equation [27], the Gibbs free energy density (U) of the ferroelectric layer can be expressed in the powers of the polarization (P) in the vicinity of a phase transition as: This equation can also be written in terms of charge(Q) because we consider (P=Q) in case of NCFET analysis as in reference [5]. Equation 1 can be written as Here α, β and γ are constants (Landau parameters) which are material dependent and t fe is thickness of the ferroelectric film, V fe is voltage applied across the ferroelectric layer. In order to get the equilibrium state of the ferroelectric layer, minima of U is derived by differentiating the U w.r.t Q and the relation for V fe is found as: Now the voltage across the NCFET can be written as where V G is the applied gate voltage across NCFET and V MOS is the intermediate contact potential (gate voltage across base line device). The 2D electrostatics for the baseline are simulated by using the same models that are used at the time of calibration as consrh, auger, conmob and bgn. The channel thickness of this device is greater than 6 nm so we have not taken Quantum simulation model here. FE-HfO 2 is used as the gate ferroelectric material which exhibit the second-order phase transition. For this FE-HfO 2 , α < 0, β > 0, and γ = 0. The nonzero parameters like α and β can be written in terms of the remnant polarization(P r ) and coercive field (E C ) [28,29] is defined as, By these above formula we can alter the value of alpha and beta with E C and P R and obtained better capacitance matching for the NCFET operation.

Assessment of Capacitance Matching with Variation in Ferroelectric Parameters
Stabilizing the negative capacitance effect is a critical issue in capacitance matching among |C fe |, C mos and C ox [30]. The required conditions for the same are |C fe | < C OX and |C fe | ≈ > C MOS (for non-hysteresis) It can be seen that for NCFET in order to function in negative capacitance region and to amplify V MOS to achieve high performance, the C fe should be approximately equal or slightly greater than C MOS is a necessary condition. So during the design, appropriate capacitance matching between the capacitance of the FE layer(C fe ), the buffer oxide capacitance(C OX ) and the MOS capacitance (C MOS ) is very important to realize the desired operation mode. The ferro-electric capacitance is defined in terms of the E C , P R and t fe written as In above Eq. 6, we neglect higher terms of charge (Q) because its value is very less. So, it can be written as P R E C * t fe (7) We can obtain better capacitance matching for NCFET by varying parameters as E C , P R and t fe [31]. SS can also be written in terms of the capacitance by which we can control the value of average SS. SS is defined at room temperature for NCFET as

Optimization of Coercive Field (Ec) and Remnant Polarization (Pr)
In this section, the material parameters such as coercive field (E C ) and remnant polarization (Pr) for FE-HFO 2 are optimized according to the experimental data reported in reference [28]. To get a better understanding of hysteresis and non-hysteresis operation of the device and to acquire the optimized values of E C and P R , we studied the charge density (Q g ) versus FE capacitance (C fe ) and MOS capacitance(C mos ) characteristics of the reference PGP-SELBOX FET device. Thickness of ferroelectric layer is considered as t fe = 5 nm, since it is the minimum thickness of doped HFO 2 which can be fabricated for the range of E C and P R values reported in reference [28]. It can be inferred from Fig. 3(a) that out of all values of E C and Pr, maximum amplification without hysteresis can be obtained for E C = 1.4 MV/cm and P R = 6.5 μC/cm 2 . For these values, FE layer capacitance is close to MOS capacitance which implies better matching to achieve maximum enhancement of the capacitance. Further it can be also seen from Fig. 3(a) that for E C = 1.4 MV/cm and P R less than or greater than 6.5 μC/cm 2 , device does not perfectly match with C fe . Figure 3(b) shows change in gate capacitance with gate voltage. Gate capacitance(C g ) is given as C g = (C −1 fe + C −1 mos ) −1 and it is found that for E C = 1.4 MV/cm and P R = 6.5 μC/cm 2 , |C fe | ≈ C MOS and obtained peak in the subthreshold region. As we moves towards larger value of P R peak is greater but slightly move towards the inversion region because at larger P R , | − C fe | >> C mos and capacitance does not match properly to operate in negative capacitance region.
From Fig. 4(a) we observed current characteristics for different values of P R and found that as values of P R decrease the SS decreases in the subthreshold region and smaller P R shows a steeper sub threshold characteristic. It can also be better explained with the graphs of variation of V MOS with V g and variation of V fe with V g for different values of P r in Fig. 4(b) and (c) respectively. It is also explained with Eq. 4, according to which when P r is reduced, V g decreases due to increase in −V fe . Thus the same value of drain current at lower V g is obtained and SS decreases. Figure 5(a) describing the effect of variation in E c for better capacitance matching. According to the Eq. 7 we found that C fe is inversely proportional to E c . As we increase the more value of E c , C fe decreases. For our simulation we get optimum matching at E c = 1.4 because at this point C fe ≈ C mos at fixed P R of 6.5 μC/cm 2 . The value of E c is varied between 1.35 to 1.5. From analysis we found that for E c > 1.4, the value of C fe is decreasing and becomes less than C mos and which is not desirable for NCFET. Figure 5(b) shows the effect of gate capacitance with variation in E c . For optimum value of E c we found peak in subthreshold region. As value of E c increases the peak is increasing but shifting towards inside because C fe is decreasing and become less than C mos and which is not desirable. Figure 6(a),(b),(c) are showing the current characteristics for different values of E c , variation of V MOS with V g and variation of V fe with V g for different values of E c . From current characteristics we found that as E c is increasing V MOS and V fe is increasing more and more due to which the hysteresis is shown in the current characteristics and which is not desirable for NCFET analysis. Figure 6(d) shows the average value of SS for different values of E c and P R . For optimum value of both E c and P R , we found average SS is 50 mV/decade which is less than the Boltzmann tyranny limit of 60mV/decade. For the baseline device the value of SS is obtained as 73 mV/decade but due to effect of negative capacitance and proper capacitance matching we obtained SS less than the baseline device. Here we also observed lower value of SS (< 50 mv/decade) but that region is not showing proper capacitance matching and having hysteresis behavior.

Variation in Ferro-electric Thickness(t fe )
Operation of NCFET based circuits is also characterized by the ferro-electric thickness(t fe ). It also affects the capacitance matching condition because C fe is inversely proportional to t fe . When the value of the t fe increases, |C fe | decreases and matching will be better. But there is a limit of increasing it because after a particular thickness we start obtaining hysteresis. In our simulation we have taken t fe = 5nm which is the maximum thickness for obtaining hysteresis free curve. Figure 7(a) showing the I d -V g curves for different values of t fe and found that hysteresis starts as we move from 5nm to 6nm. This can also be better explained with Fig. 7(b) and (c) which are describing relation between V MOS with V g and V fe with V g . From there we found that as t fe increases V MOS becomes greater than V g and moving towards hysteresis. Similarly V fe start decreasing and becomes more negative and after a critical thickness (> 5 nm), shows hysteresis property.

R PE factor
For describing the effect of P R and E C in a better way for capacitance matching, we define a factor R PE . R PE is the ratio of P R and E C .
For better matching between |C fe | and C mos , the value of |C fe | should be close to C mos and for obtaining this P R should be less and E C should be more. R PE factor also correlated with the SS of the NCFET. Figure 8(a) gives the I d -V g curves for five NCFETs which having same (R PE = 5) for different combinations of P R and E C and obtained almost the same current in sub-threshold region for all but slightly different current above this region. It is due to P r as it is dominant factor as gate voltage increases. Figure 8(b) shows that for same R PE , SS and threshold voltage (V th ) is almost the same.

Reverse DIBL and V th Roll Off
Biasing of drain is having great impact on the electrostatic behavior of the devices particulary at the nanoscale level. As we know when the value of drain biasing increases for the simple devices (without negative capacitance effect), value of V t decreases and we obtained drain induced barrier lowering (DIBL). It is basically due to lowering of band with the effect of high drain voltage. In our paper we selected PGP-SELBOX structure as baseline structure because in Fig. 9(a) we analyze the current characteristics  of both FDSOI and PGP-SELBOX structure at drain voltage (V d ) 0.7 V and 0.07 V and found reduction in DIBL.
It is because of PGP as it held high the gate induced field in comparison to without PGP structure. The DIBL is defined as where V high th is the threshold voltage at high V DS and V low th at low V DS . We calculated DIBL by above Eq (9) and found 143 mV/V for simple FDSOI and 95mV/V for the PGPSELBOX.
In case of the negative capacitance we found the reverse effect of the DIBL or we obtained drain induced barrier rising effect(DIBR) and because of it, the V t at high drain voltage increases and we obtained negative value of DIBL. It is observed because of increase in the potential barrier with increase in drain voltage. This drain induced barrier rising explained the negative capacitance phenomenon and is related with the recent studies. Figure 9(b) shows the variation of Reverse DIBL and SS with t fe .
For high value of drain voltage V t decreases with increase in t fe . This is due to the increase in barrier height. Because of this DIBL increases in negative direction and SS is also decreasing with t fe . Figure 9(c) shows the V th roll off for both type of NCFET based on FDSOI and PGP-SELBOX. From the figure we found that V th roll off improves in case of PGP-SELBOX NCFET because of its PGP type structure as it increases the gate control. Due to which V t does not decrease as much as in case of FDSOI NCFET, hence V th roll off improves in the proposed structure.

Performance Comparison with Counterpart Technologies
Maintaining performance consistency during down-scaling of devices becomes critical. In this section we compare some recent technologies with the proposed work shown in Table 1. Tunnel FET is one of the approach to overcome the thermal limit (60mV/dec) of SS during downscaling. We found TFET with L g = 13nm, has SS of 60mV/dec and improved I ON /I OFF ratio but limited I ON is the main drawback of it [32]. In the recent years, new class of device which having steep subthreshold slope device has been proposed called negative capacitance FETs. There characteristics is mainly depend upon the structure on which we apply the negative capacitance concept. In FDSOI based NCFET at L g = 20nm we found SS as 56mV/dec and improved I ON /I OFF ratio of 10 5 [31]. We obtained good results but I ON /I OFF ratio is little less. In our proposed work we improve both SS and I ON /I OFF ratio by using PGP type structure for NCFET. We found SS as 50mV/dec and improved I ON /I OFF ratio of 10 8 which makes this device suitable for low power applications.

Conclusions
Through this work we investigate PGP-SELBOX NC FET which is advantageous in terms of design and performance (low power and better heat dissipation) and improves SCEs by inclusion of PGP. For this device, analysis for capacitance matching has been carried out by varying different ferro-electric parameters like coercivity( E C ), polarization (P r ) and FE layer thickness (t fe ) at L g = 30 nm and V d = 0.7 V. This proposed device has superior I ON I OFF ratio of 10 8 and SS of 50 mV/dec at optimized values of E C (1.4 MV/cm), P R (6.5 μC/cm 2 ) and t fe (5 nm). We also analyzed the R PE factor and found that for same R PE , current characteristics and SS are approximately same due to similar capacitance matching. In addition we studied about short channel effects like reverse DIBL and V th roll off and examine their effect with ferro-electric thickness (t fe ). The obtained performance analysis of the proposed device make it suitable for low power operations especially when we taken single gate architecture FETs.
(Author 2) provided the necessary support regarding simulation and data interpretation. Chitrakant Sahu and Menka (Author 3 and 4) supervised the work and made important discussions and modifications to the final manuscript.
Funding The authors have not received any funding for this work.

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Ethics approval and consent to participate Informed consent was obtained from all individual participants included in the study.

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