The conventional format for a singleprecision binary integer still consists of 23 bits: the sign bit (S), the exponent (E), the next eight bits, and the mantissa or fractional component. Figure 4 shows the IEEE 754 standard for single precision floating point numbers.
$$FP No.={(1)}^{s }\times {2}^{exponentbias}\times (1+mantissa)$$
The leftmost of the 23 bits is known as the binary point in the mantissa o01r fractional component. Because the leftmost bit (MSB) of every binary integer is always a 1, the mantissa does indeed contain 24 bits. Therefore, even if this 1 doesn't really occupy a bit of position, it is nevertheless considered to be present.
The biased exponent, which is represented by the exponent's eight bits, is created by multiplying the real exponent by 127. The bias's goal is to enable extremely big or extremely small numbers without the need for a separate sign bit for exponents. The skewed exponent permits real exponent values in the range of 126 to + 128.
Take the binary digits 1011010010001. By first moving the binary point 12 places to the left and then multiplying by the proper power of two, it can be written as 1 plus a fractional binary number. For example, 1011010010001 = 1.011010010001 212.
The sign bit (S), if this is a positive value, is set to 0. By multiplying the exponent by 127, 12 becomes an exponent skewed (12 + 127 = 139). The biassed exponent is represented by the binary number 10001011. The fractional portion (M) of the binary number, 011010010001, is the mantissa. The binary number's floating point representation is given by,
Four distinct units can be used to split the multiplier for floating point numbers stored in IEEE 754 format:

Unit of Mantissa Calculation

Unit for Calculating Exponents

Unit for Calculating Signs

Unit of Control
The Mantissa Calculation Unit requires a 24bit multiplier. This unit will be implemented using the Vedic Multiplication method. The 16 sutras, sometimes referred to as Vedic aphorisms, are the basis of the Vedic multiplication system and provide straightforward answers to a wide range of mathematical problems.. The Urdhvatriyakbhyam sutra, one of these 16 Vedic sutras, is appropriate for this use. This approach lessens the time by concurrently generating the partial products and makes this process quick. The exponent computation unit is implemented using the 8BIT Inexact Adder. The control unit raises the flag when NaN (not a number), Infinity, zero, underflow, and overflow problems are discovered.
The control unit raises the relevant flag when the case occurs. The numerous cases and flags that comprise them include:

If f 0 and e = 255, then NaN.

If e = 255 and f = 0, Infinity results.

The number is (1)S 2((e127)) (1 f) if 0 e 255. (Normalized numbers)

If e = 0 and f 0, then (1)S 2 ((126)) occurs. (0 · f) (DE normalised numbers) Zero is the case if e = 0 and f = 0.
UrdhvaTriyakbhyam Sutra
The Urdhva Tiryakbhyam Sutra (Fig. 4) is a universal multiplication formula that applies to all multiplication circumstances. Its literal translation of "vertically and transversally". It is founded on a cuttingedge idea that enables the development of all partial items. Then these incomplete products can be added simultaneously. As a result, the development of partial items and their entirety is paralleled.
Since the Urdhva Tiryakbhyam sutra (method) may be used in all multiplication scenarios, it was chosen to use it. Without applying the Urdhva Tiryakbhyam sutra, two are multiplied vertically and transversely; vertically refers to multiplying right above the multiplication and adding the result. Therefore, using this method, any multibit multiplication can be reduced to singlebit multiplication and addition (Fig. 3). Additionally, when a partial product is created, the carry propagation from LSB to MSB is reduced.
The Mantissa compute unit's performance predominates over the floatingpoint multiplier's total performance. The 32*32 BIT multiplication required by this unit calls for an unsigned multiplier. This unit will be implemented using the Vedic Multiplication methodology. In terms of power and speed, this strategy seems promising [8]. The objective is to channel each unit enough times to increase the Multiplier's speed. Speed and performance grow along with the pipeline's stage count.
2x2Vedic Multiplier:
Each multiplicand in a 2x2 bit multiplier has two bits, while the result contains four bits. As a result, although input's input range is (00) to (11), output is the set of (0000, 0001, 0010, 0011, 0100, 0110, and 1001). The multiplication occurs via “Urdhva Tiryakbhyam”, as shown in Fig. 4. In this case, multiplicands a and b are both assumed to be (10).
Figure 5 shows how 2x2 multiplier blocks are realised in hardware. Suppose a1 and a0 are two 2bit binary values, and b1 and b0 are their product.
q0 = a0.b0
q1= (a1*b0) + (a0*b1)
q2= (a1*b1) + Ci
q3 = C0
The block diagram for the 32*32 Vedic multiplier representation used in VLSI design is shown in Fig. 6. Utilizing Verilog, this multiplier's structural design. The first Vedic multiplier used in this paper is a 2x2 multiplier. Four 2x2 Vedic multipliers are used to create the 4x4 Vedic multiplier. Four 4x4 Vedic multipliers are then used to create the 8x8 Vedic multiplier. Four 8x8 Vedic Multipliers are combined to create the 16x16 Vedic Multiplier. Last but not least, four 16x16 Vedic multipliers make up the 32x32 Vedic multiplier.