A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS

doi:10.21203/rs.3.rs-2229329/v1

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A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS

https://doi.org/10.21203/rs.3.rs-2229329/v1

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This paper presents a continuous-time linear equalizer (CTLE) with an active inductor load simultaneously connected in parallel to low frequency branch. The equalizer uses two-stage CTLE, the first stage compensating for high-frequency (HF) attenuation and the second stage equalizer compensates medium-frequency (MF) and HF by parallel low-frequency branches. The MF stage is used for the long-tail Intern symbol interference (ISI) equalization to minimize residual ISI. Equalizer with voltage control capacitor to configure the distribution of zero poles, for the HF has a configurable range of 0.5dB.The low-frequency gain can be configured by changing the load current of the active inductor to reduce the effect of parasitic resistance on the layout. The layout size is 5.9um*6um based on a 28nm CMOS process. The post layout results show that the equalizer has a maximum compensation capability of 10.37dB at a rate of 20Gb/s with an eye width of 0.85UI.

Equalizer

Continuous-time linear equalizer (CTLE)

Active inductor

Intern symbol interference (ISI)

As the data rate increases in a high-speed serial link demand for high speed chip-to-chip data communication links.[1][2][3] However, due to skin effects and dielectric losses in the channel, the high-speed serial signal is severely attenuated and distorted after passing through the lossy channel.[4] The solution is to add separate equalization circuits at the transmitter and receiver ends to compensate for the high frequency loss of the channel and to improve data integrity.[5][6]

In receive (RX) combination of CTLE and decision feedback equalization (DFE) is widely used to eliminate ISI, The signal received from the channel is first compensated for high-frequency attenuation through CTLE, and the compensation effect directly affects the subsequent DFE equalization effect.[7]

Due to the increase in transmission rates, the traditional CTLE compensation for high frequency signals is no longer able to meet the requirements of high speed rates. Therefore various CTLE improvement structures have been proposed literature [8] uses the bulk voltage of the MOSFET to regulate its threshold voltage while using a negative impedance converter at the second stage node to regulate the medium-frequency (MF) losses, but the overall area of the equalizer is large due to the use of passive inductor peaking techniques as the load of the two stages. In [9], the proposed equalizer is realized with a common gate topology, which can effectively improve the bandwidth but the structure is more complex and occupies more area due to the parallel connection of too many resistors and capacitors; In [10], it uses a folded common source and common gate topology to improve the high frequency gain of the equalizer, but the equalized data rate is low and the gain improvement is not obvious.

In this paper, an active inductor CTLE with a rate of 20Gb/s for a high loss channel is designed in the UMC28nm process. The active inductor structure used in the equalizer significantly reduces the layout area compared with the peak load of the passive inductor. Meanwhile, a two-stage structure is used to compensate the loss signal at high frequency. In the second stage, a low-frequency parallel branch is added to the CTLE to recompensate the medium-high frequency, and a configurable module is added to the load side and feedback loop to adjust the compensation range of high and low frequency. Simulation results show that the equalizer has good equalization effect at 20Gb/s rate, and can be used in SerDes system of high-speed signal transmission.

2.1 Channel Simulation

The data is transmitted through the channel to the receiver for processing. But due to the dielectric loss, skin effect and other factors, The channel show low-pass characteristics with a large attenuation in high-frequency component.[11][12] Fig. 1 shows the frequency response curve of the channel applied in this paper. It has an attenuation of 10.39 dB at the Nyquist frequency of 10 GHz.

Through the generation of a pseudo-random sequence of numbers at a rate of 20Gb/s at the transmitter, the eye diagram of the signal generated after the data passes through the channel shown in Fig. 2. Its eye diagram is closed and there is a no apparent eye height or eye width.

2.2 Analysis of conventional CTLE

Figure 3 shows the circuit structure of a conventional CTLE. The equalizer is a negative feedback circuit formed by the parallel connection of the source resistor ${R}_{S}$ and capacitor ${C}_{S}$.[13] The feedback loop provides a high-pass path for the input signal, boosting the overall system's high-frequency gain and compensating for the losses suffered when passing through the channel.[14][15]

shows in Fig. 4 in half small-signal equivalent circuit. The transfer function is given as Eq. (1).

$$H\left( s \right)=\frac{{{g_m}{R_D}\left( {{R_s}{C_s}S+1} \right)}}{{\left( {\frac{{{g_m}{R_s}}}{2}+{R_s}{C_s}S+1} \right)\left( {{R_D}{C_D}S+1} \right)}}$$

According to (1) it has a zero and the two poles.

$${z_1}=\frac{1}{{{R_s}{C_s}}}$$

$${p_1}=\frac{{1+{g_m}{R_S}/2}}{{{R_s}{C_s}}}$$

$${p_2}=\frac{1}{{{R_D}{C_D}}}$$

The low frequency gain of the equalizer is

$${A_0}=\frac{{ - {g_m}{R_D}}}{{1+{g_m}{R_S}/2}}$$

The overall gain improvement is

$${A_{imp}}=\frac{{{p_1}}}{{{z_1}}}=1+{g_m}\frac{{{R_S}}}{2}$$

The gain of the circuit is proportional to $Rs$ and ${g}_{m}$, while the low frequency gain is inversely proportional to $Rs$. To increase the gain of the circuit requires an increase in the gm of the differential pair of tubes, which will result in an increase in the parasitic capacitance of the circuit and a smaller pole, and will not provide better equalization when processing data at high rates.

2.3 Analysis of active inductor CTLE

2.3.1 Equalizer architecture analysis

Due to the limitations of the conventional CTLE[18][19], in order to improve the high frequency gain of the equalizer, this paper proposes a CTLE with a two-stage active inductor load and a combination of high and low frequency branches in parallel.

The active inductor CTLE circuits is shown in Fig. 5. The signal is equalized by a two-stage CTLE operation, where the first stage equalizes the high frequency (HF) of the data and the second stage equalizes the high and low frequencies of the signal.

Passive inductor cresting techniques with additional loads in series have also been proposed in previous equalizer designs. Adequate bandwidth of the circuit is achieved through inductor peaking, effectively extending the circuit's operating frequency. However, the larger area of the passive inductor has a larger parasitic resistance, and the longer connection length in the layout design also creates a larger parasitic capacitance, which has a greater impact on performance in high-speed systems. This paper proposes the use of active inductors as a load technique to improve the previous circuit.[20]This technique can significantly reduce the area of the circuit and can also effectively extend the operating frequency of the circuit.

When a large gain boost is achieved using a single stage CTLE, the high frequency response will have a large steep spike that will damage the transmitted signal. After a comprehensive consideration of area, power consumption and performance the overall equalizer circuit uses a two-stage CTLE circuit cascaded to equalize the data through both stages.

The main design difficulties of the equalizer in this paper are 1) the need to design the overall zero-pole distribution due to the addition of the corresponding zero-pole circuit. 2) The equalizer is based on the UMC 28nm process with large deviations and is susceptible to the effects of process angle and temperature, making the circuit less robust. The voltage control capacitors introduced at the source are used to regulate the high-frequency side; the current control of the active inductor is used to regulate the gain at the low-frequency side.

2.3.2 Equalizer circuit analysis

The first stage of the equalizer has the same structure as the HF in the second stage, and this paper focuses on the second stage due to its higher circuit complexity. Figure 5 shows Circuit structure of the active inductor CTLE. The circuit introduces two new zeros for increasing the high frequency component of the circuit.

Active inductor CTLE can be divided into 1) an amplification stage consisting of ${M}_{H1}$, ${M}_{H2}$, ${M}_{L1}$ and ${M}_{L2}$ transistors, where the ${M}_{H1}$ and ${M}_{H2}$ transistors are the high frequency branches of the circuit and the ${M}_{L1}$ and ${M}_{L2}$ transistors are the low frequency branches of the circuit. 2) ${M}_{3}-{M}_{6}$ transistors are the active inductor part of the circuit. The active inductor generates

$$H\left( s \right)=\left[ {\frac{{{g_{m1}}\left( {{R_s}{C_s}S+1} \right)}}{{{g_{m1}}{R_s}+{R_s}{C_s}S+1}}+\frac{{{g_{m2}}\left( {{R_s}{C_s}S+1} \right)}}{{5{g_{m2}}{R_s}+5{R_s}{C_s}S+1}}} \right]\cdot \frac{{\left( {{R_L}{C_{gd}}S+{R_L}{C_L}S+1} \right){C_d}}}{{{R_L}{C_L}+\left[ {\left( {{R_L}{C_{gd}}S+1} \right){C_d}{C_L}+{R_L}\frac{{{C_L}}}{{{r_0}}}} \right]S+\left( {{R_L}{C_{gd}}S+1} \right)\left( {{C_d}{g_{m{p_1}}}+1} \right)}}$$

additional zeros for the circuit, while ${M}_{5}$ and ${M}_{6}$ transistors generate part of the current through the bias circuit, increasing the voltage margin of the circuit. The overall equalizer low frequency gain value can also be adjusted by controlling the bias current to reduce the impact of parasitic parameters on the circuit performance

3) The capacitor ${C}_{S}$ in the source negative feedback loop uses a voltage control capacitor in the 28nm process to adjust the high frequency gain of the equalizer by controlling the voltage.

The CTLE small-signal equivalent circuit is shown in Fig. 6. The transfer function of the equalizer is given as Eq. (7).

The three zeros and two poles of the circuit are derived from (7) as

$${z_1}=\frac{1}{{{R_s}{C_s}}}$$

$${z_2}=\frac{1}{{5{R_s}{C_s}}}$$

$${z_3}=\frac{1}{{{R_g}\left( {{C_{gs}}+{C_{gd}}} \right)}}$$

$${p_1}=\frac{{1+{g_{m1}}{R_s}}}{{{R_s}{C_s}}}$$

$${p_2}=\frac{{1/5+{g_{m2}}{R_s}}}{{{R_s}{C_s}}}$$

The introduction of an active inductor load produces an additional zero for the circuit, while the combination of low and medium frequency circuits separates the zeros of the output function by a ratio of 5:1, producing another additional zero. Significant enhancement of the circuit's high frequency gain with the three zeros.

The input signal is balanced by a cascade of two equalization modules to enable the overall system to meet the 20Gb/s transmission requirements.

The layout of the equalizer is shown in Fig. 7, using the UMC 28nm process with a layout size of 5.9µm * 6µm. The layout is centered and symmetrical while reducing the length of the alignments, and the input pairs are symmetrically placed so that the overall layout is co-centered.

The frequency response simulation analysis of active inductor CTLE with conventional CTLE, after the first stage of CTLE with conventional CTLE, is shown in Fig. 8.

The first stage of the equalizer first lifts the high frequency band, and the curve shows that the gain improvement at 10 GHz after the first stage is 4.77 dB. The image also shows that the CTLE with active inductors as load has a better high frequency compensation effect than the conventional CTLE.

The second stage of the circuit re-equalizes both high and low frequencies by connecting low frequency branches in parallel. In order to reduce the effect of the parasitic capacitance extracted from the plate on the high frequency compensation effect of the circuit, a variable capacitor device is introduced into the circuit feedback loop, whose voltage control capacitance changes the zero pole in the overall loop, thus adjusting the high frequency compensation capability of the equalizer. The specific simulation results are shown in Fig. 9, where the voltage varies from 0.3v to 1.1v with an adjustable range of 0.5dB at the Nyquist 10GHz band. The figure shows that a gain of approximately 10.37 dB is achieved for the signal after two stages of equalization, and that the compensation of the CTLE equalizer meets the channel attenuation.

The equalizer is also designed with another configurable method of improving the plate and post-emulation excess parasitic coefficients. The resulting attenuation in the low frequency band can be changed by biasing the currents in the M5 and M6 transistors to change the overall equalizer low frequency gain. The configurable low frequency gain is shown in Fig. 10. As the bias current increases, the low-frequency gain of the equalizer becomes correspondingly larger.

The eye diagram of the signal after passing through the two-stage series CTLE circuit is shown in Fig. 11. In comparison with Fig. 2it can be observed that the signal integrity is significantly improved after passing through the equalizer, and the eye width and height of the signal are noticeable. From an initially difficult to identify jumbled signal, the desired output waveform is gradually derived. The equalizer used in this paper achieves a high rate of transmission while providing a greater boost to high frequencies than a conventional CTLE and saves more area than a CTLE with passive inductor peaking.

Table 1

shows the results of comparing the equalizer in this paper with those of other structures. COMPARISON RESULTS WITH PREVIOUS WORKS
Parameter	[8]	[9]	[10]	This work
Technology/nm	130	65	NA	28
Data rate/(Gb/s)	10	15	2.125	20
Channel loss/dB	12	12	8	10.37
Supply Voltage /v	1.2/0.7	1.1	1.8	1.2
Eye opening	0.38UI	0.75UI	0.87UI	0.85UI
Area	0.35${mm}^{2}$	700${\mu m}^{2}$	NA	35.4 μm²

In this paper, a two-stage CTLE based on active inductor load parallel low-frequency branched is designed. This equalizer introduces a new zero pole with greater high-frequency gain compared to the conventional CTLE, while the high and low-frequency gains can be adjusted by two adjustable modules, respectively, to provide significant equalization of the signal output from a heavily loss channel at 20 Gb/s high-speed data rate. The simulated eye diagram has a good eye height and eye width. At the same time, the design of the equalizer in this paper greatly reduces the chip area by using an active structure compared to the previous CTLE with passive inductors as the load, and at the same time can obtain a stable equalization effect.

Competing interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Authors' contributions Chunming Zhang was responsible for the overall architecture design and index allocation; Yibo Wang was responsible for the simulation verification and paper writing of circuit level design; Hao Wang and Yangzhen Xu were responsible for the layout design verification. All authors reviewed the manuscript.

Acknowledgements This research was sponsored by National Key R&D Program for Broadband Communications and New Networks Key Special Project (2019YFB1803600).

Data Availability The datasets analyzed during the current study are available from the corresponding author on reasonable request.

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No competing interests reported.

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You are reading this latest preprint version

A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS

Status:

Version 1

Abstract

Figures

1 Introduction

2 Equalizer Analysis And Design

2.1 Channel Simulation

2.2 Analysis of conventional CTLE

2.3 Analysis of active inductor CTLE

2.3.1 Equalizer architecture analysis

2.3.2 Equalizer circuit analysis

3 Layout And Simulation Results

4 Conclusion

Declarations

References

Additional Declarations

Status:

Version 1