## 2.3.1 Equalizer architecture analysis

Due to the limitations of the conventional CTLE[18][19], in order to improve the high frequency gain of the equalizer, this paper proposes a CTLE with a two-stage active inductor load and a combination of high and low frequency branches in parallel.

The active inductor CTLE circuits is shown in Fig. 5. The signal is equalized by a two-stage CTLE operation, where the first stage equalizes the high frequency (HF) of the data and the second stage equalizes the high and low frequencies of the signal.

Passive inductor cresting techniques with additional loads in series have also been proposed in previous equalizer designs. Adequate bandwidth of the circuit is achieved through inductor peaking, effectively extending the circuit's operating frequency. However, the larger area of the passive inductor has a larger parasitic resistance, and the longer connection length in the layout design also creates a larger parasitic capacitance, which has a greater impact on performance in high-speed systems. This paper proposes the use of active inductors as a load technique to improve the previous circuit.[20]This technique can significantly reduce the area of the circuit and can also effectively extend the operating frequency of the circuit.

When a large gain boost is achieved using a single stage CTLE, the high frequency response will have a large steep spike that will damage the transmitted signal. After a comprehensive consideration of area, power consumption and performance the overall equalizer circuit uses a two-stage CTLE circuit cascaded to equalize the data through both stages.

The main design difficulties of the equalizer in this paper are 1) the need to design the overall zero-pole distribution due to the addition of the corresponding zero-pole circuit. 2) The equalizer is based on the UMC 28nm process with large deviations and is susceptible to the effects of process angle and temperature, making the circuit less robust. The voltage control capacitors introduced at the source are used to regulate the high-frequency side; the current control of the active inductor is used to regulate the gain at the low-frequency side.

## 2.3.2 Equalizer circuit analysis

The first stage of the equalizer has the same structure as the HF in the second stage, and this paper focuses on the second stage due to its higher circuit complexity. Figure 5 shows Circuit structure of the active inductor CTLE. The circuit introduces two new zeros for increasing the high frequency component of the circuit.

Active inductor CTLE can be divided into 1) an amplification stage consisting of \({M}_{H1}\), \({M}_{H2}\), \({M}_{L1}\) and \({M}_{L2}\) transistors, where the \({M}_{H1}\) and \({M}_{H2}\) transistors are the high frequency branches of the circuit and the \({M}_{L1}\) and \({M}_{L2}\) transistors are the low frequency branches of the circuit. 2) \({M}_{3}-{M}_{6}\) transistors are the active inductor part of the circuit. The active inductor generates

$$H\left( s \right)=\left[ {\frac{{{g_{m1}}\left( {{R_s}{C_s}S+1} \right)}}{{{g_{m1}}{R_s}+{R_s}{C_s}S+1}}+\frac{{{g_{m2}}\left( {{R_s}{C_s}S+1} \right)}}{{5{g_{m2}}{R_s}+5{R_s}{C_s}S+1}}} \right]\cdot \frac{{\left( {{R_L}{C_{gd}}S+{R_L}{C_L}S+1} \right){C_d}}}{{{R_L}{C_L}+\left[ {\left( {{R_L}{C_{gd}}S+1} \right){C_d}{C_L}+{R_L}\frac{{{C_L}}}{{{r_0}}}} \right]S+\left( {{R_L}{C_{gd}}S+1} \right)\left( {{C_d}{g_{m{p_1}}}+1} \right)}}$$

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additional zeros for the circuit, while \({M}_{5}\) and \({M}_{6}\) transistors generate part of the current through the bias circuit, increasing the voltage margin of the circuit. The overall equalizer low frequency gain value can also be adjusted by controlling the bias current to reduce the impact of parasitic parameters on the circuit performance

3) The capacitor \({C}_{S}\) in the source negative feedback loop uses a voltage control capacitor in the 28nm process to adjust the high frequency gain of the equalizer by controlling the voltage.

The CTLE small-signal equivalent circuit is shown in Fig. 6. The transfer function of the equalizer is given as Eq. (7).

The three zeros and two poles of the circuit are derived from (7) as

$${z_1}=\frac{1}{{{R_s}{C_s}}}$$

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$${z_2}=\frac{1}{{5{R_s}{C_s}}}$$

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$${z_3}=\frac{1}{{{R_g}\left( {{C_{gs}}+{C_{gd}}} \right)}}$$

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$${p_1}=\frac{{1+{g_{m1}}{R_s}}}{{{R_s}{C_s}}}$$

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$${p_2}=\frac{{1/5+{g_{m2}}{R_s}}}{{{R_s}{C_s}}}$$

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The introduction of an active inductor load produces an additional zero for the circuit, while the combination of low and medium frequency circuits separates the zeros of the output function by a ratio of 5:1, producing another additional zero. Significant enhancement of the circuit's high frequency gain with the three zeros.

The input signal is balanced by a cascade of two equalization modules to enable the overall system to meet the 20Gb/s transmission requirements.