The optical majority gate is designed based photonic crystals in a 13×13 square structure with silicon rods with a refraction index of 3.4 in an air background (refraction index of 1). As shown in Fig. 2, this gate has 4 waveguides and one resonance ring, including three inputs and one output. The radius of the rods is 0.18a and the lattice constant is a = 0.64. Also, the radius of the 4 rods have decreased at the point where the waveguides are connected to the resonance ring. Two rods are reduced to 0.6r, one is reduced to 0.7r, and the output waveguide rod is reduced to 0.56r. The input optical source (B) has a phase difference of -20. The simulations demonstrated that such a phase difference improves the simulation results.
The operating wavelength of this gate is 1.55um. Since the photonic crystals operate based on the photonic band-gap, this wavelength is in the range of the photonic band-gap of this gate. Figure 3 shows the photonic band-gap diagram of the majority gate. As can be seen, there are two forbidden wavelength intervals, where 1.55 is in the range of 1.39 to 1.88µm.
According to the truth table, 8 states can be defined for this gate, which are studied here.
If all three inputs are 0, since no source is on, the output would be 0. If any of the inputs becomes 1, while the other two inputs are 0, the output remains 0. Figures 4 to 6 show these three states. In these figures, part “a” shows the optical power distribution and part “b” shows the optical power transmitted to the output. As can be seen in Fig. 4, if A = 1, B = 0, C = 0, the output is 0.16, which is close to 0 and can be considered as the logical value of 0.
When A = 0, B = 1, C = 0, the output is about 0.18. Figure 5 shows the power distribution and output power in this state. This value is considered as 0 logic.
Figure 6 also shows power distribution and output power for A = 0, B = 0, and C = 1. In this state, the output power is 0.16, which is equal to logic 0.
According to the truth table, if more than 1 input is 1, the output would be 1, and 4 states can be defined in this case. If A = B = 1, C = 0, the output is 0.65, as shown in Fig. 7. In this state, the output is 1.
If A = C = 1, B = 0, the output is 0.7, which can be considered as the logic 1. Figure 8(a) shows power distribution and Fig. 8(b) shows the output power.
If A = 0, B = C = 1, the output is 0.7, which is equal to the logic 1. Figure 9 shows simulation results and the output values.
It is obvious that if all inputs become 1 simultaneously, the output would be 1. Simulation results for A = B = C = 1 are given in Fig. 10. As can be seen in Fig. 10(b), the output power in this state is about 1.8, which can be considered as logic 1.
According to the simulation results, the above structure behaves according to the truth table; in all states that the output in the truth table is 0, the output power is very low, and in all states that the output in the truth table is 1, the output power is high. Therefore, this structure can be used as a majority gate with three inputs. The results show that the power in logics 0 and 1 is low and high, respectively. Therefore, this optical gate has a high accuracy in detecting logical values. Among other advantages of this structure, its small size can be mentioned, which makes it suitable for optical integrated circuits.