Au–Ag binary alloys on n-GaAs substrates and effect of work functions on Schottky barrier height

In this study, I investigated the effect of work function (ϕm) of AuxAg1−x (x = 0, 0.22, 0.37, 0.71 and 1) on the Au–Ag/n-GaAs Schottky diode (SD) parameters. Ag, Au metals and three alloys with different compositions deposited on n-GaAs substrates by the thermal evaporation method. Surface morphologies of the samples were investigated by an atomic force microscope (AFM). Elemental compositions of Schottky contact metals were conducted by energy dispersive X-ray spectroscopy (EDX). Current–voltage (I–V) and capacitance–voltage (C–V) measurements were performed at room temperature. SD parameters such as barrier height (Φb0), ideality factor (n), series resistance (Rs), and interface state density (Dit) of the SD’s were calculated from the obtained I–V and C–V data. Experimental results showed that all calculated SD parameters depend on the alloy composition. The lowest mean barrier height value was found as 0.789 ± 0.022 eV for Au/n-GaAs SDs and the highest value was determined 0.847 ± 0.008 eV for Au0.71Ag0.29/n-GaAs SDs from I–V measurements. Weak dependencies of barrier height to ϕm existed and gap state parameter (S) determined as 0.0526. The S value was close to the Bardeen limit (S = 0) and indicates that the Fermi level was strongly pinned in Au–Ag/n-GaAs SDs. Also, main SD parameters like series resistance (Rs), ideality factor (n), reverse bias barrier height (ΦbRB), doping density (Nd) and density of interface states (Dit) were calculated via using different methods from I–V and C–V measurement results. Also, to determine the leakage current mechanism Poole–Frenkel emission (PFE) and Schottky emission (SE) models applied on reverse bias I–V data.


Introduction
Barrier formation mechanisms of metal-semiconductor contacts have been a major research topic since the first discovery of these contacts [1][2][3][4]. In order to accurately identify the current flowing through the contact and determine the operating conditions of the devices, the basic parameter, barrier height (Φb), have to be defined correctly. First attempt was realized by Schottky to understand the rectifying behavior of metal-semiconductor contacts [5]. Schottky and Mott subsequently proposed a model for barrier formation and calculating the barrier height [5][6][7]. According to the Schottky-Mott rule [7], under the ideal condition, the factors affecting this barrier height was an electron affinity of the semiconductor (χs) and the work function of metal (ϕm), and it was simply expressed as follows; Since Schottky-Mott rule is almost never verified experimentally, it can be concluded that; interface dipoles do not disappear and play a major role in determining the properties of the metal-semiconductor interface [8]. The ϕm value of the metal depends on two components; volume term and surface dipole term, which starts just below the surface of the metal and represents where all bulk properties are same. Both dipole terms strongly correlate with surface charge distribution and depend on the condition of the surface [9]. Moreover, it was commonly known that, when a metal and semiconductor are brought into a contact without any interface layer, the atomic sites and charge distributions change, so that the contribution of the surface dipole changes. Louie et al. to overcome this situation, used the metal's electronegativity instead of the function of the metal [10]. In addition, in the presence of states at the interface has a significant effect on the formation of barrier height and investigated in many studies [2,7,8,[11][12][13][14][15].
Although Schottky-Mott rule provides accurate estimation of band bending in a semiconductor, the validity of the proposed model, due to the presence of states at the interface between the metal and the semiconductor and the "Fermi level pinning" caused by these finite states, is a matter of discussion especially for some semiconductors [2,16]. According to this model, if the thin insulating layer exists between a semiconductor and a metal, interface states of semiconductor are occupied by the electrons, create additional space charge region, and create potential difference. This potential difference reduces the effect of metals work function on barrier height [16]. Experimentally observed barrier height has a very limited relation to the results of this theory [8,14,17]. Few models proposed to reveal the formation of barrier height in a metal semiconductor contact [2,11,18]. Some of these models associate the independence of the barrier height from the ϕm with the fermi level pining mechanism caused by high density interface states [2]. Some other models are closely interested in interfacial chemistry and address the interaction of interfacial dipole with bond polarization [11]. However, all proposed models haven't yet emerged to explain the properties of metal-semiconductor contacts precisely, are not complete and usually changes with the substrate, metal, substrate cleaning method, metal deposition method, etc. [9]. It is possible to determine the diode parameters (tuning) during the production of diodes to serve a specific purpose. It is sufficient to use metals or semiconductors with different work functions [9,13,19,20].
GaAs has high thermal strength, high electron mobility and high resistance to radiation damage. It also has a direct band gap that allows efficient absorption of light emission and absorption, allowing transistors to operate at very high frequencies, reducing the noise at which higher frequencies tend to reduce electrical signal distortion in electronic circuits. Also, ternary and quaternary alloys created from GaAs utilizing elements like Al, In, P, and SB have properties that complement those of GaAs, which allows adaptability. GaAs is an important substrate material for devices, which its used in both in micro-and opto-electronic applications. Also, GaAs is a suitable substrate for a basic components for high speed and low power electronics. On the condition that the properties of the semiconductor remain the same (assuming the effect of interface states to be invariant), modifications in the composition of Schottky metal should be expected to change the barrier height. Both of Au and Ag have very similar properties such as conductivity, molar heat capacity, crystal structure, atomic and covalent radius. They miscible in all portions and known as good contact properties with GaAs.
In this study, the effect of modification in the ϕm of Schottky metal was investigated by the depending on the composition of alloys. For this purpose, electrical measurements (currentvoltage and capacitance-voltage) were performed at room temperature on produced 20 Schottky barrier diodes (SDs) which it was fabricated by using two metals (Ag, Au) and three different alloys on n-GaAs. The characteristic parameters of SDs such as ideality factor (n), barrier height (Φb), series resistance (Rs), reverse bias barrier height (Φb RB ) etc. have been determined and compared with each other. Pinning position of the Fermi level and density of interface states (Dit) have been determined and the validity of the Schottky-Mott rule for the Au-Ag/GaAs was tested.
The n-type GaAs substrate used in this study was grown by the LEC method and Te-doped with a carrier concentration of 2-5x10 17 cm 3 . To remove organic contaminations on GaAs substrate, it was cleaned with some solvents (acetone, methanol, trichloroethylene, deionized water) 5 min using ultrasonic agitation in each step. Then, GaAs substrate was immersed in an HCl:H2O (1:1) etching solution to eliminate the thin native oxide layer on the surface, rinsed with de-ionized water (18 MΩ) and high purity nitrogen gas used for drying. After the etching process, GaAs substrate inserted into the metal deposition chamber immediately.
The Ohmic contacts and transfer length method (TLM) patterns were built by thermal evaporation of Au-Ge alloy (wt.% 12), on non-polished side of substrate with a thickness of 200 nm, at 2x10 -6 Torr base chamber pressure and thermally annealed at 350 °C for 2 min. in flowing high purity (5N) nitrogen gas in a tube furnace. TLM method [21] was used to characterize the electrical contacts, with gaps of 0.25, 0.50, 0.75 mm between 0.7x3.5 mm pads. Specific contact resistance (ρc), contact resistance (Rc), and the effective length (Leff) derived from the measured I-V data and the calculated total resistance versus gap spacing by TLM and values was 9.899x10 -6 Ωcm 2 , 0.510 Ωcm and 0.770 μm, respectively.
The substrate divided into 5 parts and the area of each part was approximately 1 cm 2 . Each part immediately inserted into the vacuum chamber of NVTS-400 to form Schottky contacts by thermal evaporation of metals and alloys. The AuxAg1-x alloys made at tungsten crucibles, using a high purity Au (4N5) and Ag (5N) parts, repeating the melt-cooling cycle at least five times and under vacuum. Alloy composition (x=0, 0.22, 0.37, 0.71 and 1) was verified by EDX measurements and given in Table 1. Schottky contact metals/alloys thermally evaporated through a tungsten shadow mask on the front side of the wafers with diode area was 0.785 mm 2 . Electrical characteristics of Au-Ag/n-GaAs SDs studied from dc current-voltage (I-V) measurements (measured with the HP4140B picoammeter) and frequency dependent capacitance-voltage (C-V) measurements (measured with Agilent E4980A LCR meter) in the dark and 300 K. The forward and reverse bias I-V measurements evaluated using the standard thermionic emission theory, and Poole-Frenkel and Schottky emission theory. C-V measurement results were also evaluated using diode capacitance, and single frequency approximation for interface state density distribution model. All measurements and calculations performed with our SeCLaS-PC program [22,23].

Work functions and surface morphology of binary Au-Ag alloy
The work function was one of the most basic properties of material surfaces and it is directly affects electrical properties of metal-semiconductor contacts. Although the work functions of metals are well documented for various elements, information about the work functions of alloy surfaces and its dependence on composition is limited [24]. Segregation, especially in alloys, makes it difficult to determination of work functions of the alloys [25]. Generally, Gelatt and Ehrenreich's model is used for determine the work function of the alloy [31][32][33][34] in the experimental studies. According to this method, the work function of an alloy in the form of AxB1-x was, where and are total densities of states , and , are the work functions, and of metal A and B, respectively. The density of states at Fermi level depends on electronic specific heat constant = (1 3 ⁄ ) 2 2 . Ce values of Au and Ag are 0.948 and 0.645 mJmol -1 K -2 , respectively [26]. Contrary to the model proposed by Fain et al. [31], since this electronic specific heat constant values was not close to each other, so work functions could not show a linear variation. When the work functions considered as 5.22 eV and 4.30 eV for Au and Ag [34], respectively, obtained work functions of alloys was given in Table 1 with the corresponding atomic composition.
Grain size of Schottky metals and condition of the surface of this metal/alloy plays an important role in determining the electrical properties [27,28]. Atomic force microscopy was used to examine the surface morphology of the Au-Ag Schottky contacts on n-GaAs. Figure 1 shows the AFM images of the Au/n-GaAs and Ag/n-GaAs SDs. As shown in Figure, surface morphology of the SDs was fairly smooth. Root mean square (RMS) roughness of films was found from 20x20 μm image area and values was 45.9 nm for Au, 37.8 nm for Au0.71Ag0.29, 46.2 nm for Au0.37Ag0.63, 29.5 nm for Au0.22Ag0.78 and 26.1 nm for Ag. Correlation was not observed between the RMS values of the alloys and metals. However, relatively high RMS values are the result of the island-type metallization process observed during the metallization process [29][30][31]. The phenomenon of island formation of metals is typically observed between low and high surface energy materials. In order to minimize the total surface energy of the system, the metals/alloys agglomerates to minimize its surface area and exposes more surface area of the low surface energy materials (surface energies were determined as 0.86 J/m 2 , 1.51 J/m 2 and 1.97 J/m 2 for GaAs, Ag and Au, respectively) [32].

Forward bias I-V characteristics of the Au-Ag/n-GaAs SDs
The semi-logarithmic forward and reverse I-V characteristics of one Au-Ag/n-GaAs SDs shown in Figure 2. As can be seen in Figure 2, the rectifying properties of the SD depend on the alloy composition and therefore they depend on the work function. These experimental plots analyzed by using thermionic emission theory, assuming the barrier was homogeneous. According to the theory, the flowing current through the diode in the forward bias region (for V ≥ 3kT/q) is as follows [7,33]; where I0, V, n, k, T, A * , A, q, and Φb IV are the saturation current at zero bias, the applied bias voltage, the ideality factor, the Boltzmann constant, the temperature in Kelvin, the effective Richardson constant (8.16 Acm -2 K -2 for n-GaAs), the effective diode area, the electron charge, and the barrier height, respectively. In Equation (4), n is a dimensionless parameter and its indicator for the deviation from the theory (ideally equals unity). The experimental values of the n and the Φb were determined from slopes and intercepts of the linear regions of the forward bias lnI-V plots by using Equations (3 and 4). Other calculations and all least square fittings performed via our computer program SeCLaS-PC. The values of the Φb and n of the Au-Ag/n-GaAs SD varied with alloy compositions ( Table 1). As can be seen in Table 1, the ideality factors of Au-Ag/n-GaAs SDs were higher than the 1. This high value of the ideality factors was generally attributed to an existence of a thin oxide layer between metal and semiconductor, surface preparation techniques, Fermi level pinning, and homogeneity of the surface of the semiconductor [28,34].
Ideally, when the metal and semiconductor are combined to form a contact, the boundary between the metal and the semiconductor is assumed sharp, but in real situation is different. As stated in previous studies, even if the metallization process carried out at room temperature, solid-state reactions occur between the metal and the semiconductor [29,31,[34][35][36]. This was more clearly seen in Au/GaAs SDs. Gallide phases formed at the interface was known and have a significant effect on both the n and the Φb IV [35,37]. In this study, similar results were obtained for n and the Φb IV and these values vary depending on the contact metal/alloy. The ideality factor of the alloys decreases when the amount of silver increases. The possible reason for this change may be silver prevents the formation of the gallide phases.
It was a well-known method to incorporate very thin barrier metal films in order to allow metals of such diffusive nature to make better contact with semiconductors or to achieve diffusion in a controlled manner.  [42,43].
The electrical parameters of the diodes depend on the method of cleaning of the substrates [45], the metallization method [46], the etching method [47] etc. Tsukamato et al. worked on photocatalytic properties of alloy (Au-Ag)/TiO2 junctions [19]. They founded that the work function of the Au-Ag alloy lies at the level intermediate between the monometallic Au and Ag and calculated theoretical energy-band diagram of alloy/TiO2 junction. According to their results, barrier heights changes 0.2 eV to 1.3 eV for Ag/TiO2 and Au/TiO2, respectively. The alloy/TiO2 junction therefore creates a barrier that is larger than Ag/TiO2 but smaller than Au/TiO2. This theoretical calculation does not take into account many parameters that have significant effects on the height of the barrier, such as presence of interface states, inhomogeneity, interface compounds, doping density etc. and defines the parameters in an ideal state. However, it is expected/founded to be compatible with the parameters obtained from the experiments. Therefore, it would be more appropriate to evaluate our diodes, which are prepared in identical form and built on the same substrate with the approach that they are consistent among themselves.
When this information was taken into consideration, the change in barrier heights depending on the were given in Figure 3. Here, the data related to Au/n-GaAs SD not taken into consideration when evaluating the relationship between metal's and Φb values. The expected barrier height values could not be observed due to alloying behavior. This behavior causes the AuGa compounds to change the interface chemistry of the Au-GaAs interface as a result of some Ga out-diffusion and solid-state reactions with Au, and the remaining As atoms make the semiconductor highly doped [35,37,48]. The exact alloying mechanism that causes the degradation of the SDs was not very clear. This will result in significant field emissions along the barrier and increase the flow through it [48].
This behavior also observed in studies on AlGaN or GaN substrates [29]. In this study, although there is no annealing process, Ga migration due to solid-state reactions also observed on the contact surface by EDX measurements. On the other hand, the presence of a small amount of Ag prevents this diffusion and prevents the gallide phases to occur at the interface [30,31]. There are many examples in the literature (especially in SD on ternary and quaternary semiconductor substrates) where a thin layer of metal barrier is used to prevent these diffusion/out-diffusion processes [49].
As mentioned earlier, the slope of linear fit in Φb versus graph was an indicator of Fermi level pinning and called as "interface behavior parameter" or "gap states parameter" (S) of the semiconductor [2,8]. Here, if S=0 state is called as a "Bardeen limit", if S=1 state is called "Schottky limit". S parameter was determined as 0.0526 and close to the Bardeen limit, in our study. Therefore, surface states or interface states stabilize the Fermi level of the metalsemiconductor system and, depending on the characteristic parameters of the metal, thus Fermi level remains unchanged. In this case, the relationship between the density of the interface states and the S parameter given as follow, where, and are permittivity of the interfacial layer and thickness of interfacial layer, respectively [2,34]. Assuming the =5 0 and =5 Ǻ, we calculate Dit=1.801x10 11 eVcm -2 from S according to the Equation (5), which has a good agreement with the later results and literature [50].
The downward curvature in I-V curves at relatively high forward bias voltage region arises from the series resistance (Rs), of the semiconductor bulk between the depletion region and Ohmic contact. The Rs values of Au-Ag/n-GaAs SD were calculated using two different methods developed by Cheung's [51] and Norde [52] obtained from the forward bias current equations (Equation 3-4). According to the Cheung and Cheung theory, the barrier height as well as other diode parameters such as n and Rs was also could be determined using Cheung's functions; and the y-axis intercept and slope of a plot of dV/d(lnI) vs. I give nq/kT and Rs. Also, a plot of H(I) vs. I give a straight line with the y-axis intercept equal to nΦb Ch (not plotted in here) The slope of this plots also provides a second determination of Rs, which can be used to check the consistency of Cheung's approach. The obtained Rs, n and Φb Ch of the SDs were given in Table  2. This serial resistance values were consistent with the literature [46,53] Table 2 also contains Norde method results. According to the Norde's method, Norde function (F(V)) were expressed as in Equation (7) and where I(V) and γ was a bias dependent current value obtained from the I-V plots and dimensionless integer larger than ideality factor (γ > n), respectively, and also barrier height (Φb N ) given by the where F(Vmin) was a minimum point value of F(V), Vmin and Imin corresponding voltage and current values. The plots of F(V) versus V for the Au-Ag/n-GaAs SDs using. Mean values of Φb N and Rs values of twenty Au-Ag/n-GaAs SD were summarized in Table 2.
As can be seen from Table 2, mean Φb and Rs values of SD for each set was found to be consistent with the Cheung's approach and Norde's method. Rs values of an intimate metalsemiconductor contact without any desired interfacial layer must only arise from the bulk. The higher values of Rs may be arise from the contribution of the native oxide layer on the semiconductor surface to the neutral region series resistance plus imperfect Ohmic contact. However, in the process of making Ohmic contacts and SD it has contributed to contact resistance in the alloys resulting from solid-state reactions [46]. Table 2. Mean characteristics diode parameters and standard deviations of the twenty (for each set) Au-Ag/n-GaAs SDs obtained from Cheung functions and Norde plots.
If there are interface states exist between metal and semiconductor and in equilibrium with semiconductor, the ideality factor of the SD will be greater than unity because of this conditions [16,54]. The density of these states ( ) expressed as following equation; Here, d and εs are the interfacial layer width and permittivity of the semiconductor, respectively. The depletion layer width was determined from the C-V measurements at a high frequency. Also, n(V) is the ideality factor depending on the bias voltage and given by ( ) = ( ⁄ ) ln( 0 ⁄ ). In an n-type semiconductor, the energy of the interface states Ess with respect to the top of the conduction band (Ec) at the surface of the semiconductor is given by where, qϕ = Φ + (1 − 1⁄ ) . Interface state density distribution profile of the s for Au-Ag/n-GaAs SDs were obtained from the experimental I-V plots and were shown in Figure 4. For all Au-Ag/n-GaAs SDs there was a slight exponential increment seen in from the nearly mid-gap towards the bottom of the conductance band. Furthermore, when the Ag content increased in the Schottky contact metal, the interface state density increases. This decreasing values are supports our proposed approach for interface chemistry by a Ga out-diffusion. Gallide phases causes a much lower interface state density.  vs. EC-ESS plots for Au-Ag/n-GaAs SDs.

Reverse bias I-V characteristics of the Au-Ag/n-GaAs SDs
Reverse bias I-V characteristics could also be used for determine some parameters of the fabricated Au-Ag/n-GaAs SDs. Figure 2 reveals that the reverse current (IR) of the Au-Ag/n-GaAs SDs increases with increasing bias, but not saturated. Different mechanisms cause a leakage current and becomes an effective. The reverse current conduction mechanism of Au-Ag/n-GaAs investigated based on the Poole-Frenkel emission (PFE) and Schottky emission (SE) models [33,55]. The reverse bias current as a function of the negative bias can be written as where I0R, βPF and Φb RB are reverse saturation current, PFE field-lowering coefficient and reverse bias barrier height (Φb RB ), respectively. The theoretical values of field lowering coefficients given by where βSE is the field-lowering coefficient of SE. According to Equation (11), the theoretical values of the field lowering coefficients (βPF * ) for the Au-Ag/n-GaAs SDs were determined as 4.412x10 −5 eVm 1/2 V −1/2 . Mean values of Φb RB and βPF values of twenty Au-Ag/n-GaAs SD were summarized for each set in Table 3. As can be seen from Table 3, values of experimental slope for the Au-Ag/n-GaAs SDs are changes from 1.375±0.068 eVm 1/2 V −1/2 to 1.560±0.209 eVm 1/2 V −1/2 , which were closely matched with the theoretical slope of SE. Thus, the dominating charge conduction mechanism for the Au-Ag/n-GaAs SDs are assumed the SE. Table 3. Mean characteristics diode parameters and standard deviations of the twenty (for each set) Au-Ag/n-GaAs SDs obtained from reverse bias I-V plots.

C-V characteristics of the Au-Ag/n-GaAs SD
The bias dependent C-V characteristics of the Au-Ag/n-GaAs SDs measured at dark and room temperature. Figure 5 shows a plot of C -2 as a function of bias voltage for the Au-Ag alloy (at.% 0-100) on n-GaAs SDs at sufficiently high frequency (1 MHz or above). The main purpose of these C-V measurements were reveal the properties of the space charge region of SDs. The relationship between the capacitance of the space charge region and the applied dc bias in metalsemiconductor contacts given as follows [7,12], where, Vbi was the built-in potential and Nd were the doping concentration of the GaAs substrate. According to the Equation (12) (1/C 2 ) versus V plots gives straight line with the slope were equals to 2/qεsNd and intercepts the x-axis equals to V0 ( Figure 5). Here; V0 is related with the built-in potential Vbi by the equation Vbi=V0+kT/q and barrier height were given by equation [7], where, Vn is the potential difference between the bottom of the conduction band and the Fermi level in the neutral region of n-GaAs and Vn=(kT/q) ln(Nc/Nd), where Nc is the temperature dependent density of states in the conduction band and its value was calculated from the Nc=2(2πm*⁄kT/h 2 ) 3/2 , and m*=0.063m0, and found 4.573x10 17 cm -3 for GaAs at 300 K. The values of Φb CV and Nd for the Au-Ag/n-GaAs SDs were given in Table 4. In Table 4, the barrier heights obtained by C-V method of the SDs were changes between the 1.035±0.022 eV and 0.912±0.013 eV. These obtained barrier height values are higher than obtained from I-V measurements for corresponding to each alloy composition. Arulkumaran et al. prepared Au/n-GaAs and Ag/n-GaAs SDs and barrier height values varied from 0.82-0.93 eV and from 0.75-1.05 eV, respectively [44]. Also, barrier height found here were reasonable agreement with a value of 0.97 eV from C-V characteristics of Au/n-GaAs and Ag/n-GaAs of nearly the same doping concentration [15].  Although the same parameter was measured, the difference between the Φb CV 's can be attributed to existence of lateral inhomogeneity [56]. The source of this lateral inhomogeneity was potential fluctuations at the interface. These fluctuations generally attributed to the thickness of the contact metal, non-uniform distribution at the interface, dislocations, packing errors in the crystal and a thin native oxide layer at the interface, irregularities in the atomic scale on the semiconductor surface, and defects in bulk, and so on [56,57]. These potential fluctuations affect the dc current and the capacitance measurements in different ways. Diode capacitance was caused by the displacement of the charge carriers in the space charge region due to the ac frequency signal. This displacement was observed at near the boundaries of the space charge region. Therefore, the capacitance of the diodes depends on this space charge region and causes the barrier height to be measured only as an average value. The dc current flowing through the diode preferably tends to flow only where the Φb CV was the lowest. Besides the I-V measurements, the using a single-frequency approximation method [58] on the conductance measurements results, allows the estimation of the Dit. This method was one of the reliable way to determine the density of interface states. According to this method, Dit CV can be find using the following formula, where Gm ω are measured conductance and angular frequency of ac signal, Cm is measured capacitance. Cox is the capacitance of oxide layer in accumulation region of C-V curves, (Gm)max conforms to maximum G-V curve and Cm is the capacitance of the diodes corresponding to (Gm)max. Also, the series resistance of the equivalent circuit is [58,59], This method was applied on C-V and G-V measurement results in the frequency range from 200 Hz to 2 MHz Figure 6 depicts the changings in Dit CV with the frequency, both axis is log scale. Dit CV values of Au-Ag/n-GaAs SDs strongly depend on frequencies and decrease at lower and higher frequency range. This "U" type behavior of the interface states has a minimum value that varies from diode to diode. This minimum value and sufficiently constant Dit CV values appear at relatively high frequencies attributed to the excess capacitance. This excess capacitance because of interface states which is in equilibrium with the semiconductor that can easily follow the ac signal [60]. Dit CV values of Au-Ag/n-GaAs SDs are same order as those reported by some authors. [50]. The frequency dependent series resistance values of Au-Ag/n-GaAs SDs estimated according to Equation (15) using with the measured capacitance and conductance values in the frequency range from 200Hz to 2MHz at room temperature and plotted in Figure 7. This plot clearly indicates that when the frequency decreased, interface states cannot follow the ac signal and each states produces an excess capacitance and conductance, and becomes a resistive point for charge carriers and increases exponentially. Inset in Figure 7 shows that series resistance gives a peak depending on frequency in the wide negative bias range and second peak appear after 0V.

Conclusion
In this study, Au-Ag/n-GaAs SDs fabricated by thermal evaporation method and investigated the effect of work function of metals on SD's parameters. TLM results indicates that Ohmic contact resistance was very low and EDX results indicates that the alloy's percentage (x) by weight values were 0.22, 0.37 and 0.71. Also, AFM images showed that the smooth contacts were made. AuxAg1-x (x=0, 0.22, 0.37, 0.71 and 1) alloys were used for fabricating SDs by following same cleaning procedure with using the n-type GaAs substrate and then, characterized by various methods and techniques. In addition, characteristic parameters of SDs have been determined and compared with each other.
The lowest mean barrier height of about 0.789±0.022 eV in Au/n-GaAs SDs and the highest mean barrier height 0.847±0.008 eV in Au0.71Ag0.29/n-GaAs SDs were observed (from I-V measurements). Φb values of Au/n-GaAs SDs were lower than the expected value and, explained by the presence of the gallide phases at the interface. It was observed that the Ag was prevents the Au diffusion in to the GaAs substrate or out diffusion of Ga. Furthermore, it was found that an almost linear relationship between Schottky barrier height and metal work function (with Φ = 0.0526 + 0.577). Gap states parameter (S) found as a 0.0526 and, close to the Bardeen limit (S=0). In summary, Fermi level pinning model proposed by Cowley and Sze applies not only to metal-GaAs contacts but also to alloy-GaAs contacts, and indicates that Fermi level was strongly pinned 0.577 eV below the conduction band in our SD's. Also, from this dependency, the density of states was determined as 1.801x10 11 eVcm -2 . This interface state density value was in the same order of magnitude with the Dit IV values (calculated from I-V measurement result) and Dit CV values (calculated from C-V measurement result).